1 /* 2 * Copyright (c) 2023 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef HPM_MIPI_CSI_PHY_DRV_H 9 #define HPM_MIPI_CSI_PHY_DRV_H 10 11 /** 12 * @brief MIPI_CSI_PHY APIs 13 * @defgroup mipi_csi_phy_interface MIPI_CSI_PHY driver APIs 14 * @ingroup mipi_csi_phy_interfaces 15 * @{ 16 */ 17 18 #include "hpm_common.h" 19 #include "hpm_soc.h" 20 #include "hpm_mipi_csi_phy_regs.h" 21 22 23 typedef struct mipi_csi_phy_clane_config { 24 uint16_t t_term_en_ns; /* !< unit: nanosecond. Time for the Clock Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,MAX */ 25 uint16_t t_settle_ns; /* !< unit: nanosecond. Time interval during which the HS receiver should ignore any Clock Lane HS transitions, starting from the beginning of TCLK-PREPARE */ 26 } mipi_csi_phy_clane_config_t; 27 28 typedef struct mipi_csi_phy_dlane_config { 29 uint16_t t_term_en_ns; /* !< unit: nanosecond. Time for the Data Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,MAX */ 30 uint16_t t_settle_ns; /* !< unit: nanosecond. Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of THS-PREPARE */ 31 } mipi_csi_phy_dlane_config_t; 32 33 typedef struct mipi_csi_phy_config { 34 mipi_csi_phy_clane_config_t clane_cfg; /*!< clk lane config */ 35 mipi_csi_phy_dlane_config_t dlane_cfg; /*!< data lane config */ 36 } mipi_csi_phy_config_t; 37 38 39 40 /** 41 * @brief get MIPI CSI PHY of default config 42 * 43 * @param[out] cfg config of MIPI CSI PHY 44 */ 45 void mipi_csi_phy_default_config(mipi_csi_phy_config_t *cfg); 46 47 /** 48 * @brief MIPI_CSI_PHY init 49 * 50 * @param ptr MIPI_CSI_PHY base address 51 * @param cfg config of MIPI_CSI_PHY 52 */ 53 void mipi_csi_phy_init(MIPI_CSI_PHY_Type *ptr, mipi_csi_phy_config_t *cfg); 54 55 #ifdef __cplusplus 56 extern "C" { 57 #endif 58 59 60 #ifdef __cplusplus 61 } 62 #endif 63 64 /** 65 * @} 66 */ 67 #endif /* HPM_MIPI_CSI_PHY_DRV_H */ 68