1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_OPAMP_H
10 #define HPM_OPAMP_H
11 
12 typedef struct {
13     __RW uint32_t CTRL0;                       /* 0x0: control reg */
14     __RW uint32_t STATUS;                      /* 0x4: status reg */
15     __RW uint32_t CTRL1;                       /* 0x8: control reg1 */
16     __R  uint8_t  RESERVED0[4];                /* 0xC - 0xF: Reserved */
17     struct {
18         __RW uint32_t CFG0;                    /* 0x10:  */
19         __RW uint32_t CFG1;                    /* 0x14:  */
20         __RW uint32_t CFG2;                    /* 0x18:  */
21     } CFG[10];
22 } OPAMP_Type;
23 
24 
25 /* Bitfield definition for register: CTRL0 */
26 /*
27  * EN_LV (RW)
28  *
29  */
30 #define OPAMP_CTRL0_EN_LV_MASK (0x4000000UL)
31 #define OPAMP_CTRL0_EN_LV_SHIFT (26U)
32 #define OPAMP_CTRL0_EN_LV_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_EN_LV_SHIFT) & OPAMP_CTRL0_EN_LV_MASK)
33 #define OPAMP_CTRL0_EN_LV_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_EN_LV_MASK) >> OPAMP_CTRL0_EN_LV_SHIFT)
34 
35 /*
36  * VIM_SEL (RW)
37  *
38  */
39 #define OPAMP_CTRL0_VIM_SEL_MASK (0x70000UL)
40 #define OPAMP_CTRL0_VIM_SEL_SHIFT (16U)
41 #define OPAMP_CTRL0_VIM_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_VIM_SEL_SHIFT) & OPAMP_CTRL0_VIM_SEL_MASK)
42 #define OPAMP_CTRL0_VIM_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_VIM_SEL_MASK) >> OPAMP_CTRL0_VIM_SEL_SHIFT)
43 
44 /*
45  * MODE (RW)
46  *
47  */
48 #define OPAMP_CTRL0_MODE_MASK (0xF800U)
49 #define OPAMP_CTRL0_MODE_SHIFT (11U)
50 #define OPAMP_CTRL0_MODE_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_MODE_SHIFT) & OPAMP_CTRL0_MODE_MASK)
51 #define OPAMP_CTRL0_MODE_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_MODE_MASK) >> OPAMP_CTRL0_MODE_SHIFT)
52 
53 /*
54  * GAIN_SEL (RW)
55  *
56  */
57 #define OPAMP_CTRL0_GAIN_SEL_MASK (0x700U)
58 #define OPAMP_CTRL0_GAIN_SEL_SHIFT (8U)
59 #define OPAMP_CTRL0_GAIN_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_GAIN_SEL_SHIFT) & OPAMP_CTRL0_GAIN_SEL_MASK)
60 #define OPAMP_CTRL0_GAIN_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_GAIN_SEL_MASK) >> OPAMP_CTRL0_GAIN_SEL_SHIFT)
61 
62 /*
63  * DISABLE_PM_CAP (RW)
64  *
65  */
66 #define OPAMP_CTRL0_DISABLE_PM_CAP_MASK (0x80U)
67 #define OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT (7U)
68 #define OPAMP_CTRL0_DISABLE_PM_CAP_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT) & OPAMP_CTRL0_DISABLE_PM_CAP_MASK)
69 #define OPAMP_CTRL0_DISABLE_PM_CAP_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_DISABLE_PM_CAP_MASK) >> OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT)
70 
71 /*
72  * MILLER_SEL (RW)
73  *
74  */
75 #define OPAMP_CTRL0_MILLER_SEL_MASK (0x70U)
76 #define OPAMP_CTRL0_MILLER_SEL_SHIFT (4U)
77 #define OPAMP_CTRL0_MILLER_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_MILLER_SEL_SHIFT) & OPAMP_CTRL0_MILLER_SEL_MASK)
78 #define OPAMP_CTRL0_MILLER_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_MILLER_SEL_MASK) >> OPAMP_CTRL0_MILLER_SEL_SHIFT)
79 
80 /*
81  * VBYPASS (RW)
82  *
83  */
84 #define OPAMP_CTRL0_VBYPASS_MASK (0x8U)
85 #define OPAMP_CTRL0_VBYPASS_SHIFT (3U)
86 #define OPAMP_CTRL0_VBYPASS_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_VBYPASS_SHIFT) & OPAMP_CTRL0_VBYPASS_MASK)
87 #define OPAMP_CTRL0_VBYPASS_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_VBYPASS_MASK) >> OPAMP_CTRL0_VBYPASS_SHIFT)
88 
89 /*
90  * VIP_SEL (RW)
91  *
92  */
93 #define OPAMP_CTRL0_VIP_SEL_MASK (0x7U)
94 #define OPAMP_CTRL0_VIP_SEL_SHIFT (0U)
95 #define OPAMP_CTRL0_VIP_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_VIP_SEL_SHIFT) & OPAMP_CTRL0_VIP_SEL_MASK)
96 #define OPAMP_CTRL0_VIP_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_VIP_SEL_MASK) >> OPAMP_CTRL0_VIP_SEL_SHIFT)
97 
98 /* Bitfield definition for register: STATUS */
99 /*
100  * TRIG_CONFLICT (RWC)
101  *
102  * if more than one hardware trigger is set, will put all trigger input here;
103  * write any value to clear
104  */
105 #define OPAMP_STATUS_TRIG_CONFLICT_MASK (0xFF00000UL)
106 #define OPAMP_STATUS_TRIG_CONFLICT_SHIFT (20U)
107 #define OPAMP_STATUS_TRIG_CONFLICT_SET(x) (((uint32_t)(x) << OPAMP_STATUS_TRIG_CONFLICT_SHIFT) & OPAMP_STATUS_TRIG_CONFLICT_MASK)
108 #define OPAMP_STATUS_TRIG_CONFLICT_GET(x) (((uint32_t)(x) & OPAMP_STATUS_TRIG_CONFLICT_MASK) >> OPAMP_STATUS_TRIG_CONFLICT_SHIFT)
109 
110 /*
111  * PRESET_ACT (RO)
112  *
113  * 1 for preset active; one of cur_preset is selected for OPAMP;
114  * 0 for no preset, OPAMP use cfg0 parameters
115  */
116 #define OPAMP_STATUS_PRESET_ACT_MASK (0x80000UL)
117 #define OPAMP_STATUS_PRESET_ACT_SHIFT (19U)
118 #define OPAMP_STATUS_PRESET_ACT_GET(x) (((uint32_t)(x) & OPAMP_STATUS_PRESET_ACT_MASK) >> OPAMP_STATUS_PRESET_ACT_SHIFT)
119 
120 /*
121  * CUR_PRESET (RO)
122  *
123  * current selected preset
124  */
125 #define OPAMP_STATUS_CUR_PRESET_MASK (0x70000UL)
126 #define OPAMP_STATUS_CUR_PRESET_SHIFT (16U)
127 #define OPAMP_STATUS_CUR_PRESET_GET(x) (((uint32_t)(x) & OPAMP_STATUS_CUR_PRESET_MASK) >> OPAMP_STATUS_CUR_PRESET_SHIFT)
128 
129 /* Bitfield definition for register: CTRL1 */
130 /*
131  * SW_PRESET (RW)
132  *
133  * set to use preset defined by sw_sel.
134  * NOTE: when set, the hardware trigger will not be used
135  */
136 #define OPAMP_CTRL1_SW_PRESET_MASK (0x80000000UL)
137 #define OPAMP_CTRL1_SW_PRESET_SHIFT (31U)
138 #define OPAMP_CTRL1_SW_PRESET_SET(x) (((uint32_t)(x) << OPAMP_CTRL1_SW_PRESET_SHIFT) & OPAMP_CTRL1_SW_PRESET_MASK)
139 #define OPAMP_CTRL1_SW_PRESET_GET(x) (((uint32_t)(x) & OPAMP_CTRL1_SW_PRESET_MASK) >> OPAMP_CTRL1_SW_PRESET_SHIFT)
140 
141 /*
142  * SW_SEL (RW)
143  *
144  */
145 #define OPAMP_CTRL1_SW_SEL_MASK (0x7U)
146 #define OPAMP_CTRL1_SW_SEL_SHIFT (0U)
147 #define OPAMP_CTRL1_SW_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL1_SW_SEL_SHIFT) & OPAMP_CTRL1_SW_SEL_MASK)
148 #define OPAMP_CTRL1_SW_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL1_SW_SEL_MASK) >> OPAMP_CTRL1_SW_SEL_SHIFT)
149 
150 /* Bitfield definition for register of struct array CFG: CFG0 */
151 /*
152  * DISABLE_PM_CAP (RW)
153  *
154  */
155 #define OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK (0x8000000UL)
156 #define OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT (27U)
157 #define OPAMP_CFG_CFG0_DISABLE_PM_CAP_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT) & OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK)
158 #define OPAMP_CFG_CFG0_DISABLE_PM_CAP_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK) >> OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT)
159 
160 /*
161  * MILLER_SEL (RW)
162  *
163  */
164 #define OPAMP_CFG_CFG0_MILLER_SEL_MASK (0x7000000UL)
165 #define OPAMP_CFG_CFG0_MILLER_SEL_SHIFT (24U)
166 #define OPAMP_CFG_CFG0_MILLER_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_MILLER_SEL_SHIFT) & OPAMP_CFG_CFG0_MILLER_SEL_MASK)
167 #define OPAMP_CFG_CFG0_MILLER_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_MILLER_SEL_MASK) >> OPAMP_CFG_CFG0_MILLER_SEL_SHIFT)
168 
169 /*
170  * VIM_SEL (RW)
171  *
172  */
173 #define OPAMP_CFG_CFG0_VIM_SEL_MASK (0x700U)
174 #define OPAMP_CFG_CFG0_VIM_SEL_SHIFT (8U)
175 #define OPAMP_CFG_CFG0_VIM_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_VIM_SEL_SHIFT) & OPAMP_CFG_CFG0_VIM_SEL_MASK)
176 #define OPAMP_CFG_CFG0_VIM_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_VIM_SEL_MASK) >> OPAMP_CFG_CFG0_VIM_SEL_SHIFT)
177 
178 /*
179  * VIP_SEL (RW)
180  *
181  */
182 #define OPAMP_CFG_CFG0_VIP_SEL_MASK (0x7U)
183 #define OPAMP_CFG_CFG0_VIP_SEL_SHIFT (0U)
184 #define OPAMP_CFG_CFG0_VIP_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_VIP_SEL_SHIFT) & OPAMP_CFG_CFG0_VIP_SEL_MASK)
185 #define OPAMP_CFG_CFG0_VIP_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_VIP_SEL_MASK) >> OPAMP_CFG_CFG0_VIP_SEL_SHIFT)
186 
187 /* Bitfield definition for register of struct array CFG: CFG1 */
188 /*
189  * HW_TRIG_EN (RW)
190  *
191  * set to enable hardware trigger from moto system.
192  * NOTE: when sw_preset is enabled, this bit will not take effert
193  */
194 #define OPAMP_CFG_CFG1_HW_TRIG_EN_MASK (0x80000000UL)
195 #define OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT (31U)
196 #define OPAMP_CFG_CFG1_HW_TRIG_EN_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT) & OPAMP_CFG_CFG1_HW_TRIG_EN_MASK)
197 #define OPAMP_CFG_CFG1_HW_TRIG_EN_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_HW_TRIG_EN_MASK) >> OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT)
198 
199 /*
200  * EN_LV (RW)
201  *
202  */
203 #define OPAMP_CFG_CFG1_EN_LV_MASK (0x40000000UL)
204 #define OPAMP_CFG_CFG1_EN_LV_SHIFT (30U)
205 #define OPAMP_CFG_CFG1_EN_LV_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_EN_LV_SHIFT) & OPAMP_CFG_CFG1_EN_LV_MASK)
206 #define OPAMP_CFG_CFG1_EN_LV_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_EN_LV_MASK) >> OPAMP_CFG_CFG1_EN_LV_SHIFT)
207 
208 /*
209  * VBYPASS_LV (RW)
210  *
211  */
212 #define OPAMP_CFG_CFG1_VBYPASS_LV_MASK (0x20000000UL)
213 #define OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT (29U)
214 #define OPAMP_CFG_CFG1_VBYPASS_LV_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT) & OPAMP_CFG_CFG1_VBYPASS_LV_MASK)
215 #define OPAMP_CFG_CFG1_VBYPASS_LV_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_VBYPASS_LV_MASK) >> OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT)
216 
217 /*
218  * MODE (RW)
219  *
220  */
221 #define OPAMP_CFG_CFG1_MODE_MASK (0xF8U)
222 #define OPAMP_CFG_CFG1_MODE_SHIFT (3U)
223 #define OPAMP_CFG_CFG1_MODE_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_MODE_SHIFT) & OPAMP_CFG_CFG1_MODE_MASK)
224 #define OPAMP_CFG_CFG1_MODE_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_MODE_MASK) >> OPAMP_CFG_CFG1_MODE_SHIFT)
225 
226 /*
227  * GAIN_SEL (RW)
228  *
229  */
230 #define OPAMP_CFG_CFG1_GAIN_SEL_MASK (0x7U)
231 #define OPAMP_CFG_CFG1_GAIN_SEL_SHIFT (0U)
232 #define OPAMP_CFG_CFG1_GAIN_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_GAIN_SEL_SHIFT) & OPAMP_CFG_CFG1_GAIN_SEL_MASK)
233 #define OPAMP_CFG_CFG1_GAIN_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_GAIN_SEL_MASK) >> OPAMP_CFG_CFG1_GAIN_SEL_SHIFT)
234 
235 /* Bitfield definition for register of struct array CFG: CFG2 */
236 /*
237  * CHANNEL (RW)
238  *
239  */
240 #define OPAMP_CFG_CFG2_CHANNEL_MASK (0x7000000UL)
241 #define OPAMP_CFG_CFG2_CHANNEL_SHIFT (24U)
242 #define OPAMP_CFG_CFG2_CHANNEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG2_CHANNEL_SHIFT) & OPAMP_CFG_CFG2_CHANNEL_MASK)
243 #define OPAMP_CFG_CFG2_CHANNEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG2_CHANNEL_MASK) >> OPAMP_CFG_CFG2_CHANNEL_SHIFT)
244 
245 
246 
247 /* CFG register group index macro definition */
248 #define OPAMP_CFG_PRESET0 (0UL)
249 #define OPAMP_CFG_PRESET1 (1UL)
250 #define OPAMP_CFG_PRESET2 (2UL)
251 #define OPAMP_CFG_PRESET3 (4UL)
252 #define OPAMP_CFG_PRESET4 (5UL)
253 #define OPAMP_CFG_PRESET5 (6UL)
254 #define OPAMP_CFG_PRESET6 (8UL)
255 #define OPAMP_CFG_PRESET7 (9UL)
256 
257 
258 #endif /* HPM_OPAMP_H */
259