1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_RTL8201_REGS_H
10 #define HPM_RTL8201_REGS_H
11 
12 typedef enum {
13     RTL8201_BMCR                        = 0,   /* 0x0: Basic Mode Control Register */
14     RTL8201_BMSR                        = 1,   /* 0x1: Basic Mode Status Register */
15     RTL8201_PHYID1                      = 2,   /* 0x2: PHY Identifier Register 1 */
16     RTL8201_PHYID2                      = 3,   /* 0x3: PHY Identifier Register 2 */
17     RTL8201_RMSR_P7                     = 16,  /* 0x10: RMII Mode Setting Register */
18     RTL8201_PAGESEL                     = 31,  /* 0x1F: Page Select Register */
19 } RTL8201_REG_Type;
20 
21 
22 /* Bitfield definition for register: BMCR */
23 /*
24  * RESET (RW/SC)
25  *
26  * This bit sets the status and control registers of the PHY in the
27  * default state. This bit is self-clearing.
28  * 1: Software reset  0: Normal operation
29  * Register 0 and register 1 will return to default values after a
30  * software reset (set Bit15 to 1).
31  * This action may change the internal PHY state and the state of the
32  * physical link associated with the PHY.
33  */
34 #define RTL8201_BMCR_RESET_MASK (0x8000U)
35 #define RTL8201_BMCR_RESET_SHIFT (15U)
36 #define RTL8201_BMCR_RESET_SET(x) (((uint16_t)(x) << RTL8201_BMCR_RESET_SHIFT) & RTL8201_BMCR_RESET_MASK)
37 #define RTL8201_BMCR_RESET_GET(x) (((uint16_t)(x) & RTL8201_BMCR_RESET_MASK) >> RTL8201_BMCR_RESET_SHIFT)
38 
39 /*
40  * LOOPBACK (RW)
41  *
42  * This bit enables loopback of transmit data nibbles TXD3:0 to the
43  * receive data path.
44  * 1: Enable loopback  0: Normal operation
45  */
46 #define RTL8201_BMCR_LOOPBACK_MASK (0x4000U)
47 #define RTL8201_BMCR_LOOPBACK_SHIFT (14U)
48 #define RTL8201_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << RTL8201_BMCR_LOOPBACK_SHIFT) & RTL8201_BMCR_LOOPBACK_MASK)
49 #define RTL8201_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & RTL8201_BMCR_LOOPBACK_MASK) >> RTL8201_BMCR_LOOPBACK_SHIFT)
50 
51 /*
52  * SPEED0 (RW)
53  *
54  * This bit sets the network speed.
55  * 1: 100Mbps  0: 10Mbps
56  * After completing auto negotiation, this bit will reflect the speed
57  * status.
58  * 1: 100Base-T  0: 10Base-T
59  * When 100Base-FX mode is enabled, this bit=1 and is read only.
60  */
61 #define RTL8201_BMCR_SPEED0_MASK (0x2000U)
62 #define RTL8201_BMCR_SPEED0_SHIFT (13U)
63 #define RTL8201_BMCR_SPEED0_SET(x) (((uint16_t)(x) << RTL8201_BMCR_SPEED0_SHIFT) & RTL8201_BMCR_SPEED0_MASK)
64 #define RTL8201_BMCR_SPEED0_GET(x) (((uint16_t)(x) & RTL8201_BMCR_SPEED0_MASK) >> RTL8201_BMCR_SPEED0_SHIFT)
65 
66 /*
67  * ANE (RW)
68  *
69  * This bit enables/disables the NWay auto-negotiation function.
70  * 1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored
71  * 0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the
72  * link speed and the data transfer mode, respectively
73  * When 100Base-FX mode is enabled, this bit=0 and is read only.
74  */
75 #define RTL8201_BMCR_ANE_MASK (0x1000U)
76 #define RTL8201_BMCR_ANE_SHIFT (12U)
77 #define RTL8201_BMCR_ANE_SET(x) (((uint16_t)(x) << RTL8201_BMCR_ANE_SHIFT) & RTL8201_BMCR_ANE_MASK)
78 #define RTL8201_BMCR_ANE_GET(x) (((uint16_t)(x) & RTL8201_BMCR_ANE_MASK) >> RTL8201_BMCR_ANE_SHIFT)
79 
80 /*
81  * PWD (RW)
82  *
83  * This bit turns down the power of the PHY chip, including the
84  * internal crystal oscillator circuit.
85  * The MDC, MDIO is still alive for accessing the MAC.
86  * 1: Power down  0: Normal operation
87  */
88 #define RTL8201_BMCR_PWD_MASK (0x800U)
89 #define RTL8201_BMCR_PWD_SHIFT (11U)
90 #define RTL8201_BMCR_PWD_SET(x) (((uint16_t)(x) << RTL8201_BMCR_PWD_SHIFT) & RTL8201_BMCR_PWD_MASK)
91 #define RTL8201_BMCR_PWD_GET(x) (((uint16_t)(x) & RTL8201_BMCR_PWD_MASK) >> RTL8201_BMCR_PWD_SHIFT)
92 
93 /*
94  * ISOLATE (RW)
95  *
96  * 1: Electrically isolate the PHY from MII/GMII/RGMII/RSGMII.
97  * PHY is still able to respond to MDC/MDIO.
98  * 0: Normal operation
99  */
100 #define RTL8201_BMCR_ISOLATE_MASK (0x400U)
101 #define RTL8201_BMCR_ISOLATE_SHIFT (10U)
102 #define RTL8201_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << RTL8201_BMCR_ISOLATE_SHIFT) & RTL8201_BMCR_ISOLATE_MASK)
103 #define RTL8201_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & RTL8201_BMCR_ISOLATE_MASK) >> RTL8201_BMCR_ISOLATE_SHIFT)
104 
105 /*
106  * RESTART_AN (RW/SC)
107  *
108  * This bit allows the NWay auto-negotiation function to be reset.
109  * 1: Re-start auto-negotiation  0: Normal operation
110  */
111 #define RTL8201_BMCR_RESTART_AN_MASK (0x200U)
112 #define RTL8201_BMCR_RESTART_AN_SHIFT (9U)
113 #define RTL8201_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << RTL8201_BMCR_RESTART_AN_SHIFT) & RTL8201_BMCR_RESTART_AN_MASK)
114 #define RTL8201_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & RTL8201_BMCR_RESTART_AN_MASK) >> RTL8201_BMCR_RESTART_AN_SHIFT)
115 
116 /*
117  * DUPLEX (RW)
118  *
119  * This bit sets the duplex mode if auto-negotiation is disabled (bit
120  * 0:12=0).
121  * 1: Full duplex  0: Half duplex
122  * After completing auto-negotiation, this bit will reflect the duplex
123  * status.
124  * 1: Full duplex  0: Half duplex
125  */
126 #define RTL8201_BMCR_DUPLEX_MASK (0x100U)
127 #define RTL8201_BMCR_DUPLEX_SHIFT (8U)
128 #define RTL8201_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << RTL8201_BMCR_DUPLEX_SHIFT) & RTL8201_BMCR_DUPLEX_MASK)
129 #define RTL8201_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & RTL8201_BMCR_DUPLEX_MASK) >> RTL8201_BMCR_DUPLEX_SHIFT)
130 
131 /*
132  * COLLISION_TEST (RW)
133  *
134  * Collision Test.
135  * 1: Collision test enabled
136  * 0: Normal operation
137  * When set, this bit will cause the COL signal to be asserted in
138  * response to the TXEN assertion within 512-bit times. The COL
139  * signal will be de-asserted within 4-bit times in response to the
140  * TXEN de-assertion.
141  */
142 #define RTL8201_BMCR_COLLISION_TEST_MASK (0x80U)
143 #define RTL8201_BMCR_COLLISION_TEST_SHIFT (7U)
144 #define RTL8201_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << RTL8201_BMCR_COLLISION_TEST_SHIFT) & RTL8201_BMCR_COLLISION_TEST_MASK)
145 #define RTL8201_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & RTL8201_BMCR_COLLISION_TEST_MASK) >> RTL8201_BMCR_COLLISION_TEST_SHIFT)
146 
147 /*
148  * SPEED1 (RW)
149  *
150  * Speed Select Bit 1.
151  * Refer to bit 13.
152  */
153 #define RTL8201_BMCR_SPEED1_MASK (0x40U)
154 #define RTL8201_BMCR_SPEED1_SHIFT (6U)
155 #define RTL8201_BMCR_SPEED1_SET(x) (((uint16_t)(x) << RTL8201_BMCR_SPEED1_SHIFT) & RTL8201_BMCR_SPEED1_MASK)
156 #define RTL8201_BMCR_SPEED1_GET(x) (((uint16_t)(x) & RTL8201_BMCR_SPEED1_MASK) >> RTL8201_BMCR_SPEED1_SHIFT)
157 
158 /* Bitfield definition for register: BMSR */
159 /*
160  * 100BASE_T4 (RO)
161  *
162  * 1: Enable 100Base-T4 support
163  * 0: Suppress 100Base-T4 support
164  */
165 #define RTL8201_BMSR_100BASE_T4_MASK (0x8000U)
166 #define RTL8201_BMSR_100BASE_T4_SHIFT (15U)
167 #define RTL8201_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & RTL8201_BMSR_100BASE_T4_MASK) >> RTL8201_BMSR_100BASE_T4_SHIFT)
168 
169 /*
170  * 100BASE_TX_FULL (RO)
171  *
172  * 1: Enable 100Base-TX full duplex support
173  * 0: Suppress 100Base-TX full duplex support
174  */
175 #define RTL8201_BMSR_100BASE_TX_FULL_MASK (0x4000U)
176 #define RTL8201_BMSR_100BASE_TX_FULL_SHIFT (14U)
177 #define RTL8201_BMSR_100BASE_TX_FULL_GET(x) (((uint16_t)(x) & RTL8201_BMSR_100BASE_TX_FULL_MASK) >> RTL8201_BMSR_100BASE_TX_FULL_SHIFT)
178 
179 /*
180  * 100BASE_TX_HALF (RO)
181  *
182  * 1: Enable 100Base-TX half duplex support
183  * 0: Suppress 100Base-TX half duplex support
184  */
185 #define RTL8201_BMSR_100BASE_TX_HALF_MASK (0x2000U)
186 #define RTL8201_BMSR_100BASE_TX_HALF_SHIFT (13U)
187 #define RTL8201_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & RTL8201_BMSR_100BASE_TX_HALF_MASK) >> RTL8201_BMSR_100BASE_TX_HALF_SHIFT)
188 
189 /*
190  * 10BASE_T_FULL (RO)
191  *
192  * 1: Enable 10Base-T full duplex support
193  * 0: Suppress 10Base-T full duplex support
194  */
195 #define RTL8201_BMSR_10BASE_T_FULL_MASK (0x1000U)
196 #define RTL8201_BMSR_10BASE_T_FULL_SHIFT (12U)
197 #define RTL8201_BMSR_10BASE_T_FULL_GET(x) (((uint16_t)(x) & RTL8201_BMSR_10BASE_T_FULL_MASK) >> RTL8201_BMSR_10BASE_T_FULL_SHIFT)
198 
199 /*
200  * 10BASE_T_HALF (RO)
201  *
202  * 1: Enable 10Base-T half duplex support
203  * 0: Suppress 10Base-T half duplex support
204  */
205 #define RTL8201_BMSR_10BASE_T_HALF_MASK (0x800U)
206 #define RTL8201_BMSR_10BASE_T_HALF_SHIFT (11U)
207 #define RTL8201_BMSR_10BASE_T_HALF_GET(x) (((uint16_t)(x) & RTL8201_BMSR_10BASE_T_HALF_MASK) >> RTL8201_BMSR_10BASE_T_HALF_SHIFT)
208 
209 /*
210  * PREAMBLE_SUPPRESSION (RO)
211  *
212  * The RTL8201F/FL/FN will accept management frames
213  * with preamble suppressed.
214  * A minimum of 32 preamble bits are required for the first
215  * management interface read/write transaction after reset.
216  * One idle bit is required between any two management
217  * transactions as per IEEE 802.3u specifications.
218  */
219 #define RTL8201_BMSR_PREAMBLE_SUPPRESSION_MASK (0x40U)
220 #define RTL8201_BMSR_PREAMBLE_SUPPRESSION_SHIFT (6U)
221 #define RTL8201_BMSR_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & RTL8201_BMSR_PREAMBLE_SUPPRESSION_MASK) >> RTL8201_BMSR_PREAMBLE_SUPPRESSION_SHIFT)
222 
223 /*
224  * AUTO_NEGOTIATION_COMPLETE (RO)
225  *
226  * 1: Auto-negotiation process completed
227  * 0: Auto-negotiation process not completed
228  */
229 #define RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U)
230 #define RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U)
231 #define RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT)
232 
233 /*
234  * REMOTE_FAULT (RC)
235  *
236  * 1: Remote fault condition detected (cleared on read)
237  * 0: No remote fault condition detected
238  * When in 100Base-FX mode, this bit means an in-band
239  * signal Far-End-Fault has been detected (see 8.10 Far End
240  * Fault Indication, page 39).
241  */
242 #define RTL8201_BMSR_REMOTE_FAULT_MASK (0x10U)
243 #define RTL8201_BMSR_REMOTE_FAULT_SHIFT (4U)
244 #define RTL8201_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & RTL8201_BMSR_REMOTE_FAULT_MASK) >> RTL8201_BMSR_REMOTE_FAULT_SHIFT)
245 
246 /*
247  * AUTO_NEGOTIATION_ABILITY (RO)
248  *
249  * 1: PHY is able to perform auto-negotiation
250  * 0: PHY is not able to perform auto-negotiation
251  */
252 #define RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U)
253 #define RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U)
254 #define RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT)
255 
256 /*
257  * LINK_STATUS (RO)
258  *
259  * 1: Valid link established
260  * 0: No valid link established
261  * This bit indicates whether the link was lost since the last
262  * read. For the current link status, read this register twice.
263  */
264 #define RTL8201_BMSR_LINK_STATUS_MASK (0x4U)
265 #define RTL8201_BMSR_LINK_STATUS_SHIFT (2U)
266 #define RTL8201_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & RTL8201_BMSR_LINK_STATUS_MASK) >> RTL8201_BMSR_LINK_STATUS_SHIFT)
267 
268 /*
269  * JABBER_DETECT (RO)
270  *
271  * 1: Jabber condition detected
272  * 0: No jabber condition detected
273  */
274 #define RTL8201_BMSR_JABBER_DETECT_MASK (0x2U)
275 #define RTL8201_BMSR_JABBER_DETECT_SHIFT (1U)
276 #define RTL8201_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & RTL8201_BMSR_JABBER_DETECT_MASK) >> RTL8201_BMSR_JABBER_DETECT_SHIFT)
277 
278 /*
279  * EXTENDED_CAPABILITY (RO)
280  *
281  * 1: Extended register capable (permanently=1)
282  * 0: Not extended register capable
283  */
284 #define RTL8201_BMSR_EXTENDED_CAPABILITY_MASK (0x1U)
285 #define RTL8201_BMSR_EXTENDED_CAPABILITY_SHIFT (0U)
286 #define RTL8201_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & RTL8201_BMSR_EXTENDED_CAPABILITY_MASK) >> RTL8201_BMSR_EXTENDED_CAPABILITY_SHIFT)
287 
288 /* Bitfield definition for register: PHYID1 */
289 /*
290  * OUI_MSB (RO)
291  *
292  * Composed of the 6 th  to 21 st  bits of the Organizationally Unique
293  * Identifier (OUI), respectively.
294  */
295 #define RTL8201_PHYID1_OUI_MSB_MASK (0xFFFFU)
296 #define RTL8201_PHYID1_OUI_MSB_SHIFT (0U)
297 #define RTL8201_PHYID1_OUI_MSB_GET(x) (((uint16_t)(x) & RTL8201_PHYID1_OUI_MSB_MASK) >> RTL8201_PHYID1_OUI_MSB_SHIFT)
298 
299 /* Bitfield definition for register: PHYID2 */
300 /*
301  * OUI_LSB (RO)
302  *
303  * Assigned to the 0 through 5 th  bits of the OUI.  RO  110010
304  */
305 #define RTL8201_PHYID2_OUI_LSB_MASK (0xFC00U)
306 #define RTL8201_PHYID2_OUI_LSB_SHIFT (10U)
307 #define RTL8201_PHYID2_OUI_LSB_GET(x) (((uint16_t)(x) & RTL8201_PHYID2_OUI_LSB_MASK) >> RTL8201_PHYID2_OUI_LSB_SHIFT)
308 
309 /*
310  * MODEL_NUMBER (RO)
311  *
312  * Model Number
313  */
314 #define RTL8201_PHYID2_MODEL_NUMBER_MASK (0x3F0U)
315 #define RTL8201_PHYID2_MODEL_NUMBER_SHIFT (4U)
316 #define RTL8201_PHYID2_MODEL_NUMBER_GET(x) (((uint16_t)(x) & RTL8201_PHYID2_MODEL_NUMBER_MASK) >> RTL8201_PHYID2_MODEL_NUMBER_SHIFT)
317 
318 /*
319  * REVISION_NUMBER (RO)
320  *
321  * Revision Number
322  */
323 #define RTL8201_PHYID2_REVISION_NUMBER_MASK (0xFU)
324 #define RTL8201_PHYID2_REVISION_NUMBER_SHIFT (0U)
325 #define RTL8201_PHYID2_REVISION_NUMBER_GET(x) (((uint16_t)(x) & RTL8201_PHYID2_REVISION_NUMBER_MASK) >> RTL8201_PHYID2_REVISION_NUMBER_SHIFT)
326 
327 /* Bitfield definition for register: RMSR_P7 */
328 /*
329  * RG_RMII_CLKDIR (RW)
330  *
331  * This Bit Sets the Type of TXC in RMII Mode.
332  * 0: Output
333  * 1: Input
334  */
335 #define RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK (0x1000U)
336 #define RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT (12U)
337 #define RTL8201_RMSR_P7_RG_RMII_CLKDIR_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT) & RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK)
338 #define RTL8201_RMSR_P7_RG_RMII_CLKDIR_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK) >> RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT)
339 
340 /*
341  * RG_RMII_TX_OFFSET (RW)
342  *
343  * Adjust RMII TX Interface Timing.
344  */
345 #define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_MASK (0xF00U)
346 #define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SHIFT (8U)
347 #define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SHIFT) & RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_MASK)
348 #define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_MASK) >> RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SHIFT)
349 
350 /*
351  * RG_RMII_RX_OFFSET (RW)
352  *
353  * Adjust RMII RX Interface Timing.
354  */
355 #define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_MASK (0xF0U)
356 #define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SHIFT (4U)
357 #define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SHIFT) & RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_MASK)
358 #define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_MASK) >> RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SHIFT)
359 
360 /*
361  * RMII_MODE (RW)
362  *
363  * 0: MII Mode
364  * 1: RMII Mode
365  */
366 #define RTL8201_RMSR_P7_RMII_MODE_MASK (0x8U)
367 #define RTL8201_RMSR_P7_RMII_MODE_SHIFT (3U)
368 #define RTL8201_RMSR_P7_RMII_MODE_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RMII_MODE_SHIFT) & RTL8201_RMSR_P7_RMII_MODE_MASK)
369 #define RTL8201_RMSR_P7_RMII_MODE_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RMII_MODE_MASK) >> RTL8201_RMSR_P7_RMII_MODE_SHIFT)
370 
371 /*
372  * RG_RMII_RXDV_SEL (RW)
373  *
374  * 0: CRS/CRS_DV pin is CRS_DV signal
375  * 1: CRS/CRS_DV pin is RXDV signal
376  */
377 #define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_MASK (0x4U)
378 #define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SHIFT (2U)
379 #define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SHIFT) & RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_MASK)
380 #define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_MASK) >> RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SHIFT)
381 
382 /*
383  * RG_RMII_RXDSEL (RW)
384  *
385  * 0: RMII data only
386  * 1: RMII data with SSD Error
387  */
388 #define RTL8201_RMSR_P7_RG_RMII_RXDSEL_MASK (0x2U)
389 #define RTL8201_RMSR_P7_RG_RMII_RXDSEL_SHIFT (1U)
390 #define RTL8201_RMSR_P7_RG_RMII_RXDSEL_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_RXDSEL_SHIFT) & RTL8201_RMSR_P7_RG_RMII_RXDSEL_MASK)
391 #define RTL8201_RMSR_P7_RG_RMII_RXDSEL_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_RXDSEL_MASK) >> RTL8201_RMSR_P7_RG_RMII_RXDSEL_SHIFT)
392 
393 /* Bitfield definition for register: PAGESEL */
394 /*
395  * PAGE_SEL (RW)
396  *
397  * Select Page Address: 00000000~11111111.
398  */
399 #define RTL8201_PAGESEL_PAGE_SEL_MASK (0xFFU)
400 #define RTL8201_PAGESEL_PAGE_SEL_SHIFT (0U)
401 #define RTL8201_PAGESEL_PAGE_SEL_SET(x) (((uint16_t)(x) << RTL8201_PAGESEL_PAGE_SEL_SHIFT) & RTL8201_PAGESEL_PAGE_SEL_MASK)
402 #define RTL8201_PAGESEL_PAGE_SEL_GET(x) (((uint16_t)(x) & RTL8201_PAGESEL_PAGE_SEL_MASK) >> RTL8201_PAGESEL_PAGE_SEL_SHIFT)
403 
404 
405 
406 
407 #endif /* HPM_RTL8201_REGS_H */
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