1 /**
2 * \file
3 *
4 * \brief SAM RAMECC
5 *
6 * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Subject to your compliance with these terms, you may use Microchip
13 * software and any derivatives exclusively with Microchip products.
14 * It is your responsibility to comply with third party license terms applicable
15 * to your use of third party software (including open source software) that
16 * may accompany Microchip software.
17 *
18 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
19 * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
20 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
21 * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
22 * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
23 * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
24 * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
25 * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
26 * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
27 * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
28 * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
29 *
30 * \asf_license_stop
31 *
32 */
33
34 #ifdef _SAME54_RAMECC_COMPONENT_
35 #ifndef _HRI_RAMECC_E54_H_INCLUDED_
36 #define _HRI_RAMECC_E54_H_INCLUDED_
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 #include <stdbool.h>
43 #include <hal_atomic.h>
44
45 #if defined(ENABLE_RAMECC_CRITICAL_SECTIONS)
46 #define RAMECC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
47 #define RAMECC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
48 #else
49 #define RAMECC_CRITICAL_SECTION_ENTER()
50 #define RAMECC_CRITICAL_SECTION_LEAVE()
51 #endif
52
53 typedef uint32_t hri_ramecc_erraddr_reg_t;
54 typedef uint8_t hri_ramecc_dbgctrl_reg_t;
55 typedef uint8_t hri_ramecc_intenset_reg_t;
56 typedef uint8_t hri_ramecc_intflag_reg_t;
57 typedef uint8_t hri_ramecc_status_reg_t;
58
hri_ramecc_get_INTFLAG_SINGLEE_bit(const void * const hw)59 static inline bool hri_ramecc_get_INTFLAG_SINGLEE_bit(const void *const hw)
60 {
61 return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos;
62 }
63
hri_ramecc_clear_INTFLAG_SINGLEE_bit(const void * const hw)64 static inline void hri_ramecc_clear_INTFLAG_SINGLEE_bit(const void *const hw)
65 {
66 ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE;
67 }
68
hri_ramecc_get_INTFLAG_DUALE_bit(const void * const hw)69 static inline bool hri_ramecc_get_INTFLAG_DUALE_bit(const void *const hw)
70 {
71 return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos;
72 }
73
hri_ramecc_clear_INTFLAG_DUALE_bit(const void * const hw)74 static inline void hri_ramecc_clear_INTFLAG_DUALE_bit(const void *const hw)
75 {
76 ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE;
77 }
78
hri_ramecc_get_interrupt_SINGLEE_bit(const void * const hw)79 static inline bool hri_ramecc_get_interrupt_SINGLEE_bit(const void *const hw)
80 {
81 return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos;
82 }
83
hri_ramecc_clear_interrupt_SINGLEE_bit(const void * const hw)84 static inline void hri_ramecc_clear_interrupt_SINGLEE_bit(const void *const hw)
85 {
86 ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE;
87 }
88
hri_ramecc_get_interrupt_DUALE_bit(const void * const hw)89 static inline bool hri_ramecc_get_interrupt_DUALE_bit(const void *const hw)
90 {
91 return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos;
92 }
93
hri_ramecc_clear_interrupt_DUALE_bit(const void * const hw)94 static inline void hri_ramecc_clear_interrupt_DUALE_bit(const void *const hw)
95 {
96 ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE;
97 }
98
hri_ramecc_get_INTFLAG_reg(const void * const hw,hri_ramecc_intflag_reg_t mask)99 static inline hri_ramecc_intflag_reg_t hri_ramecc_get_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask)
100 {
101 uint8_t tmp;
102 tmp = ((Ramecc *)hw)->INTFLAG.reg;
103 tmp &= mask;
104 return tmp;
105 }
106
hri_ramecc_read_INTFLAG_reg(const void * const hw)107 static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw)
108 {
109 return ((Ramecc *)hw)->INTFLAG.reg;
110 }
111
hri_ramecc_clear_INTFLAG_reg(const void * const hw,hri_ramecc_intflag_reg_t mask)112 static inline void hri_ramecc_clear_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask)
113 {
114 ((Ramecc *)hw)->INTFLAG.reg = mask;
115 }
116
hri_ramecc_set_INTEN_SINGLEE_bit(const void * const hw)117 static inline void hri_ramecc_set_INTEN_SINGLEE_bit(const void *const hw)
118 {
119 ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE;
120 }
121
hri_ramecc_get_INTEN_SINGLEE_bit(const void * const hw)122 static inline bool hri_ramecc_get_INTEN_SINGLEE_bit(const void *const hw)
123 {
124 return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_SINGLEE) >> RAMECC_INTENSET_SINGLEE_Pos;
125 }
126
hri_ramecc_write_INTEN_SINGLEE_bit(const void * const hw,bool value)127 static inline void hri_ramecc_write_INTEN_SINGLEE_bit(const void *const hw, bool value)
128 {
129 if (value == 0x0) {
130 ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE;
131 } else {
132 ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE;
133 }
134 }
135
hri_ramecc_clear_INTEN_SINGLEE_bit(const void * const hw)136 static inline void hri_ramecc_clear_INTEN_SINGLEE_bit(const void *const hw)
137 {
138 ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE;
139 }
140
hri_ramecc_set_INTEN_DUALE_bit(const void * const hw)141 static inline void hri_ramecc_set_INTEN_DUALE_bit(const void *const hw)
142 {
143 ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE;
144 }
145
hri_ramecc_get_INTEN_DUALE_bit(const void * const hw)146 static inline bool hri_ramecc_get_INTEN_DUALE_bit(const void *const hw)
147 {
148 return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_DUALE) >> RAMECC_INTENSET_DUALE_Pos;
149 }
150
hri_ramecc_write_INTEN_DUALE_bit(const void * const hw,bool value)151 static inline void hri_ramecc_write_INTEN_DUALE_bit(const void *const hw, bool value)
152 {
153 if (value == 0x0) {
154 ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE;
155 } else {
156 ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE;
157 }
158 }
159
hri_ramecc_clear_INTEN_DUALE_bit(const void * const hw)160 static inline void hri_ramecc_clear_INTEN_DUALE_bit(const void *const hw)
161 {
162 ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE;
163 }
164
hri_ramecc_set_INTEN_reg(const void * const hw,hri_ramecc_intenset_reg_t mask)165 static inline void hri_ramecc_set_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask)
166 {
167 ((Ramecc *)hw)->INTENSET.reg = mask;
168 }
169
hri_ramecc_get_INTEN_reg(const void * const hw,hri_ramecc_intenset_reg_t mask)170 static inline hri_ramecc_intenset_reg_t hri_ramecc_get_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask)
171 {
172 uint8_t tmp;
173 tmp = ((Ramecc *)hw)->INTENSET.reg;
174 tmp &= mask;
175 return tmp;
176 }
177
hri_ramecc_read_INTEN_reg(const void * const hw)178 static inline hri_ramecc_intenset_reg_t hri_ramecc_read_INTEN_reg(const void *const hw)
179 {
180 return ((Ramecc *)hw)->INTENSET.reg;
181 }
182
hri_ramecc_write_INTEN_reg(const void * const hw,hri_ramecc_intenset_reg_t data)183 static inline void hri_ramecc_write_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t data)
184 {
185 ((Ramecc *)hw)->INTENSET.reg = data;
186 ((Ramecc *)hw)->INTENCLR.reg = ~data;
187 }
188
hri_ramecc_clear_INTEN_reg(const void * const hw,hri_ramecc_intenset_reg_t mask)189 static inline void hri_ramecc_clear_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask)
190 {
191 ((Ramecc *)hw)->INTENCLR.reg = mask;
192 }
193
hri_ramecc_get_STATUS_ECCDIS_bit(const void * const hw)194 static inline bool hri_ramecc_get_STATUS_ECCDIS_bit(const void *const hw)
195 {
196 return (((Ramecc *)hw)->STATUS.reg & RAMECC_STATUS_ECCDIS) >> RAMECC_STATUS_ECCDIS_Pos;
197 }
198
hri_ramecc_get_STATUS_reg(const void * const hw,hri_ramecc_status_reg_t mask)199 static inline hri_ramecc_status_reg_t hri_ramecc_get_STATUS_reg(const void *const hw, hri_ramecc_status_reg_t mask)
200 {
201 uint8_t tmp;
202 tmp = ((Ramecc *)hw)->STATUS.reg;
203 tmp &= mask;
204 return tmp;
205 }
206
hri_ramecc_read_STATUS_reg(const void * const hw)207 static inline hri_ramecc_status_reg_t hri_ramecc_read_STATUS_reg(const void *const hw)
208 {
209 return ((Ramecc *)hw)->STATUS.reg;
210 }
211
hri_ramecc_get_ERRADDR_ERRADDR_bf(const void * const hw,hri_ramecc_erraddr_reg_t mask)212 static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_ERRADDR_bf(const void *const hw,
213 hri_ramecc_erraddr_reg_t mask)
214 {
215 return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR(mask)) >> RAMECC_ERRADDR_ERRADDR_Pos;
216 }
217
hri_ramecc_read_ERRADDR_ERRADDR_bf(const void * const hw)218 static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_ERRADDR_bf(const void *const hw)
219 {
220 return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR_Msk) >> RAMECC_ERRADDR_ERRADDR_Pos;
221 }
222
hri_ramecc_get_ERRADDR_reg(const void * const hw,hri_ramecc_erraddr_reg_t mask)223 static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_reg(const void *const hw, hri_ramecc_erraddr_reg_t mask)
224 {
225 uint32_t tmp;
226 tmp = ((Ramecc *)hw)->ERRADDR.reg;
227 tmp &= mask;
228 return tmp;
229 }
230
hri_ramecc_read_ERRADDR_reg(const void * const hw)231 static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw)
232 {
233 return ((Ramecc *)hw)->ERRADDR.reg;
234 }
235
hri_ramecc_set_DBGCTRL_ECCDIS_bit(const void * const hw)236 static inline void hri_ramecc_set_DBGCTRL_ECCDIS_bit(const void *const hw)
237 {
238 RAMECC_CRITICAL_SECTION_ENTER();
239 ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCDIS;
240 RAMECC_CRITICAL_SECTION_LEAVE();
241 }
242
hri_ramecc_get_DBGCTRL_ECCDIS_bit(const void * const hw)243 static inline bool hri_ramecc_get_DBGCTRL_ECCDIS_bit(const void *const hw)
244 {
245 uint8_t tmp;
246 tmp = ((Ramecc *)hw)->DBGCTRL.reg;
247 tmp = (tmp & RAMECC_DBGCTRL_ECCDIS) >> RAMECC_DBGCTRL_ECCDIS_Pos;
248 return (bool)tmp;
249 }
250
hri_ramecc_write_DBGCTRL_ECCDIS_bit(const void * const hw,bool value)251 static inline void hri_ramecc_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value)
252 {
253 uint8_t tmp;
254 RAMECC_CRITICAL_SECTION_ENTER();
255 tmp = ((Ramecc *)hw)->DBGCTRL.reg;
256 tmp &= ~RAMECC_DBGCTRL_ECCDIS;
257 tmp |= value << RAMECC_DBGCTRL_ECCDIS_Pos;
258 ((Ramecc *)hw)->DBGCTRL.reg = tmp;
259 RAMECC_CRITICAL_SECTION_LEAVE();
260 }
261
hri_ramecc_clear_DBGCTRL_ECCDIS_bit(const void * const hw)262 static inline void hri_ramecc_clear_DBGCTRL_ECCDIS_bit(const void *const hw)
263 {
264 RAMECC_CRITICAL_SECTION_ENTER();
265 ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCDIS;
266 RAMECC_CRITICAL_SECTION_LEAVE();
267 }
268
hri_ramecc_toggle_DBGCTRL_ECCDIS_bit(const void * const hw)269 static inline void hri_ramecc_toggle_DBGCTRL_ECCDIS_bit(const void *const hw)
270 {
271 RAMECC_CRITICAL_SECTION_ENTER();
272 ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCDIS;
273 RAMECC_CRITICAL_SECTION_LEAVE();
274 }
275
hri_ramecc_set_DBGCTRL_ECCELOG_bit(const void * const hw)276 static inline void hri_ramecc_set_DBGCTRL_ECCELOG_bit(const void *const hw)
277 {
278 RAMECC_CRITICAL_SECTION_ENTER();
279 ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCELOG;
280 RAMECC_CRITICAL_SECTION_LEAVE();
281 }
282
hri_ramecc_get_DBGCTRL_ECCELOG_bit(const void * const hw)283 static inline bool hri_ramecc_get_DBGCTRL_ECCELOG_bit(const void *const hw)
284 {
285 uint8_t tmp;
286 tmp = ((Ramecc *)hw)->DBGCTRL.reg;
287 tmp = (tmp & RAMECC_DBGCTRL_ECCELOG) >> RAMECC_DBGCTRL_ECCELOG_Pos;
288 return (bool)tmp;
289 }
290
hri_ramecc_write_DBGCTRL_ECCELOG_bit(const void * const hw,bool value)291 static inline void hri_ramecc_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value)
292 {
293 uint8_t tmp;
294 RAMECC_CRITICAL_SECTION_ENTER();
295 tmp = ((Ramecc *)hw)->DBGCTRL.reg;
296 tmp &= ~RAMECC_DBGCTRL_ECCELOG;
297 tmp |= value << RAMECC_DBGCTRL_ECCELOG_Pos;
298 ((Ramecc *)hw)->DBGCTRL.reg = tmp;
299 RAMECC_CRITICAL_SECTION_LEAVE();
300 }
301
hri_ramecc_clear_DBGCTRL_ECCELOG_bit(const void * const hw)302 static inline void hri_ramecc_clear_DBGCTRL_ECCELOG_bit(const void *const hw)
303 {
304 RAMECC_CRITICAL_SECTION_ENTER();
305 ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCELOG;
306 RAMECC_CRITICAL_SECTION_LEAVE();
307 }
308
hri_ramecc_toggle_DBGCTRL_ECCELOG_bit(const void * const hw)309 static inline void hri_ramecc_toggle_DBGCTRL_ECCELOG_bit(const void *const hw)
310 {
311 RAMECC_CRITICAL_SECTION_ENTER();
312 ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCELOG;
313 RAMECC_CRITICAL_SECTION_LEAVE();
314 }
315
hri_ramecc_set_DBGCTRL_reg(const void * const hw,hri_ramecc_dbgctrl_reg_t mask)316 static inline void hri_ramecc_set_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
317 {
318 RAMECC_CRITICAL_SECTION_ENTER();
319 ((Ramecc *)hw)->DBGCTRL.reg |= mask;
320 RAMECC_CRITICAL_SECTION_LEAVE();
321 }
322
hri_ramecc_get_DBGCTRL_reg(const void * const hw,hri_ramecc_dbgctrl_reg_t mask)323 static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_get_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
324 {
325 uint8_t tmp;
326 tmp = ((Ramecc *)hw)->DBGCTRL.reg;
327 tmp &= mask;
328 return tmp;
329 }
330
hri_ramecc_write_DBGCTRL_reg(const void * const hw,hri_ramecc_dbgctrl_reg_t data)331 static inline void hri_ramecc_write_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t data)
332 {
333 RAMECC_CRITICAL_SECTION_ENTER();
334 ((Ramecc *)hw)->DBGCTRL.reg = data;
335 RAMECC_CRITICAL_SECTION_LEAVE();
336 }
337
hri_ramecc_clear_DBGCTRL_reg(const void * const hw,hri_ramecc_dbgctrl_reg_t mask)338 static inline void hri_ramecc_clear_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
339 {
340 RAMECC_CRITICAL_SECTION_ENTER();
341 ((Ramecc *)hw)->DBGCTRL.reg &= ~mask;
342 RAMECC_CRITICAL_SECTION_LEAVE();
343 }
344
hri_ramecc_toggle_DBGCTRL_reg(const void * const hw,hri_ramecc_dbgctrl_reg_t mask)345 static inline void hri_ramecc_toggle_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask)
346 {
347 RAMECC_CRITICAL_SECTION_ENTER();
348 ((Ramecc *)hw)->DBGCTRL.reg ^= mask;
349 RAMECC_CRITICAL_SECTION_LEAVE();
350 }
351
hri_ramecc_read_DBGCTRL_reg(const void * const hw)352 static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_read_DBGCTRL_reg(const void *const hw)
353 {
354 return ((Ramecc *)hw)->DBGCTRL.reg;
355 }
356
357 #ifdef __cplusplus
358 }
359 #endif
360
361 #endif /* _HRI_RAMECC_E54_H_INCLUDED */
362 #endif /* _SAME54_RAMECC_COMPONENT_ */
363