1 /*********************************************************************************************************//** 2 * @file ht32f5xxxx_adc.h 3 * @version $Rev:: 7678 $ 4 * @date $Date:: 2024-04-01 #$ 5 * @brief The header file of the ADC library. 6 ************************************************************************************************************* 7 * @attention 8 * 9 * Firmware Disclaimer Information 10 * 11 * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the 12 * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the 13 * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and 14 * other intellectual property laws. 15 * 16 * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the 17 * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties 18 * other than HOLTEK and the customer. 19 * 20 * 3. The program technical documentation, including the code, is provided "as is" and for customer reference 21 * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including 22 * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including 23 * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. 24 * 25 * <h2><center>Copyright (C) Holtek Semiconductor Inc. All rights reserved</center></h2> 26 ************************************************************************************************************/ 27 28 /* Define to prevent recursive inclusion -------------------------------------------------------------------*/ 29 #ifndef __ht32f5XXXX_ADC_H 30 #define __ht32f5XXXX_ADC_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* Includes ------------------------------------------------------------------------------------------------*/ 37 #include "ht32.h" 38 39 /** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver 40 * @{ 41 */ 42 43 /** @addtogroup ADC 44 * @{ 45 */ 46 47 48 /* Exported constants --------------------------------------------------------------------------------------*/ 49 /** @defgroup ADC_Exported_Constants ADC exported constants 50 * @{ 51 */ 52 #define IS_ADC(x) (x == HT_ADC0) 53 54 #define ONE_SHOT_MODE (0x00000000) 55 #define CONTINUOUS_MODE (0x00000002) 56 #if (LIBCFG_ADC_NO_DISCON_MODE) 57 #define IS_DISCONTINUOUS_MODE(x) (0) 58 #else 59 #define DISCONTINUOUS_MODE (0x00000003) 60 #define IS_DISCONTINUOUS_MODE(x) (x == DISCONTINUOUS_MODE) 61 #endif 62 63 #define IS_ADC_CONVERSION_MODE(REGULAR_MODE) ((REGULAR_MODE == ONE_SHOT_MODE) || \ 64 (REGULAR_MODE == CONTINUOUS_MODE) || \ 65 (IS_DISCONTINUOUS_MODE(REGULAR_MODE))) 66 67 #define ADC_CH_0 (0) 68 #define ADC_CH_1 (1) 69 #define ADC_CH_2 (2) 70 #define ADC_CH_3 (3) 71 #define ADC_CH_4 (4) 72 #define ADC_CH_5 (5) 73 #define ADC_CH_6 (6) 74 #define ADC_CH_7 (7) 75 76 #define IS_ADC_CHANNEL1(CHANNEL) (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || \ 77 ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) || \ 78 ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || \ 79 ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7)) 80 81 #if (LIBCFG_ADC_CH8_9) 82 #define ADC_CH_8 (8) 83 #define ADC_CH_9 (9) 84 #define IS_ADC_CHANNEL2(CHANNEL) (((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9)) 85 #elif (LIBCFG_ADC_CH8_11) 86 #define ADC_CH_8 (8) 87 #define ADC_CH_9 (9) 88 #define ADC_CH_10 (10) 89 #define ADC_CH_11 (11) 90 #define IS_ADC_CHANNEL2(CHANNEL) (((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || \ 91 ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11)) 92 #else 93 #define IS_ADC_CHANNEL2(CHANNEL) (0) 94 #endif 95 96 #if (LIBCFG_ADC_CH12_15) 97 #define ADC_CH_12 (12) 98 #define ADC_CH_13 (13) 99 #define ADC_CH_14 (14) 100 #define ADC_CH_15 (15) 101 #define IS_ADC_CHANNEL3(CHANNEL) (((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || \ 102 ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15)) 103 #else 104 #define IS_ADC_CHANNEL3(CHANNEL) (0) 105 #endif 106 107 #if defined(USE_HT32F50020_30) 108 #define ADC_CH_BANDGAP (12) 109 #define ADC_CH_MVDDA (13) 110 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_BANDGAP) || ((CH) == ADC_CH_MVDDA)) 111 #endif 112 113 #if defined(USE_HT32F50220_30) 114 #define ADC_CH_GND_VREF (12) 115 #define ADC_CH_VDD_VREF (13) 116 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) 117 #endif 118 119 #if defined(USE_HT32F50231_41) 120 #define ADC_CH_GND_VREF (12) 121 #define ADC_CH_VDD_VREF (13) 122 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) 123 #endif 124 125 #if defined(USE_HT32F52220_30) 126 #define ADC_CH_GND_VREF (16) 127 #define ADC_CH_VDD_VREF (17) 128 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) 129 #endif 130 131 #if defined(USE_HT32F52231_41) 132 #define ADC_CH_GND_VREF (16) 133 #define ADC_CH_VDD_VREF (17) 134 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) 135 #endif 136 137 #if defined(USE_HT32F52243_53) 138 #define ADC_CH_GND_VREF (16) 139 #define ADC_CH_VDD_VREF (17) 140 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) 141 #endif 142 143 #if defined(USE_HT32F52331_41) 144 #define ADC_CH_GND_VREF (16) 145 #define ADC_CH_VDD_VREF (17) 146 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) 147 #endif 148 149 #if defined(USE_HT32F52342_52) 150 #define ADC_CH_GND_VREF (16) 151 #define ADC_CH_VDD_VREF (17) 152 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) 153 #endif 154 155 #if defined(USE_HT32F52344_54) 156 #define ADC_CH_IVREF (15) 157 #define ADC_CH_GND_VREF (16) 158 #define ADC_CH_MVDDA (17) 159 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ 160 ((CH) == ADC_CH_GND_VREF) || \ 161 ((CH) == ADC_CH_MVDDA)) 162 #endif 163 164 #if defined(USE_HT32F52357_67) 165 #define ADC_CH_VDD_VREF (12) 166 #define ADC_CH_DAC0_CH1 (13) 167 #define ADC_CH_DAC0_CH0 (14) 168 #define ADC_CH_IVREF (15) 169 #define ADC_CH_GND_VREF (16) 170 #define ADC_CH_MVDDA (17) 171 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_VDD_VREF) || \ 172 ((CH) == ADC_CH_DAC0_CH1) || \ 173 ((CH) == ADC_CH_DAC0_CH0) || \ 174 ((CH) == ADC_CH_IVREF) || \ 175 ((CH) == ADC_CH_GND_VREF) || \ 176 ((CH) == ADC_CH_MVDDA)) 177 #endif 178 179 #if defined(USE_HT32F57331_41) 180 #define ADC_CH_VDD_VREF (12) 181 #define ADC_CH_IVREF (15) 182 #define ADC_CH_GND_VREF (16) 183 #define ADC_CH_MVDDA (17) 184 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_VDD_VREF) || \ 185 ((CH) == ADC_CH_IVREF) || \ 186 ((CH) == ADC_CH_GND_VREF) || \ 187 ((CH) == ADC_CH_MVDDA)) 188 #endif 189 190 #if defined(USE_HT32F57342_52) 191 #define ADC_CH_VDD_VREF (12) 192 #define ADC_CH_DAC0_CH1 (13) 193 #define ADC_CH_DAC0_CH0 (14) 194 #define ADC_CH_IVREF (15) 195 #define ADC_CH_GND_VREF (16) 196 #define ADC_CH_MVDDA (17) 197 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_VDD_VREF) || \ 198 ((CH) == ADC_CH_DAC0_CH1) || \ 199 ((CH) == ADC_CH_DAC0_CH0) || \ 200 ((CH) == ADC_CH_IVREF) || \ 201 ((CH) == ADC_CH_GND_VREF) || \ 202 ((CH) == ADC_CH_MVDDA)) 203 #endif 204 205 #if defined(USE_HT32F0006) 206 #define ADC_CH_GND_VREF (16) 207 #define ADC_CH_VDD_VREF (17) 208 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) 209 #endif 210 211 #if defined(USE_HT32F61244_45) 212 #define ADC_CH_GND_VREF (16) 213 #define ADC_CH_VDD_VREF (17) 214 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) 215 #endif 216 217 #if defined(USE_HT32F50343) 218 #define ADC_CH_MVDDA (17) 219 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_MVDDA)) 220 #endif 221 222 #if defined(USE_HT32F5826) 223 #define ADC_CH_GND_VREF (16) 224 #define ADC_CH_VDD_VREF (17) 225 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || ((CH) == ADC_CH_VDD_VREF)) 226 #endif 227 228 #if defined(USE_HT32F54231_41) 229 #define ADC_CH_GND_VREF (10) 230 #define ADC_CH_VDD_VREF (11) 231 #define ADC_CH_IVREF (12) 232 #define ADC_CH_MVDDA (13) 233 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || \ 234 ((CH) == ADC_CH_VDD_VREF) || \ 235 ((CH) == ADC_CH_IVREF) || \ 236 ((CH) == ADC_CH_MVDDA)) 237 #endif 238 239 #if defined(USE_HT32F54243_53) 240 #define ADC_CH_GND_VREF (10) 241 #define ADC_CH_VDD_VREF (11) 242 #define ADC_CH_IVREF (12) 243 #define ADC_CH_MVDDA (13) 244 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_GND_VREF) || \ 245 ((CH) == ADC_CH_VDD_VREF) || \ 246 ((CH) == ADC_CH_IVREF) || \ 247 ((CH) == ADC_CH_MVDDA)) 248 #endif 249 250 #if defined(USE_HT32F67041_51) 251 #define ADC_CH_IVREF (15) 252 #define ADC_CH_GND_VREF (16) 253 #define ADC_CH_MVDDA (17) 254 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ 255 ((CH) == ADC_CH_GND_VREF) || \ 256 ((CH) == ADC_CH_MVDDA)) 257 #endif 258 259 #if defined(USE_HT32F52234_44) 260 #define ADC_CH_DAC0_CH0 (12) 261 #define ADC_CH_DAC0_CH1 (13) 262 #define ADC_CH_DAC1_CH0 (14) 263 #define ADC_CH_DAC1_CH1 (15) 264 #define ADC_CH_IVREF (16) 265 #define ADC_CH_MVDDA (17) 266 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_DAC0_CH0) || \ 267 ((CH) == ADC_CH_DAC0_CH1) || \ 268 ((CH) == ADC_CH_DAC1_CH0) || \ 269 ((CH) == ADC_CH_DAC1_CH1) || \ 270 ((CH) == ADC_CH_IVREF) || \ 271 ((CH) == ADC_CH_MVDDA)) 272 #endif 273 274 #if defined(USE_HT32F53231_41) 275 #define ADC_CH_IVREF (12) 276 #define ADC_CH_MVDDA (13) 277 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ 278 ((CH) == ADC_CH_MVDDA)) 279 #endif 280 281 #if defined(USE_HT32F53242_52) 282 #define ADC_CH_IVREF (12) 283 #define ADC_CH_MVDDA (13) 284 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ 285 ((CH) == ADC_CH_MVDDA)) 286 #endif 287 288 #if defined(USE_HT32F50431_41) 289 #define ADC_CH_IVREF (12) 290 #define ADC_CH_MVDDA (13) 291 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ 292 ((CH) == ADC_CH_MVDDA)) 293 #endif 294 295 #if defined(USE_HT32F50442_52) 296 #define ADC_CH_IVREF (12) 297 #define ADC_CH_MVDDA (13) 298 #define IS_ADC_CH_INTERNAL1(CH) (((CH) == ADC_CH_IVREF) || \ 299 ((CH) == ADC_CH_MVDDA)) 300 #endif 301 302 #define IS_ADC_CHANNEL(CHANNEL) (IS_ADC_CHANNEL1(CHANNEL) || \ 303 IS_ADC_CHANNEL2(CHANNEL) || \ 304 IS_ADC_CHANNEL3(CHANNEL) || \ 305 IS_ADC_CH_INTERNAL1(CHANNEL)) 306 307 #define IS_ADC_INPUT_CHANNEL(CHANNEL) (IS_ADC_CHANNEL1(CHANNEL) || IS_ADC_CHANNEL2(CHANNEL) || IS_ADC_CHANNEL3(CHANNEL)) 308 309 310 #define ADC_TRIG_SOFTWARE (1UL << 0) 311 312 #if (LIBCFG_ADC_SW_TRIGGER_ONLY) 313 #define IS_ADC_TRIG(REGTRIG) ((REGTRIG) == ADC_TRIG_SOFTWARE) 314 #else 315 /* ((ADCTCR[4] << 4) | (ADCTSR[20] << 20)) */ 316 #if (LIBCFG_CMP) 317 #define ADC_TRIG_CMP0 ((1UL << 4) | (0UL << 20)) 318 #define ADC_TRIG_CMP1 ((1UL << 4) | (1UL << 20)) 319 #endif 320 321 /* ((ADCTCR[3] << 3) | (ADCTSR[23:22] << 22) | (ADCTSR[19] << 19)) */ 322 #define ADC_TRIG_BFTM0 ((1UL << 3) | (0UL << 22) | (0UL << 19)) 323 #if (LIBCFG_BFTM1) 324 #define ADC_TRIG_BFTM1 ((1UL << 3) | (0UL << 22) | (1UL << 19)) 325 #endif 326 327 /* ((ADCTCR[3] << 3) | (ADCTSR[29:27]) << 27) | (ADCTSR[23:22] << 22) | (ADCTSR[19] << 19)) */ 328 #if (LIBCFG_PWM0) 329 #define ADC_TRIG_PWM0_MTO ((1UL << 3) | (0UL << 27) | (1UL << 22) | (0UL << 19)) 330 #define ADC_TRIG_PWM0_CH0O ((1UL << 3) | (1UL << 27) | (1UL << 22) | (0UL << 19)) 331 #define ADC_TRIG_PWM0_CH1O ((1UL << 3) | (2UL << 27) | (1UL << 22) | (0UL << 19)) 332 #define ADC_TRIG_PWM0_CH2O ((1UL << 3) | (3UL << 27) | (1UL << 22) | (0UL << 19)) 333 #define ADC_TRIG_PWM0_CH3O ((1UL << 3) | (4UL << 27) | (1UL << 22) | (0UL << 19)) 334 #endif 335 #if (LIBCFG_PWM1) 336 #define ADC_TRIG_PWM1_MTO ((1UL << 3) | (0UL << 27) | (1UL << 22) | (1UL << 19)) 337 #define ADC_TRIG_PWM1_CH0O ((1UL << 3) | (1UL << 27) | (1UL << 22) | (1UL << 19)) 338 #define ADC_TRIG_PWM1_CH1O ((1UL << 3) | (2UL << 27) | (1UL << 22) | (1UL << 19)) 339 #define ADC_TRIG_PWM1_CH2O ((1UL << 3) | (3UL << 27) | (1UL << 22) | (1UL << 19)) 340 #define ADC_TRIG_PWM1_CH3O ((1UL << 3) | (4UL << 27) | (1UL << 22) | (1UL << 19)) 341 #endif 342 343 /* ((ADCTCR[2] << 2) | (ADCTSR[26:24] << 24) | (ADCTSR[18:16] << 16)) */ 344 #if (LIBCFG_MCTM0) 345 #define ADC_TRIG_MCTM0_MTO ((1UL << 2) | (0UL << 24) | (0UL << 16)) 346 #define ADC_TRIG_MCTM0_CH0O ((1UL << 2) | (1UL << 24) | (0UL << 16)) 347 #define ADC_TRIG_MCTM0_CH1O ((1UL << 2) | (2UL << 24) | (0UL << 16)) 348 #define ADC_TRIG_MCTM0_CH2O ((1UL << 2) | (3UL << 24) | (0UL << 16)) 349 #define ADC_TRIG_MCTM0_CH3O ((1UL << 2) | (4UL << 24) | (0UL << 16)) 350 #endif 351 352 #if (LIBCFG_NO_GPTM0) 353 #define IS_ADC_TRIG_GPTM0(x) (0) 354 #else 355 #define ADC_TRIG_GPTM0_MTO ((1UL << 2) | (0UL << 24) | (2UL << 16)) 356 #define ADC_TRIG_GPTM0_CH0O ((1UL << 2) | (1UL << 24) | (2UL << 16)) 357 #define ADC_TRIG_GPTM0_CH1O ((1UL << 2) | (2UL << 24) | (2UL << 16)) 358 #define ADC_TRIG_GPTM0_CH2O ((1UL << 2) | (3UL << 24) | (2UL << 16)) 359 #define ADC_TRIG_GPTM0_CH3O ((1UL << 2) | (4UL << 24) | (2UL << 16)) 360 361 #define IS_ADC_TRIG_GPTM0(x) (((x) == ADC_TRIG_GPTM0_MTO) || \ 362 ((x) == ADC_TRIG_GPTM0_CH0O) || \ 363 ((x) == ADC_TRIG_GPTM0_CH1O) || \ 364 ((x) == ADC_TRIG_GPTM0_CH2O) || \ 365 ((x) == ADC_TRIG_GPTM0_CH3O)) 366 #endif 367 368 #if (LIBCFG_GPTM1) 369 #define ADC_TRIG_GPTM1_MTO ((1UL << 2) | (0UL << 24) | (3UL << 16)) 370 #define ADC_TRIG_GPTM1_CH0O ((1UL << 2) | (1UL << 24) | (3UL << 16)) 371 #define ADC_TRIG_GPTM1_CH1O ((1UL << 2) | (2UL << 24) | (3UL << 16)) 372 #define ADC_TRIG_GPTM1_CH2O ((1UL << 2) | (3UL << 24) | (3UL << 16)) 373 #define ADC_TRIG_GPTM1_CH3O ((1UL << 2) | (4UL << 24) | (3UL << 16)) 374 #endif 375 376 /* (ADCTCR[1] << 1) | (ADCTSR[11:8] << 8) */ 377 #define ADC_TRIG_EXTI_0 ((1UL << 1) | ( 0UL << 8)) 378 #define ADC_TRIG_EXTI_1 ((1UL << 1) | ( 1UL << 8)) 379 #define ADC_TRIG_EXTI_2 ((1UL << 1) | ( 2UL << 8)) 380 #define ADC_TRIG_EXTI_3 ((1UL << 1) | ( 3UL << 8)) 381 #define ADC_TRIG_EXTI_4 ((1UL << 1) | ( 4UL << 8)) 382 #define ADC_TRIG_EXTI_5 ((1UL << 1) | ( 5UL << 8)) 383 #define ADC_TRIG_EXTI_6 ((1UL << 1) | ( 6UL << 8)) 384 #define ADC_TRIG_EXTI_7 ((1UL << 1) | ( 7UL << 8)) 385 #define ADC_TRIG_EXTI_8 ((1UL << 1) | ( 8UL << 8)) 386 #define ADC_TRIG_EXTI_9 ((1UL << 1) | ( 9UL << 8)) 387 #define ADC_TRIG_EXTI_10 ((1UL << 1) | (10UL << 8)) 388 #define ADC_TRIG_EXTI_11 ((1UL << 1) | (11UL << 8)) 389 #define ADC_TRIG_EXTI_12 ((1UL << 1) | (12UL << 8)) 390 #define ADC_TRIG_EXTI_13 ((1UL << 1) | (13UL << 8)) 391 #define ADC_TRIG_EXTI_14 ((1UL << 1) | (14UL << 8)) 392 #define ADC_TRIG_EXTI_15 ((1UL << 1) | (15UL << 8)) 393 394 #define IS_ADC_TRIG(REGTRIG) (IS_ADC_TRIG1(REGTRIG) || \ 395 IS_ADC_TRIG2(REGTRIG) || \ 396 IS_ADC_TRIG3(REGTRIG) || \ 397 IS_ADC_TRIG4(REGTRIG) || \ 398 IS_ADC_TRIG5(REGTRIG) || \ 399 IS_ADC_TRIG6(REGTRIG) || \ 400 IS_ADC_TRIG7(REGTRIG)) 401 402 #define IS_ADC_TRIG1(REGTRIG) (IS_ADC_TRIG_GPTM0(REGTRIG) || \ 403 ((REGTRIG) == ADC_TRIG_BFTM0) || \ 404 ((REGTRIG) == ADC_TRIG_EXTI_0) || \ 405 ((REGTRIG) == ADC_TRIG_EXTI_1) || \ 406 ((REGTRIG) == ADC_TRIG_EXTI_2) || \ 407 ((REGTRIG) == ADC_TRIG_EXTI_3) || \ 408 ((REGTRIG) == ADC_TRIG_EXTI_4) || \ 409 ((REGTRIG) == ADC_TRIG_EXTI_5) || \ 410 ((REGTRIG) == ADC_TRIG_EXTI_6) || \ 411 ((REGTRIG) == ADC_TRIG_EXTI_7) || \ 412 ((REGTRIG) == ADC_TRIG_EXTI_8) || \ 413 ((REGTRIG) == ADC_TRIG_EXTI_9) || \ 414 ((REGTRIG) == ADC_TRIG_EXTI_10) || \ 415 ((REGTRIG) == ADC_TRIG_EXTI_11) || \ 416 ((REGTRIG) == ADC_TRIG_EXTI_12) || \ 417 ((REGTRIG) == ADC_TRIG_EXTI_13) || \ 418 ((REGTRIG) == ADC_TRIG_EXTI_14) || \ 419 ((REGTRIG) == ADC_TRIG_EXTI_15) || \ 420 ((REGTRIG) == ADC_TRIG_SOFTWARE)) 421 422 #if (LIBCFG_BFTM1) 423 #define IS_ADC_TRIG2(REGTRIG) ((REGTRIG) == ADC_TRIG_BFTM1) 424 #else 425 #define IS_ADC_TRIG2(REGTRIG) (0) 426 #endif 427 428 #if (LIBCFG_MCTM0) 429 #define IS_ADC_TRIG3(REGTRIG) (((REGTRIG) == ADC_TRIG_MCTM0_MTO) || \ 430 ((REGTRIG) == ADC_TRIG_MCTM0_CH0O) || \ 431 ((REGTRIG) == ADC_TRIG_MCTM0_CH1O) || \ 432 ((REGTRIG) == ADC_TRIG_MCTM0_CH2O) || \ 433 ((REGTRIG) == ADC_TRIG_MCTM0_CH3O) || \ 434 ((REGTRIG) == ADC_TRIG_BFTM1)) 435 #else 436 #define IS_ADC_TRIG3(REGTRIG) (0) 437 #endif 438 439 #if (LIBCFG_GPTM1) 440 #define IS_ADC_TRIG4(REGTRIG) (((REGTRIG) == ADC_TRIG_GPTM1_MTO) || \ 441 ((REGTRIG) == ADC_TRIG_GPTM1_CH0O) || \ 442 ((REGTRIG) == ADC_TRIG_GPTM1_CH1O) || \ 443 ((REGTRIG) == ADC_TRIG_GPTM1_CH2O) || \ 444 ((REGTRIG) == ADC_TRIG_GPTM1_CH3O)) 445 #else 446 #define IS_ADC_TRIG4(REGTRIG) (0) 447 #endif 448 449 #if (LIBCFG_PWM0) 450 #define IS_ADC_TRIG5(REGTRIG) (((REGTRIG) == ADC_TRIG_PWM0_MTO) || \ 451 ((REGTRIG) == ADC_TRIG_PWM0_CH0O) || \ 452 ((REGTRIG) == ADC_TRIG_PWM0_CH1O) || \ 453 ((REGTRIG) == ADC_TRIG_PWM0_CH2O) || \ 454 ((REGTRIG) == ADC_TRIG_PWM0_CH3O)) 455 #else 456 #define IS_ADC_TRIG5(REGTRIG) (0) 457 #endif 458 459 #if (LIBCFG_PWM1) 460 #define IS_ADC_TRIG6(REGTRIG) (((REGTRIG) == ADC_TRIG_PWM1_MTO) || \ 461 ((REGTRIG) == ADC_TRIG_PWM1_CH0O) || \ 462 ((REGTRIG) == ADC_TRIG_PWM1_CH1O) || \ 463 ((REGTRIG) == ADC_TRIG_PWM1_CH2O) || \ 464 ((REGTRIG) == ADC_TRIG_PWM1_CH3O)) 465 #else 466 #define IS_ADC_TRIG6(REGTRIG) (0) 467 #endif 468 469 #if (LIBCFG_CMP) 470 #define IS_ADC_TRIG7(REGTRIG) (((REGTRIG) == ADC_TRIG_CMP0) || \ 471 ((REGTRIG) == ADC_TRIG_CMP1)) 472 #else 473 #define IS_ADC_TRIG7(REGTRIG) (0) 474 #endif 475 #endif 476 477 #define ADC_INT_SINGLE_EOC (0x00000001) 478 #if (LIBCFG_ADC_NO_DISCON_MODE == 0) 479 #define ADC_INT_SUB_GROUP_EOC (0x00000002) 480 #endif 481 #define ADC_INT_CYCLE_EOC (0x00000004) 482 #if (LIBCFG_ADC_NO_WDT == 0) 483 #define ADC_INT_AWD_LOWER (0x00010000) 484 #define ADC_INT_AWD_UPPER (0x00020000) 485 #endif 486 #define ADC_INT_DATA_OVERWRITE (0x01000000) 487 488 #define IS_ADC_INT(INT) ((((INT) & 0xFEFCFFF8) == 0) && ((INT) != 0)) 489 490 491 #define ADC_FLAG_SINGLE_EOC (0x00000001) 492 #if (LIBCFG_ADC_NO_DISCON_MODE == 0) 493 #define ADC_FLAG_SUB_GROUP_EOC (0x00000002) 494 #endif 495 #define ADC_FLAG_CYCLE_EOC (0x00000004) 496 #if (LIBCFG_ADC_NO_WDT == 0) 497 #define ADC_FLAG_AWD_LOWER (0x00010000) 498 #define ADC_FLAG_AWD_UPPER (0x00020000) 499 #endif 500 #define ADC_FLAG_DATA_OVERWRITE (0x01000000) 501 502 #define IS_ADC_FLAG(FLAG) ((((FLAG) & 0xFEFCFFF8) == 0) && ((FLAG) != 0)) 503 504 505 #define ADC_REGULAR_DATA0 (0) 506 #define ADC_REGULAR_DATA1 (1) 507 #define ADC_REGULAR_DATA2 (2) 508 #define ADC_REGULAR_DATA3 (3) 509 #if (LIBCFG_ADC_NO_SEQ_4_7 == 0) 510 #define ADC_REGULAR_DATA4 (4) 511 #define ADC_REGULAR_DATA5 (5) 512 #define ADC_REGULAR_DATA6 (6) 513 #define ADC_REGULAR_DATA7 (7) 514 #endif 515 516 #if (LIBCFG_ADC_NO_SEQ_4_7) 517 #define IS_ADC_REGULAR_DATA(DATA) ((DATA) < 4) 518 #else 519 #define IS_ADC_REGULAR_DATA(DATA) ((DATA) < 8) 520 #endif 521 522 #define ADC_AWD_DISABLE (u8)0x00 523 #define ADC_AWD_ALL_LOWER (u8)0x05 524 #define ADC_AWD_ALL_UPPER (u8)0x06 525 #define ADC_AWD_ALL_LOWER_UPPER (u8)0x07 526 #define ADC_AWD_SINGLE_LOWER (u8)0x01 527 #define ADC_AWD_SINGLE_UPPER (u8)0x02 528 #define ADC_AWD_SINGLE_LOWER_UPPER (u8)0x03 529 530 #define IS_ADC_AWD(AWD) (((AWD) == ADC_AWD_DISABLE) || \ 531 ((AWD) == ADC_AWD_ALL_LOWER) || \ 532 ((AWD) == ADC_AWD_ALL_UPPER) || \ 533 ((AWD) == ADC_AWD_ALL_LOWER_UPPER) || \ 534 ((AWD) == ADC_AWD_SINGLE_LOWER) || \ 535 ((AWD) == ADC_AWD_SINGLE_UPPER) || \ 536 ((AWD) == ADC_AWD_SINGLE_LOWER_UPPER)) 537 538 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) < 4096) 539 540 #if (LIBCFG_PDMA) 541 #define ADC_PDMA_REGULAR_SINGLE (0x00000001) 542 #define ADC_PDMA_REGULAR_SUBGROUP (0x00000002) 543 #define ADC_PDMA_REGULAR_CYCLE (0x00000004) 544 545 #define IS_ADC_PDMA(PDMA) (((PDMA) == ADC_PDMA_REGULAR_SINGLE) || \ 546 ((PDMA) == ADC_PDMA_REGULAR_SUBGROUP) || \ 547 ((PDMA) == ADC_PDMA_REGULAR_CYCLE)) 548 #endif 549 550 #define IS_ADC_INPUT_SAMPLING_TIME(TIME) ((TIME) <= 255) 551 552 #define IS_ADC_OFFSET(OFFSET) ((OFFSET) < 4096) 553 554 555 #if (LIBCFG_ADC_NO_SEQ_4_7) 556 #define IS_ADC_REGULAR_RANK(RANK) ((RANK) < 4) 557 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 4)) 558 #else 559 #define IS_ADC_REGULAR_RANK(RANK) ((RANK) < 8) 560 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 8)) 561 #endif 562 #define IS_ADC_REGULAR_SUB_LENGTH(SUB_LENGTH) (((SUB_LENGTH) >= 1) && ((SUB_LENGTH) <= 8)) 563 564 #if (LIBCFG_ADC_IVREF) 565 #if (LIBCFG_ADC_IVREF_LEVEL_TYPE2) 566 #define ADC_VREF_2V5 (0ul << 4) 567 #define ADC_VREF_3V0 (1ul << 4) 568 #define ADC_VREF_4V0 (2ul << 4) 569 #define ADC_VREF_4V5 (3ul << 4) 570 571 #define IS_ADC_VREF_SEL(SEL) ((SEL == ADC_VREF_2V5) || \ 572 (SEL == ADC_VREF_3V0) || \ 573 (SEL == ADC_VREF_4V0) || \ 574 (SEL == ADC_VREF_4V5)) 575 #else 576 #if LIBCFG_ADC_IVREF_DEFAULT_08V 577 #define ADC_VREF_0V8 (0ul << 4) 578 #define ADC_VREF_DEFAULT ADC_VREF_0V8 579 #else 580 #define ADC_VREF_1V215 (0ul << 4) 581 #define ADC_VREF_DEFAULT ADC_VREF_1V215 582 #endif 583 #define ADC_VREF_2V0 (1ul << 4) 584 #define ADC_VREF_2V5 (2ul << 4) 585 #define ADC_VREF_2V7 (3ul << 4) 586 587 #define IS_ADC_VREF_SEL(SEL) ((SEL == ADC_VREF_DEFAULT) || \ 588 (SEL == ADC_VREF_2V0) || \ 589 (SEL == ADC_VREF_2V5) || \ 590 (SEL == ADC_VREF_2V7)) 591 #endif 592 #endif 593 594 /** 595 * @} 596 */ 597 598 /* Exported functions --------------------------------------------------------------------------------------*/ 599 /** @defgroup ADC_Exported_Functions ADC exported functions 600 * @{ 601 */ 602 void ADC_DeInit(HT_ADC_TypeDef* HT_ADCn); 603 void ADC_Reset(HT_ADC_TypeDef* HT_ADCn); 604 void ADC_Cmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); 605 606 void ADC_SamplingTimeConfig(HT_ADC_TypeDef* HT_ADCn, u8 SampleClock); 607 void ADC_RegularChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n, u8 Rank, ...); 608 void ADC_RegularGroupConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_MODE, u8 Length, u8 SubLength); 609 void ADC_RegularTrigConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_TRIG_x); 610 611 void ADC_SoftwareStartConvCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); 612 613 u16 ADC_GetConversionData(HT_ADC_TypeDef* HT_ADCn, u8 ADC_REGULAR_DATAn); 614 615 void ADC_IntConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x, ControlStatus NewState); 616 FlagStatus ADC_GetIntStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); 617 void ADC_ClearIntPendingBit(HT_ADC_TypeDef* HT_ADCn, u32 ADC_INT_x); 618 FlagStatus ADC_GetFlagStatus(HT_ADC_TypeDef* HT_ADCn, u32 ADC_FLAG_x); 619 620 #if (LIBCFG_ADC_NO_WDT) 621 #else 622 void ADC_AWDConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_AWD_x); 623 void ADC_AWDSingleChannelConfig(HT_ADC_TypeDef* HT_ADCn, u8 ADC_CH_n); 624 void ADC_AWDThresholdsConfig(HT_ADC_TypeDef* HT_ADCn, u16 UPPER, u16 LOWER); 625 #endif 626 627 #if (LIBCFG_PDMA) 628 void ADC_PDMAConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_PDMA_x, ControlStatus NewState); 629 #endif 630 631 #if (LIBCFG_ADC_IVREF) 632 void ADC_VREFCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); 633 void ADC_VREFConfig(HT_ADC_TypeDef* HT_ADCn, u32 ADC_VREF_x); 634 #endif 635 636 #if (LIBCFG_ADC_VREFBUF) 637 void ADC_VREFOutputADVREFPCmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); 638 #endif 639 640 #if (LIBCFG_ADC_MVDDA) 641 void ADC_MVDDACmd(HT_ADC_TypeDef* HT_ADCn, ControlStatus NewState); 642 #endif 643 /** 644 * @} 645 */ 646 647 648 /** 649 * @} 650 */ 651 652 /** 653 * @} 654 */ 655 656 #ifdef __cplusplus 657 } 658 #endif 659 660 #endif 661