1 /*********************************************************************************************************//** 2 * @file ht32f5xxxx_can.h 3 * @version $Rev:: 8284 $ 4 * @date $Date:: 2024-11-22 #$ 5 * @brief The header file of the CAN library. 6 ************************************************************************************************************* 7 * @attention 8 * 9 * Firmware Disclaimer Information 10 * 11 * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the 12 * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the 13 * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and 14 * other intellectual property laws. 15 * 16 * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the 17 * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties 18 * other than HOLTEK and the customer. 19 * 20 * 3. The program technical documentation, including the code, is provided "as is" and for customer reference 21 * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including 22 * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including 23 * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. 24 * 25 * <h2><center>Copyright (C) Holtek Semiconductor Inc. All rights reserved</center></h2> 26 ************************************************************************************************************/ 27 28 /* Define to prevent recursive inclusion -------------------------------------------------------------------*/ 29 #ifndef __HT32F5XXXX_CAN_H 30 #define __HT32F5XXXX_CAN_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* Includes ------------------------------------------------------------------------------------------------*/ 37 #include "ht32.h" 38 39 /** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver 40 * @{ 41 */ 42 43 /** @addtogroup CAN 44 * @{ 45 */ 46 47 48 /* Exported types ------------------------------------------------------------------------------------------*/ 49 /** @defgroup CAN_Exported_Types CAN exported types 50 * @{ 51 */ 52 53 /** 54 * @brief CAN init structure definition 55 */ 56 typedef struct 57 { 58 u16 CAN_BRPrescaler; /* Synchronisation Jump Width , Range: 1~1024. */ 59 u8 CAN_Mode; /* CAN_MODE_NORMAL : Normal mode. */ 60 /* CAN_MODE_BASIC : Basic mode. */ 61 /* CAN_MODE_SILENT : Silent mode. */ 62 /* CAN_MODE_LBACK : Loop Back Mode. */ 63 /* CAN_MODE_MONITORER : Sample Point can be monitored. */ 64 /* CAN_MODE_TX_DOMINANT : CAN_TX pin drives a dominant. */ 65 /* CAN_MODE_TX_RECESSIVE : CAN_TX pin drives a recessive. */ 66 u8 CAN_SJW; /* Synchronisation Jump Width , Range: 1~4. */ 67 u8 CAN_TSEG0; /* The time segment before the sample point. */ 68 u8 CAN_TSEG1; /* The time segment after the sample point. */ 69 ControlStatus CAN_NART; /* Set the no automatic retransmission */ 70 } CAN_InitTypeDef; 71 72 /** 73 * @brief CAN receive status structure 74 */ 75 typedef enum 76 { 77 MSG_RX_FINISH, 78 MSG_OBJ_NOT_SET, 79 MSG_NOT_RECEIVED, 80 MSG_OVER_RUN 81 } CAN_RxStatus_TypeDef; 82 83 /** 84 * @brief CAN mask message structure 85 */ 86 typedef enum 87 { 88 NO_ERROR = 0, 89 STUFF_ERROR = 1, 90 FORM_ERROR = 2, 91 ACK_ERROR = 3, 92 BIT1_EROR = 4, 93 BIT0_ERROR = 5, 94 CRC_ERROR = 6, 95 NO_CHANGE = 7 96 } CAN_LastErrorCode_TypeDef; 97 98 /** 99 * @brief Message ID Type Constant structure 100 */ 101 typedef enum 102 { 103 CAN_STD_ID = 0, 104 CAN_EXT_ID = 1 105 } CAN_IdType_Enum; 106 107 /** 108 * @brief Message Frame Type Constant structure 109 */ 110 typedef enum 111 { 112 CAN_REMOTE_FRAME = 0, 113 CAN_DATA_FRAME = 1 114 } CAN_FrameType_Enum; 115 116 /** 117 * @brief CAN message structure 118 */ 119 typedef struct 120 { 121 u32 Id; /* Arbitration ID. Rang 0x0 ~ 0x1FFFFFFF */ 122 u32 IdMask; /* Arbitration ID mask. Rang 0x0 ~ 0x1FFFFFFF */ 123 u8 MsgNum; /* Message number */ 124 CAN_IdType_Enum IdType; /* CAN_STD_ID (0x0 ~ 0x7FF) or CAN_EXT_ID (0x0 ~ 0x1FFFFFFF) */ 125 CAN_FrameType_Enum FrameType; /* CAN_REMOTE_FRAME or CAN_DATA_FRAME */ 126 } CAN_MSG_TypeDef; 127 /** 128 * @} 129 */ 130 131 /* Exported constants --------------------------------------------------------------------------------------*/ 132 /** @defgroup CAN_Exported_Constants CAN exported constants 133 * @{ 134 */ 135 #define IS_CAN(x) IS_CAN0(x) 136 #define IS_CAN0(x) (x == HT_CAN0) 137 138 #define CAN_STD_FRAME_Msk 0x7FF 139 #define CAN_EXT_FRAME_MSB_Msk 0x1FFF 140 #define CAN_EXT_FRAME_LSB_Msk 0xFFFF 141 142 143 #define CAN_MODE_NORMAL 0 144 #define MSG_OBJ_TOTAL_NUM 32 145 146 /** 147 * @brief CAN CR Bit Field Definitions 148 */ 149 #define CAN_CR_TEST_Pos 7 /*!< CAN_T::CR: TEST Position */ 150 #define CAN_CR_TEST (1ul << CAN_CR_TEST_Pos) /*!< CAN_T::CR: TEST */ 151 152 #define CAN_CR_CCE_Pos 6 /*!< CAN_T::CR: CCE Position */ 153 #define CAN_CR_CCE (1ul << CAN_CR_CCE_Pos) /*!< CAN_T::CR: CCE */ 154 155 #define CAN_CR_DAR_Pos 5 /*!< CAN_T::CR: DAR Position */ 156 #define CAN_CR_DAR (1ul << CAN_CR_DAR_Pos) /*!< CAN_T::CR: DAR */ 157 158 #define CAN_CR_EIE_Pos 3 /*!< CAN_T::CR: EIE Position */ 159 #define CAN_INT_EIE (1ul << CAN_CR_EIE_Pos) /*!< CAN_T::CR: EIE */ 160 161 #define CAN_CR_SIE_Pos 2 /*!< CAN_T::CR: SIE Position */ 162 #define CAN_INT_SIE (1ul << CAN_CR_SIE_Pos) /*!< CAN_T::CR SIE */ 163 164 #define CAN_CR_IE_Pos 1 /*!< CAN_T::CR: IE Position */ 165 #define CAN_INT_IE (1ul << CAN_CR_IE_Pos) /*!< CAN_T::CR: IE */ 166 167 #define CAN_INT_ALL (CAN_INT_EIE | CAN_INT_SIE | CAN_INT_IE) 168 169 #define CAN_CR_INIT_Pos 0 /*!< CAN_T::CR: INIT Position */ 170 #define CAN_CR_INIT (1ul << CAN_CR_INIT_Pos) /*!< CAN_T::CR: INIT */ 171 172 /** 173 * @brief CAN STATUS Bit Field Definitions 174 */ 175 #define CAN_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */ 176 #define CAN_FLAG_BOFF (1ul << CAN_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Flag */ 177 178 #define CAN_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */ 179 #define CAN_FLAG_EWARN (1ul << CAN_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Flag */ 180 181 #define CAN_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */ 182 #define CAN_FLAG_EPASS (1ul << CAN_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Flag */ 183 184 #define CAN_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */ 185 #define CAN_FLAG_RXOK (1ul << CAN_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Flag */ 186 187 #define CAN_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */ 188 #define CAN_FLAG_TXOK (1ul << CAN_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Flag */ 189 190 #define CAN_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */ 191 #define CAN_LEC_Msk (0x7ul << CAN_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */ 192 193 /** 194 * @brief CAN ECR Bit Field Definitions 195 */ 196 #define CAN_ECR_RP_Pos 15 /*!< CAN_T::ECR: RP Position */ 197 #define CAN_ECR_RP_MsK (1ul << CAN_ECR_RP_Pos) /*!< CAN_T::ECR: RP */ 198 199 #define CAN_ECR_REC_Pos 8 /*!< CAN_T::ECR: REC Position */ 200 #define CAN_ECR_REC_MsK (0x7Ful << CAN_ECR_REC_Pos) /*!< CAN_T::ECR: REC Mask */ 201 202 #define CAN_ECR_TEC_Pos 0 /*!< CAN_T::ECR: TEC Position */ 203 #define CAN_ECR_TEC_MsK (0xFFul << CAN_ECR_TEC_Pos) /*!< CAN_T::ECR: TEC Mask */ 204 205 /** 206 * @brief CAN BTR Bit Field Definitions 207 */ 208 #define CAN_BTR_TSEG1_Pos 12 /*!< CAN_T::BTR: TSEG1 Position */ 209 #define CAN_BTR_TSEG1_Msk (0x7ul << CAN_BTR_TSEG1_Pos) /*!< CAN_T::BTR: TSEG1 Mask */ 210 211 #define CAN_BTR_TSEG0_Pos 8 /*!< CAN_T::BTR: TSEG0 Position */ 212 #define CAN_BTR_TSEG0_Msk (0xFul << CAN_BTR_TSEG0_Pos) /*!< CAN_T::BTR: TSEG0 Mask */ 213 214 #define CAN_BTR_SJW_Pos 6 /*!< CAN_T::BTR: SJW Position */ 215 #define CAN_BTR_SJW_Msk (0x3ul << CAN_BTR_SJW_Pos) /*!< CAN_T::BTR: SJW Mask */ 216 217 #define CAN_BTR_BRP_Pos 0 /*!< CAN_T::BTR: BRP Position */ 218 #define CAN_BTR_BRP_Msk (0x3Ful << CAN_BTR_BRP_Pos) /*!< CAN_T::BTR: BRP Mask */ 219 220 /** 221 * @brief CAN IR Bit Field Definitions 222 */ 223 #define CAN_IR_INTID_Pos 0 /*!< CAN_T::IR: INTID Position */ 224 #define CAN_IR_INTID_Msk (0xFFFFul << CAN_IR_INTID_Pos) /*!< CAN_T::IR: INTID Mask */ 225 226 /** 227 * @brief CAN TEST Bit Field Definitions 228 */ 229 #define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */ 230 #define CAN_TEST_RX (1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX */ 231 232 #define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */ 233 #define CAN_MODE_MONITORER (0x1ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: SP monitored */ 234 #define CAN_MODE_TX_DOMINANT (0x2ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX dominant */ 235 #define CAN_MODE_TX_RECESSIVE (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX recessive */ 236 237 #define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */ 238 #define CAN_MODE_LBACK (1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK */ 239 240 #define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */ 241 #define CAN_MODE_SILENT (1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent */ 242 243 #define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */ 244 #define CAN_MODE_BASIC (1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic */ 245 246 /** 247 * @brief CAN BPRE Bit Field Definitions 248 */ 249 #define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */ 250 #define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */ 251 252 /** 253 * @brief CAN IFn_CREQ Bit Field Definitions 254 */ 255 #define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_T::IFnCREQ: BUSY Position */ 256 #define CAN_FLAG_IF_BUSY (1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_T::IFnCREQ: BUSY FLAG */ 257 258 #define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_T::IFnCREQ: MSGNUM Position */ 259 #define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_T::IFnCREQ: MSGNUM Mask */ 260 261 /** 262 * @brief CAN IFn_CMASK Bit Field Definitions 263 */ 264 #define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_T::IFnCMASK: WRRD Position */ 265 #define CAN_IF_CMASK_WRRD (1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_T::IFnCMASK: WRRD */ 266 267 #define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_T::IFnCMASK: MASK Position */ 268 #define CAN_IF_CMASK_MASK (1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_T::IFnCMASK: MASK */ 269 270 #define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_T::IFnCMASK: ARB Position */ 271 #define CAN_IF_CMASK_ARB (1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_T::IFnCMASK: ARB */ 272 273 #define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_T::IFnCMASK: CONTROL Position */ 274 #define CAN_IF_CMASK_CONTROL (1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_T::IFnCMASK: CONTROL */ 275 276 #define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_T::IFnCMASK: CLRINTPND Position */ 277 #define CAN_IF_CMASK_CLRINTPND (1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_T::IFnCMASK: CLRINTPND */ 278 279 #define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_T::IFnCMASK: TXRQSTNEWDAT Position */ 280 #define CAN_IF_CMASK_TXRQSTNEWDAT (1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_T::IFnCMASK: TXRQSTNEWDAT */ 281 282 #define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_T::IFnCMASK: DATAA Position */ 283 #define CAN_IF_CMASK_DATAA (1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_T::IFnCMASK: DATAA */ 284 285 #define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_T::IFnCMASK: DATAB Position */ 286 #define CAN_IF_CMASK_DATAB (1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_T::IFnCMASK: DATAB */ 287 288 /** 289 * @brief CAN IFn_MASK0 Bit Field Definitions 290 */ 291 #define CAN_IF_MASK0_MSK_Pos 0 /*!< CAN_T::IFnMASK0: MSK Position */ 292 #define CAN_IF_MASK0_MSK_Msk (0xFFul << CAN_IF_MASK0_MSK_Pos) /*!< CAN_T::IFnMASK0: MSK Mask */ 293 294 /** 295 * @brief CAN IFn_MASK1 Bit Field Definitions 296 */ 297 #define CAN_IF_MASK1_MXTD_Pos 15 /*!< CAN_T::IFnMASK1: MXTD Position */ 298 #define CAN_IF_MASK1_MXTD (1ul << CAN_IF_MASK1_MXTD_Pos) /*!< CAN_T::IFnMASK1: MXTD */ 299 300 #define CAN_IF_MASK1_MDIR_Pos 14 /*!< CAN_T::IFnMASK1: MDIR Position */ 301 #define CAN_IF_MASK1_MDIR (1ul << CAN_IF_MASK1_MDIR_Pos) /*!< CAN_T::IFnMASK1: MDIR */ 302 303 #define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_T::IFnMASK1: MSK Position */ 304 #define CAN_IF_MASK1_MSK_Msk (0x1FFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_T::IFnMASK1: MSK Mask */ 305 306 /** 307 * @brief CAN IFn_ARB0 Bit Field Definitions 308 */ 309 #define CAN_IF_ARB0_ID_Pos 0 /*!< CAN_T::IFnARB0: ID Position */ 310 #define CAN_IF_ARB0_ID_Msk (0xFFFFul << CAN_IF_ARB0_ID_Pos) /*!< CAN_T::IFnARB0: ID Mask */ 311 312 /** 313 * @brief CAN IFn_ARB1 Bit Field Definitions 314 */ 315 #define CAN_IF_ARB1_MSGVAL_Pos 15 /*!< CAN_T::IFnARB1: MSGVAL Position */ 316 #define CAN_IF_ARB1_MSGVAL (1ul << CAN_IF_ARB1_MSGVAL_Pos) /*!< CAN_T::IFnARB1: MSGVAL */ 317 318 #define CAN_IF_ARB1_XTD_Pos 14 /*!< CAN_T::IFnARB1: XTD Position */ 319 #define CAN_IF_ARB1_XTD (1ul << CAN_IF_ARB1_XTD_Pos) /*!< CAN_T::IFnARB1: XTD */ 320 321 #define CAN_IF_ARB1_DIR_Pos 13 /*!< CAN_T::IFnARB1: DIR Position */ 322 #define CAN_IF_ARB1_DIR (1ul << CAN_IF_ARB1_DIR_Pos) /*!< CAN_T::IFnARB1: DIR */ 323 324 #define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_T::IFnARB1: ID Position */ 325 #define CAN_IF_ARB1_ID_Msk (0x1FFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_T::IFnARB1: ID Mask */ 326 327 /** 328 * @brief CAN IFn_MCR Bit Field Definitions 329 */ 330 #define CAN_IF_MCR_NEWDAT_Pos 15 /*!< CAN_T::IFnMCON: NEWDAT Position */ 331 #define CAN_IF_MCR_NEWDAT (1ul << CAN_IF_MCR_NEWDAT_Pos) /*!< CAN_T::IFnMCON: NEWDAT */ 332 333 #define CAN_IF_MCR_MSGLST_Pos 14 /*!< CAN_T::IFnMCON: MSGLST Position */ 334 #define CAN_IF_MCR_MSGLST (1ul << CAN_IF_MCR_MSGLST_Pos) /*!< CAN_T::IFnMCON: MSGLST */ 335 336 #define CAN_IF_MCR_INTPND_Pos 13 /*!< CAN_T::IFnMCON: INTPND Position */ 337 #define CAN_IF_MCR_INTPND (1ul << CAN_IF_MCR_INTPND_Pos) /*!< CAN_T::IFnMCON: INTPND */ 338 339 #define CAN_IF_MCR_UMASK_Pos 12 /*!< CAN_T::IFnMCON: UMASK Position */ 340 #define CAN_IF_MCR_UMASK (1ul << CAN_IF_MCR_UMASK_Pos) /*!< CAN_T::IFnMCON: UMASK */ 341 342 #define CAN_IF_MCR_TXIE_Pos 11 /*!< CAN_T::IFnMCON: TXIE Position */ 343 #define CAN_IF_MCR_TXIE (1ul << CAN_IF_MCR_TXIE_Pos) /*!< CAN_T::IFnMCON: TXIE */ 344 345 #define CAN_IF_MCR_RXIE_Pos 10 /*!< CAN_T::IFnMCON: RXIE Position */ 346 #define CAN_IF_MCR_RXIE (1ul << CAN_IF_MCR_RXIE_Pos) /*!< CAN_T::IFnMCON: RXIE */ 347 348 #define CAN_IF_MCR_RMTEN_Pos 9 /*!< CAN_T::IFnMCON: RMTEN Position */ 349 #define CAN_IF_MCR_RMTEN (1ul << CAN_IF_MCR_RMTEN_Pos) /*!< CAN_T::IFnMCON: RMTEN */ 350 351 #define CAN_IF_MCR_TXRQST_Pos 8 /*!< CAN_T::IFnMCON: TXRQST Position */ 352 #define CAN_IF_MCR_TXRQST (1ul << CAN_IF_MCR_TXRQST_Pos) /*!< CAN_T::IFnMCON: TXRQST */ 353 354 #define CAN_IF_MCR_EOB_Pos 7 /*!< CAN_T::IFnMCON: EOB Position */ 355 #define CAN_IF_MCR_EOB (1ul << CAN_IF_MCR_EOB_Pos) /*!< CAN_T::IFnMCON: EOB */ 356 357 #define CAN_IF_MCR_DLC_Pos 0 /*!< CAN_T::IFnMCON: DLC Position */ 358 #define CAN_IF_MCR_DLC_Msk (0xFul << CAN_IF_MCR_DLC_Pos) /*!< CAN_T::IFnMCON: DLC Mask */ 359 360 /** 361 * @brief CAN IFn_DATA_A0 Bit Field Definitions 362 */ 363 #define CAN_IF_DAT_A0_DATA1_Pos 8 /*!< CAN_T::IFnDATAA0: DATA1 Position */ 364 #define CAN_IF_DAT_A0_DATA1_Msk (0xFFul << CAN_IF_DAT_A0_DATA1_Pos) /*!< CAN_T::IFnDATAA0: DATA1 Mask */ 365 366 #define CAN_IF_DAT_A0_DATA0_Pos 0 /*!< CAN_T::IFnDATAA0: DATA0 Position */ 367 #define CAN_IF_DAT_A0_DATA0_Msk (0xFFul << CAN_IF_DAT_A0_DATA0_Pos) /*!< CAN_T::IFnDATAA0: DATA0 Mask */ 368 369 /** 370 * @brief CAN IFn_DATA_A1 Bit Field Definitions 371 */ 372 #define CAN_IF_DAT_A1_DATA3_Pos 8 /*!< CAN_T::IFnDATAA1: DATA3 Position */ 373 #define CAN_IF_DAT_A1_DATA3_Msk (0xFFul << CAN_IF_DAT_A1_DATA3_Pos) /*!< CAN_T::IFnDATAA1: DATA3 Mask */ 374 375 #define CAN_IF_DAT_A1_DATA2_Pos 0 /*!< CAN_T::IFnDATAA1: DATA2 Position */ 376 #define CAN_IF_DAT_A1_DATA2_Msk (0xFFul << CAN_IF_DAT_A1_DATA2_Pos) /*!< CAN_T::IFnDATAA1: DATA2 Mask */ 377 378 /** 379 * @brief CAN IFn_DATA_B0 Bit Field Definitions 380 */ 381 #define CAN_IF_DAT_B0_DATA5_Pos 8 /*!< CAN_T::IFnDATAB0: DATA5 Position */ 382 #define CAN_IF_DAT_B0_DATA5_Msk (0xFFul << CAN_IF_DAT_B0_DATA5_Pos) /*!< CAN_T::IFnDATAB0: DATA5 Mask */ 383 384 #define CAN_IF_DAT_B0_DATA4_Pos 0 /*!< CAN_T::IFnDATAB0: DATA4 Position */ 385 #define CAN_IF_DAT_B0_DATA4_Msk (0xFFul << CAN_IF_DAT_B0_DATA4_Pos) /*!< CAN_T::IFnDATAB0: DATA4 Mask */ 386 387 /** 388 * @brief CAN IFn_DATA_B1 Bit Field Definitions 389 */ 390 #define CAN_IF_DAT_B1_DATA7_Pos 8 /*!< CAN_T::IFnDATAB1: DATA7 Position */ 391 #define CAN_IF_DAT_B1_DATA7_Msk (0xFFul << CAN_IF_DAT_B1_DATA7_Pos) /*!< CAN_T::IFnDATAB1: DATA7 Mask */ 392 393 #define CAN_IF_DAT_B1_DATA6_Pos 0 /*!< CAN_T::IFnDATAB1: DATA6 Position */ 394 #define CAN_IF_DAT_B1_DATA6_Msk (0xFFul << CAN_IF_DAT_B1_DATA6_Pos) /*!< CAN_T::IFnDATAB1: DATA6 Mask */ 395 396 /** 397 * @brief CAN IFn_TXRQST0 Bit Field Definitions 398 */ 399 #define CAN_IF_TXRQST0_TXRQST_Pos 0 /*!< CAN_T::IFnTXRQST0: TXRQST Position */ 400 #define CAN_IF_TXRQST0_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST0_TXRQST_Pos) /*!< CAN_T::IFnTXRQST0: TXRQST Mask */ 401 402 /** 403 * @brief CAN IFn_TXRQST1 Bit Field Definitions 404 */ 405 #define CAN_IF_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::IFnTXRQST1: TXRQST Position */ 406 #define CAN_IF_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST1_TXRQST_Pos) /*!< CAN_T::IFnTXRQST1: TXRQST Mask */ 407 408 /** 409 * @brief CAN IFn_NDAT0 Bit Field Definitions 410 */ 411 #define CAN_IF_NDAT0_NEWDATA_Pos 0 /*!< CAN_T::IFnNDAT0: NEWDATA Position */ 412 #define CAN_IF_NDAT0_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT0_NEWDATA_Pos) /*!< CAN_T::IFnNDAT0: NEWDATA Mask */ 413 414 /** 415 * @brief CAN IFn_NDAT1 Bit Field Definitions 416 */ 417 #define CAN_IF_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::IFnNDAT1: NEWDATA Position */ 418 #define CAN_IF_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT1_NEWDATA_Pos) /*!< CAN_T::IFnNDAT1: NEWDATA Mask */ 419 420 /** 421 * @brief CAN IFn_IPND0 Bit Field Definitions 422 */ 423 #define CAN_IF_IPND0_INTPND_Pos 0 /*!< CAN_T::IFnIPND0: INTPND Position */ 424 #define CAN_IF_IPND0_INTPND_Msk (0xFFFFul << CAN_IF_IPND0_INTPND_Pos) /*!< CAN_T::IFnIPND0: INTPND Mask */ 425 426 /** 427 * @brief CAN IFn_IPND1 Bit Field Definitions 428 */ 429 #define CAN_IF_IPND1_INTPND_Pos 0 /*!< CAN_T::IFnIPND1: INTPND Position */ 430 #define CAN_IF_IPND1_INTPND_Msk (0xFFFFul << CAN_IF_IPND1_INTPND_Pos) /*!< CAN_T::IFnIPND1: INTPND Mask */ 431 432 /** 433 * @brief CAN IFn_MVLD0 Bit Field Definitions 434 */ 435 #define CAN_IF_MVLD0_MSGVAL_Pos 0 /*!< CAN_T::IFnMVLD0: MSGVAL Position */ 436 #define CAN_IF_MVLD0_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD0_MSGVAL_Pos) /*!< CAN_T::IFnMVLD0: MSGVAL Mask */ 437 438 /** 439 * @brief CAN IFn_MVLD1 Bit Field Definitions 440 */ 441 #define CAN_IF_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::IFnMVLD1: MSGVAL Position */ 442 #define CAN_IF_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD1_MSGVAL_Pos) /*!< CAN_T::IFnMVLD1: MSGVAL Mask */ 443 /** 444 * @} 445 */ 446 447 /* Exported functions --------------------------------------------------------------------------------------*/ 448 /** @defgroup CAN_Exported_Functions CAN exported functions 449 * @{ 450 */ 451 /* Initialization functions *********************************************************************************/ 452 void CAN_DeInit(HT_CAN_TypeDef* CANx); 453 void CAN_Init(HT_CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); 454 455 /* Interrupts and flags management functions ****************************************************************/ 456 void CAN_IntConfig(HT_CAN_TypeDef *CANx, u32 CAN_Int, ControlStatus NewState); 457 FlagStatus CAN_GetIntStatus(HT_CAN_TypeDef* CANx, u32 CAN_Int); 458 FlagStatus CAN_GetFlagStatus(HT_CAN_TypeDef* CANx, uint32_t CAN_Flag); 459 void CAN_ClearFlag(HT_CAN_TypeDef* CANx, uint32_t CAN_Flag); 460 461 /* Error management functions *******************************************************************************/ 462 CAN_LastErrorCode_TypeDef CAN_GetLastErrorCode(HT_CAN_TypeDef* CANx); 463 u32 CAN_GetReceiveErrorCounter(HT_CAN_TypeDef* CANx); 464 u32 CAN_GetLSBTransmitErrorCounter(HT_CAN_TypeDef* CANx); 465 void CAN_BusOffRecovery(HT_CAN_TypeDef *CANx); 466 467 /* Test Mode functions **************************************************************************************/ 468 void CAN_EnterTestMode(HT_CAN_TypeDef *CANx, u32 u8TestMask); 469 void CAN_LeaveTestMode(HT_CAN_TypeDef *CANx); 470 ErrStatus CAN_BasicSendMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8 len); 471 ErrStatus CAN_BasicReceiveMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8* len); 472 473 /* Transmit/Receive functions *******************************************************************************/ 474 ErrStatus CAN_Transmit(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8 len); 475 CAN_RxStatus_TypeDef CAN_Receive(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u32* len); 476 ErrStatus CAN_UpdateTxMsgData(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg, u8* data, u8 len); 477 ErrStatus CAN_TriggerTxMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg); 478 479 /* Set Rx Message Object ************************************************************************************/ 480 ErrStatus CAN_SetRxMsg(HT_CAN_TypeDef *CANx ,CAN_MSG_TypeDef* pCanMsg, u32 FifoDepth); 481 482 /* Message Object status function ***************************************************************************/ 483 ErrStatus CAN_CancelTransmit(HT_CAN_TypeDef* CANx, CAN_MSG_TypeDef* pCanMsg); 484 ErrStatus CAN_DiscardRxMsg(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg); 485 bool CAN_NewDataReceived(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg); 486 s32 CAN_TransmitStatus(HT_CAN_TypeDef* CANx, CAN_MSG_TypeDef* pCanMsg); 487 bool CAN_GetMsgPending(HT_CAN_TypeDef* CANx, CAN_MSG_TypeDef* pCanMsg); 488 ErrStatus CAN_ClearMsgPendingFlag(HT_CAN_TypeDef *CANx, CAN_MSG_TypeDef* pCanMsg); 489 void CAN_ClearAllMsgPendingFlag(HT_CAN_TypeDef *CANx); 490 /** 491 * @} 492 */ 493 494 495 /** 496 * @} 497 */ 498 499 /** 500 * @} 501 */ 502 503 #ifdef __cplusplus 504 } 505 #endif 506 507 #endif 508