1 /*********************************************************************************************************//** 2 * @file ht32f5xxxx_ckcu.h 3 * @version $Rev:: 8260 $ 4 * @date $Date:: 2024-11-05 #$ 5 * @brief The header file of the Clock Control Unit library. 6 ************************************************************************************************************* 7 * @attention 8 * 9 * Firmware Disclaimer Information 10 * 11 * 1. The customer hereby acknowledges and agrees that the program technical documentation, including the 12 * code, which is supplied by Holtek Semiconductor Inc., (hereinafter referred to as "HOLTEK") is the 13 * proprietary and confidential intellectual property of HOLTEK, and is protected by copyright law and 14 * other intellectual property laws. 15 * 16 * 2. The customer hereby acknowledges and agrees that the program technical documentation, including the 17 * code, is confidential information belonging to HOLTEK, and must not be disclosed to any third parties 18 * other than HOLTEK and the customer. 19 * 20 * 3. The program technical documentation, including the code, is provided "as is" and for customer reference 21 * only. After delivery by HOLTEK, the customer shall use the program technical documentation, including 22 * the code, at their own risk. HOLTEK disclaims any expressed, implied or statutory warranties, including 23 * the warranties of merchantability, satisfactory quality and fitness for a particular purpose. 24 * 25 * <h2><center>Copyright (C) Holtek Semiconductor Inc. All rights reserved</center></h2> 26 ************************************************************************************************************/ 27 28 /* Define to prevent recursive inclusion -------------------------------------------------------------------*/ 29 #ifndef __HT32F5XXXX_CKCU_H 30 #define __HT32F5XXXX_CKCU_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* Includes ------------------------------------------------------------------------------------------------*/ 37 #include "ht32.h" 38 39 /** @addtogroup HT32F5xxxx_Peripheral_Driver HT32F5xxxx Peripheral Driver 40 * @{ 41 */ 42 43 /** @addtogroup CKCU 44 * @{ 45 */ 46 47 48 /* Exported types ------------------------------------------------------------------------------------------*/ 49 /** @defgroup CKCU_Exported_Types CKCU exported types 50 * @{ 51 */ 52 53 #if (!LIBCFG_CKCU_NO_APB_PRESCALER) 54 /** 55 * @brief Enumeration of APB peripheral prescaler. 56 */ 57 typedef enum 58 { 59 CKCU_APBCLKPRE_DIV1 = 0, 60 CKCU_APBCLKPRE_DIV2, 61 CKCU_APBCLKPRE_DIV4, 62 CKCU_APBCLKPRE_DIV8, 63 CKCU_APBCLKPRE_DIV16, 64 CKCU_APBCLKPRE_DIV32 65 } CKCU_APBCLKPRE_TypeDef; 66 #endif 67 68 /** 69 * @brief Enumeration of CK_REF prescaler. 70 */ 71 typedef enum 72 { 73 CKCU_CKREFPRE_DIV2 = 0, 74 CKCU_CKREFPRE_DIV4, 75 CKCU_CKREFPRE_DIV6, 76 CKCU_CKREFPRE_DIV8, 77 CKCU_CKREFPRE_DIV10, 78 CKCU_CKREFPRE_DIV12, 79 CKCU_CKREFPRE_DIV14, 80 CKCU_CKREFPRE_DIV16, 81 CKCU_CKREFPRE_DIV18, 82 CKCU_CKREFPRE_DIV20, 83 CKCU_CKREFPRE_DIV22, 84 CKCU_CKREFPRE_DIV24, 85 CKCU_CKREFPRE_DIV26, 86 CKCU_CKREFPRE_DIV28, 87 CKCU_CKREFPRE_DIV30, 88 CKCU_CKREFPRE_DIV32, 89 CKCU_CKREFPRE_DIV34, 90 CKCU_CKREFPRE_DIV36, 91 CKCU_CKREFPRE_DIV38, 92 CKCU_CKREFPRE_DIV40, 93 CKCU_CKREFPRE_DIV42, 94 CKCU_CKREFPRE_DIV44, 95 CKCU_CKREFPRE_DIV46, 96 CKCU_CKREFPRE_DIV48, 97 CKCU_CKREFPRE_DIV50, 98 CKCU_CKREFPRE_DIV52, 99 CKCU_CKREFPRE_DIV54, 100 CKCU_CKREFPRE_DIV56, 101 CKCU_CKREFPRE_DIV58, 102 CKCU_CKREFPRE_DIV60, 103 CKCU_CKREFPRE_DIV62, 104 CKCU_CKREFPRE_DIV64 105 } CKCU_CKREFPRE_TypeDef; 106 107 #if (!LIBCFG_NO_PLL) 108 /** 109 * @brief Enumeration of PLL clock source. 110 */ 111 typedef enum 112 { 113 CKCU_PLLSRC_HSE = 0, 114 CKCU_PLLSRC_HSI 115 } CKCU_PLLSRC_TypeDef; 116 117 #define IS_PLL_CLKSRC(SRC) ((SRC == CKCU_PLLSRC_HSE) || \ 118 (SRC == CKCU_PLLSRC_HSI)) 119 #endif 120 121 #if (LIBCFG_CKCU_USB_PLL) 122 /** 123 * @brief Enumeration of CK_USB clock source. 124 */ 125 typedef enum 126 { 127 CKCU_CKPLL = 0, 128 CKCU_CKUSBPLL 129 } CKCU_USBSRC_TypeDef; 130 #endif 131 132 #if (LIBCFG_CKCU_LCD_SRC) 133 /** 134 * @brief Enumeration of CK_LCD clock source. 135 */ 136 typedef enum 137 { 138 CKCU_LCDSRC_LSI = 0, 139 #if (LIBCFG_LSE) 140 CKCU_LCDSRC_LSE, 141 #endif 142 CKCU_LCDSRC_HSI, 143 CKCU_LCDSRC_HSE 144 } CKCU_LCDSRC_TypeDef; 145 #endif 146 147 #if (LIBCFG_CKCU_MCTM_SRC) 148 /** 149 * @brief Enumeration of MCTM clock source. 150 */ 151 typedef enum 152 { 153 CKCU_MCTMSRC_AHB = 0, 154 CKCU_MCTMSRC_USBPLL 155 } CKCU_MCTMSRC_TypeDef; 156 157 #define IS_MCTM_SRC(SRC) ((SRC == CKCU_MCTMSRC_AHB) || \ 158 (SRC == CKCU_MCTMSRC_USBPLL)) 159 #endif 160 161 162 #if (((LIBCFG_LSE) || (LIBCFG_USBD) || (LIBCFG_CKCU_REFCLK_EXT_PIN)) && (!LIBCFG_CKCU_NO_AUTO_TRIM)) 163 /** 164 * @brief Enumeration of HSI auto-trim clock source. 165 */ 166 typedef enum 167 { 168 #if (LIBCFG_LSE) 169 CKCU_ATC_LSE = 0, 170 #endif 171 #if (LIBCFG_USBD) 172 CKCU_ATC_USB = 1, 173 #endif 174 #if (LIBCFG_CKCU_REFCLK_EXT_PIN) 175 CKCU_ATC_CKIN = 2, 176 #endif 177 } CKCU_ATC_TypeDef; 178 #endif 179 180 #if (LIBCFG_CKCU_ATM_V01) 181 /** 182 * @brief Enumeration of ATC search algorithm. 183 */ 184 typedef enum 185 { 186 CKCU_ATC_BINARY_SEARCH = 0, 187 CKCU_ATC_LINEAR_SEARCH = 8 188 } CKCU_ATCSearchAlgorithm_TypeDef; 189 190 /** 191 * @brief Enumeration of ATC frequency tolerance. 192 */ 193 typedef enum 194 { 195 CKCU_ATC_DOUBLE_PRECISION = 0, 196 CKCU_ATC_SINGLE_PRECISION = 4 197 } CKCU_ATCFrqTolerance_TypeDef; 198 #endif 199 200 /** 201 * @brief Enumeration of CK_AHB prescaler. 202 */ 203 typedef enum 204 { 205 CKCU_SYSCLK_DIV1 = 0, 206 CKCU_SYSCLK_DIV2, 207 CKCU_SYSCLK_DIV4, 208 CKCU_SYSCLK_DIV8, 209 CKCU_SYSCLK_DIV16, 210 CKCU_SYSCLK_DIV32 211 } CKCU_SYSCLKDIV_TypeDef; 212 213 /** 214 * @brief Enumeration of CK_ADC prescaler. 215 */ 216 typedef enum 217 { 218 #if (LIBCFG_CKCU_NO_ADCPRE_DIV1) 219 #else 220 CKCU_ADCPRE_DIV1 = 0, 221 #endif 222 CKCU_ADCPRE_DIV2 = 1, 223 CKCU_ADCPRE_DIV4, 224 CKCU_ADCPRE_DIV8, 225 CKCU_ADCPRE_DIV16, 226 CKCU_ADCPRE_DIV32, 227 CKCU_ADCPRE_DIV64, 228 CKCU_ADCPRE_DIV3 229 } CKCU_ADCPRE_TypeDef; 230 231 /** 232 * @brief Enumeration of CK_ADCn. 233 */ 234 typedef enum 235 { 236 CKCU_ADCPRE_ADC0 = 16, 237 #if (LIBCFG_ADC1) 238 CKCU_ADCPRE_ADC1 = 20, 239 #endif 240 } CKCU_ADCPRE_ADCn_TypeDef; 241 242 #if (LIBCFG_LCD) 243 /** 244 * @brief Enumeration of CK_LCD prescaler. 245 */ 246 typedef enum 247 { 248 CKCU_LCDPRE_DIV1 = 0, 249 CKCU_LCDPRE_DIV2, 250 CKCU_LCDPRE_DIV4, 251 CKCU_LCDPRE_DIV8, 252 CKCU_LCDPRE_DIV16, 253 } CKCU_LCDPRE_TypeDef; 254 #endif 255 256 #if (LIBCFG_MIDI) 257 /** 258 * @brief Enumeration of CK_MIDI prescaler. 259 */ 260 typedef enum 261 { 262 CKCU_MIDIPRE_DIV16 = 0, 263 CKCU_MIDIPRE_DIV13, 264 CKCU_MIDIPRE_DIV11, 265 CKCU_MIDIPRE_DIV9, 266 CKCU_MIDIPRE_DIV8, 267 } CKCU_MIDIPRE_TypeDef; 268 #endif 269 270 /** 271 * @brief Enumeration of System clock source. 272 */ 273 typedef enum 274 { 275 #if (!LIBCFG_NO_PLL) 276 CKCU_SW_PLL = 1, 277 #endif 278 CKCU_SW_HSE = 2, 279 CKCU_SW_HSI = 3, 280 #if (LIBCFG_LSE) 281 CKCU_SW_LSE = 6, 282 #endif 283 CKCU_SW_LSI = 7 284 } CKCU_SW_TypeDef; 285 286 /** 287 * @brief Enumeration of CKOUT clock source. 288 */ 289 typedef enum 290 { 291 CKCU_CKOUTSRC_REFCK = 0, 292 CKCU_CKOUTSRC_HCLK_DIV16 = 1, 293 CKCU_CKOUTSRC_SYSCK_DIV16 = 2, 294 CKCU_CKOUTSRC_HSECK_DIV16 = 3, 295 CKCU_CKOUTSRC_HSICK_DIV16 = 4, 296 #if (LIBCFG_LSE) 297 CKCU_CKOUTSRC_LSECK = 5, 298 #endif 299 CKCU_CKOUTSRC_LSICK = 6 300 } CKCU_CKOUTSRC_TypeDef; 301 302 #if (!LIBCFG_NO_PLL) 303 /** 304 * @brief Enumeration of PLL clock source status. 305 */ 306 typedef enum 307 { 308 CKCU_PLLST_SYSCK = 1, 309 #if (LIBCFG_USBD) 310 CKCU_PLLST_USB = 4, 311 #endif 312 CKCU_PLLST_REFCK = 8 313 } CKCU_PLLST_TypeDef; 314 #endif 315 316 /** 317 * @brief Enumeration of HSI clock source status. 318 */ 319 typedef enum 320 { 321 CKCU_HSIST_SYSCK = 1, 322 #if (!LIBCFG_NO_PLL) 323 CKCU_HSIST_PLL = 2, 324 #endif 325 CKCU_HSIST_CKM = 4 326 } CKCU_HSIST_TypeDef; 327 328 /** 329 * @brief Enumeration of HSE clock source status. 330 */ 331 typedef enum 332 { 333 CKCU_HSEST_SYSCK = 1, 334 #if (!LIBCFG_NO_PLL) 335 CKCU_HSEST_PLL 336 #endif 337 } CKCU_HSEST_TypeDef; 338 339 /** 340 * @brief Definition of CKOUT Init Structure. 341 */ 342 typedef struct 343 { 344 CKCU_CKOUTSRC_TypeDef CKOUTSRC; 345 } CKCU_CKOUTInitTypeDef; 346 347 #if (!LIBCFG_NO_PLL) 348 /** 349 * @brief Definition of PLL Init Structure. 350 */ 351 typedef struct 352 { 353 u32 CFG; 354 CKCU_PLLSRC_TypeDef ClockSource; 355 ControlStatus BYPASSCmd; 356 } CKCU_PLLInitTypeDef; 357 #endif 358 359 /** 360 * @brief Definition of structure for clock frequency. 361 */ 362 typedef struct 363 { 364 #if (!LIBCFG_NO_PLL) 365 u32 PLL_Freq; 366 #endif 367 u32 SYSCK_Freq; 368 u32 HCLK_Freq; 369 #if (HT32_LIB_ENABLE_GET_CK_ADC) 370 #if (!LIBCFG_NO_ADC) 371 u32 ADC0_Freq; 372 #endif 373 #if (LIBCFG_ADC1) 374 u32 ADC1_Freq; 375 #endif 376 #endif 377 } CKCU_ClocksTypeDef; 378 379 #if (LIBCFG_CKCU_ATM_V01) 380 /** 381 * @brief Definition of ATC Init Structure. 382 */ 383 typedef struct 384 { 385 CKCU_ATCSearchAlgorithm_TypeDef SearchAlgorithm; 386 CKCU_ATCFrqTolerance_TypeDef FrqTolerance; 387 } CKCU_ATCInitTypeDef; 388 #endif 389 390 /** 391 * @brief Definition of initial structure of peripheral clock control. 392 */ 393 typedef union 394 { 395 struct 396 { 397 /* Definitions of AHB clock control */ 398 unsigned long FMC :1; // Bit 0 399 unsigned long :1; // Bit 1 400 unsigned long SRAM :1; // Bit 2 401 unsigned long :1; // Bit 3 402 unsigned long PDMA :1; // Bit 4 403 unsigned long BM :1; // Bit 5 404 unsigned long APB :1; // Bit 6 405 unsigned long :1; // Bit 7 406 407 unsigned long :1; // Bit 8 408 unsigned long :1; // Bit 9 409 unsigned long USBD :1; // Bit 10 410 unsigned long CKREF :1; // Bit 11 411 unsigned long EBI :1; // Bit 12 412 unsigned long CRC :1; // Bit 13 413 unsigned long :1; // Bit 14 414 unsigned long AES :1; // Bit 15 415 416 unsigned long PA :1; // Bit 16 417 unsigned long PB :1; // Bit 17 418 unsigned long PC :1; // Bit 18 419 unsigned long PD :1; // Bit 19 420 unsigned long PE :1; // Bit 20 421 unsigned long PF :1; // Bit 21 422 unsigned long :1; // Bit 22 423 unsigned long :1; // Bit 23 424 425 unsigned long DIV :1; // Bit 24 426 unsigned long QSPI :1; // Bit 25 427 unsigned long RF :1; // Bit 26 428 unsigned long PID0 :1; // Bit 27 429 unsigned long :1; // Bit 28 430 unsigned long CORDIC :1; // Bit 29 431 unsigned long :1; // Bit 30 432 unsigned long :1; // Bit 31 433 434 /* Definitions of APB0 clock control */ 435 unsigned long I2C0 :1; // Bit 0 436 unsigned long I2C1 :1; // Bit 1 437 unsigned long I2C2 :1; // Bit 2 438 unsigned long :1; // Bit 3 439 unsigned long SPI0 :1; // Bit 4 440 unsigned long SPI1 :1; // Bit 5 441 unsigned long :1; // Bit 6 442 unsigned long :1; // Bit 7 443 444 unsigned long USART0 :1; // Bit 8 445 unsigned long USART1 :1; // Bit 9 446 unsigned long UART0 :1; // Bit 10 447 unsigned long UART1 :1; // Bit 11 448 unsigned long UART2 :1; // Bit 12 449 unsigned long UART3 :1; // Bit 13 450 unsigned long AFIO :1; // Bit 14 451 unsigned long EXTI :1; // Bit 15 452 453 unsigned long :1; // Bit 16 454 unsigned long :1; // Bit 17 455 unsigned long :1; // Bit 18 456 unsigned long :1; // Bit 19 457 unsigned long :1; // Bit 20 458 unsigned long :1; // Bit 21 459 unsigned long SLED0 :1; // Bit 22 460 unsigned long SLED1 :1; // Bit 23 461 462 unsigned long SCI0 :1; // Bit 24 463 unsigned long I2S :1; // Bit 25 464 unsigned long :1; // Bit 26 465 unsigned long SCI1 :1; // Bit 27 466 unsigned long MIDI :1; // Bit 28 467 unsigned long LEDC :1; // Bit 29 468 unsigned long CAN0 :1; // Bit 30 469 unsigned long :1; // Bit 31 470 471 /* Definitions of APB1 clock control */ 472 unsigned long MCTM0 :1; // Bit 0 473 unsigned long :1; // Bit 1 474 unsigned long :1; // Bit 2 475 unsigned long :1; // Bit 3 476 unsigned long WDT :1; // Bit 4 477 unsigned long :1; // Bit 5 478 unsigned long BKP :1; // Bit 6 479 unsigned long DAC1 :1; // Bit 7 480 481 unsigned long GPTM0 :1; // Bit 8 482 unsigned long GPTM1 :1; // Bit 9 483 unsigned long :1; // Bit 10 484 unsigned long :1; // Bit 11 485 unsigned long PWM0 :1; // Bit 12 486 unsigned long PWM1 :1; // Bit 13 487 unsigned long PWM2 :1; // Bit 14 488 unsigned long :1; // Bit 15 489 490 unsigned long BFTM0 :1; // Bit 16 491 unsigned long BFTM1 :1; // Bit 17 492 unsigned long TKEY :1; // Bit 18 493 unsigned long LCDR :1; // Bit 19 494 unsigned long LCDC :1; // Bit 20 495 unsigned long DAC0 :1; // Bit 21 496 unsigned long CMP :1; // Bit 22 497 #if defined(USE_HT32F66242) || defined(USE_HT32F66246) 498 unsigned long PGA :1; // Bit 23 499 #else 500 unsigned long OPA :1; // Bit 23 501 #endif 502 unsigned long ADC0 :1; // Bit 24 503 unsigned long ADC1 :1; // Bit 25 504 unsigned long :1; // Bit 26 505 unsigned long :1; // Bit 27 506 unsigned long SCTM0 :1; // Bit 28 507 unsigned long SCTM1 :1; // Bit 29 508 unsigned long SCTM2 :1; // Bit 30 509 unsigned long SCTM3 :1; // Bit 31 510 } Bit; 511 u32 Reg[3]; 512 } CKCU_PeripClockConfig_TypeDef; 513 514 #define CKCU_APBPCSR_OFFSET (5) 515 #define CKCU_APBPCSR0 (0 << CKCU_APBPCSR_OFFSET) 516 #define CKCU_APBPCSR1 (1 << CKCU_APBPCSR_OFFSET) 517 #define CKCU_APBPCSR2 (4 << CKCU_APBPCSR_OFFSET) 518 typedef enum 519 { 520 CKCU_PCLK_I2C0 = (CKCU_APBPCSR0 | 0), 521 #if (LIBCFG_I2C1) 522 CKCU_PCLK_I2C1 = (CKCU_APBPCSR0 | 2), 523 #endif 524 CKCU_PCLK_SPI0 = (CKCU_APBPCSR0 | 4), 525 #if (LIBCFG_SPI1) 526 CKCU_PCLK_SPI1 = (CKCU_APBPCSR0 | 6), 527 #endif 528 #if (LIBCFG_UART2) 529 CKCU_PCLK_UART2 = (CKCU_APBPCSR0 | 8), 530 #endif 531 #if (LIBCFG_UART3) 532 CKCU_PCLK_UART3 = (CKCU_APBPCSR0 | 10), 533 #endif 534 CKCU_PCLK_BFTM0 = (CKCU_APBPCSR0 | 12), 535 #if (LIBCFG_BFTM1) 536 CKCU_PCLK_BFTM1 = (CKCU_APBPCSR0 | 14), 537 #endif 538 #if (LIBCFG_MCTM0) 539 CKCU_PCLK_MCTM0 = (CKCU_APBPCSR0 | 16), 540 #endif 541 #if (!LIBCFG_NO_GPTM0) 542 CKCU_PCLK_GPTM0 = (CKCU_APBPCSR0 | 20), 543 #endif 544 #if (LIBCFG_GPTM1) 545 CKCU_PCLK_GPTM1 = (CKCU_APBPCSR0 | 22), 546 #endif 547 #if (!LIBCFG_NO_USART0) 548 CKCU_PCLK_USART0 = (CKCU_APBPCSR0 | 24), 549 #endif 550 #if (LIBCFG_USART1) 551 CKCU_PCLK_USART1 = (CKCU_APBPCSR0 | 26), 552 #endif 553 CKCU_PCLK_UART0 = (CKCU_APBPCSR0 | 28), 554 #if (LIBCFG_UART1) 555 CKCU_PCLK_UART1 = (CKCU_APBPCSR0 | 30), 556 #endif 557 CKCU_PCLK_AFIO = (CKCU_APBPCSR1 | 0), 558 CKCU_PCLK_EXTI = (CKCU_APBPCSR1 | 2), 559 #if (!LIBCFG_NO_ADC) 560 CKCU_PCLK_ADC0 = (CKCU_APBPCSR1 | 4), 561 #endif 562 #if (LIBCFG_ADC1) 563 CKCU_PCLK_ADC1 = (CKCU_APBPCSR1 | 6), 564 #endif 565 #if (LIBCFG_CMP) 566 CKCU_PCLK_CMP = (CKCU_APBPCSR1 | 8), 567 #endif 568 #if (LIBCFG_OPA) 569 CKCU_PCLK_OPA = (CKCU_APBPCSR1 | 10), 570 #endif 571 #if (LIBCFG_PGA) 572 CKCU_PCLK_PGA = (CKCU_APBPCSR1 | 10), 573 #endif 574 CKCU_PCLK_WDTR = (CKCU_APBPCSR1 | 12), 575 CKCU_PCLK_BKPR = (CKCU_APBPCSR1 | 14), 576 #if (LIBCFG_SCI0) 577 CKCU_PCLK_SCI0 = (CKCU_APBPCSR1 | 16), 578 #endif 579 #if (LIBCFG_SCI1) 580 CKCU_PCLK_SCI1 = (CKCU_APBPCSR1 | 18), 581 #endif 582 #if (LIBCFG_I2S) 583 CKCU_PCLK_I2S = (CKCU_APBPCSR1 | 20), 584 #endif 585 #if (LIBCFG_I2C2) 586 CKCU_PCLK_I2C2 = (CKCU_APBPCSR1 | 22), 587 #endif 588 #if (LIBCFG_SCTM0) 589 CKCU_PCLK_SCTM0 = (CKCU_APBPCSR1 | 24), 590 #endif 591 #if (LIBCFG_SCTM1) 592 CKCU_PCLK_SCTM1 = (CKCU_APBPCSR1 | 26), 593 #endif 594 #if (LIBCFG_SCTM2) 595 CKCU_PCLK_SCTM2 = (CKCU_APBPCSR1 | 28), 596 #endif 597 #if (LIBCFG_SCTM3) 598 CKCU_PCLK_SCTM3 = (CKCU_APBPCSR1 | 30), 599 #endif 600 #if (LIBCFG_AFE0006) 601 CKCU_PCLK_AFE = (CKCU_APBPCSR2 | 0), 602 #endif 603 #if (LIBCFG_DACDUAL16) || (LIBCFG_DAC0) 604 CKCU_PCLK_DAC0 = (CKCU_APBPCSR2 | 2), 605 #endif 606 #if (LIBCFG_LEDC) 607 CKCU_PCLK_LEDC = (CKCU_APBPCSR2 | 6), 608 #endif 609 #if (LIBCFG_MIDI) 610 CKCU_PCLK_MIDI = (CKCU_APBPCSR2 | 8), 611 #endif 612 #if (LIBCFG_TKEY) 613 CKCU_PCLK_TKEY = (CKCU_APBPCSR2 | 10), 614 #endif 615 #if (LIBCFG_SLED0) 616 CKCU_PCLK_SLED0 = (CKCU_APBPCSR2 | 12), 617 #endif 618 #if (LIBCFG_SLED1) 619 CKCU_PCLK_SLED1 = (CKCU_APBPCSR2 | 14), 620 #endif 621 #if (LIBCFG_PWM0) 622 CKCU_PCLK_PWM0 = (CKCU_APBPCSR2 | 16), 623 #endif 624 #if (LIBCFG_PWM1) 625 CKCU_PCLK_PWM1 = (CKCU_APBPCSR2 | 18), 626 #endif 627 #if (LIBCFG_PWM2) 628 CKCU_PCLK_PWM2 = (CKCU_APBPCSR2 | 20), 629 #endif 630 #if (LIBCFG_CAN0) 631 CKCU_PCLK_CAN0 = (CKCU_APBPCSR2 | 20), 632 #endif 633 #if (LIBCFG_DAC1) 634 CKCU_PCLK_DAC1 = (CKCU_APBPCSR2 | 24), 635 #endif 636 } CKCU_PeripPrescaler_TypeDef; 637 638 #define CKCU_PCLK_ADC CKCU_PCLK_ADC0 639 /** 640 * @} 641 */ 642 643 /* Exported constants --------------------------------------------------------------------------------------*/ 644 /** @defgroup CKCU_Exported_Constants CKCU exported constants 645 * @{ 646 */ 647 648 /* Definitions of clock ready flag */ 649 #if (LIBCFG_CKCU_USB_PLL) 650 #define CKCU_FLAG_USBPLLRDY (1UL) 651 #endif 652 #if (!LIBCFG_NO_PLL) 653 #define CKCU_FLAG_PLLRDY (1UL << 1) 654 #endif 655 #define CKCU_FLAG_HSERDY (1UL << 2) 656 #define CKCU_FLAG_HSIRDY (1UL << 3) 657 #if (LIBCFG_LSE) 658 #define CKCU_FLAG_LSERDY (1UL << 4) 659 #endif 660 #define CKCU_FLAG_LSIRDY (1UL << 5) 661 662 #define IS_CKCU_FLAG(FLAG) (((FLAG & 0xFFFFFFC0) == 0) && (FLAG != 0)) 663 664 /* Definitions of clock interrupt & flag */ 665 #define CKCU_INT_CKS (1UL) 666 #define IS_CKCU_INT_FLAG(FLAG) (FLAG == CKCU_INT_CKS) 667 668 #define CKCU_INT_CKSIE (1UL << 16) 669 #define IS_CKCU_INT(INT) (((INT & 0xFFFEFFFF) == 0) && (INT != 0)) 670 671 #if (!LIBCFG_NO_PLL) 672 /* Definitions of PLL frequency */ 673 #define CKCU_PLL_4M_48M ((12UL << 23) | (0UL << 21)) 674 #define CKCU_PLL_4M_40M ((10UL << 23) | (0UL << 21)) 675 #define CKCU_PLL_8M_48M (( 6UL << 23) | (0UL << 21)) 676 #define CKCU_PLL_8M_40M (( 5UL << 23) | (0UL << 21)) 677 #define CKCU_PLL_8M_32M (( 4UL << 23) | (0UL << 21)) 678 #define CKCU_PLL_12M_48M (( 4UL << 23) | (0UL << 21)) 679 #define CKCU_PLL_16M_48M (( 3UL << 23) | (0UL << 21)) 680 681 #if (LIBCFG_CKCU_SYS_CK_60M) 682 #define CKCU_PLL_4M_60M ((0UL << 28) | (15UL << 23) | (0UL << 21)) 683 #define CKCU_PLL_8M_60M ((1UL << 28) | (15UL << 23) | (0UL << 21)) 684 #define CKCU_PLL_12M_60M ((0UL << 28) | ( 5UL << 23) | (0UL << 21)) 685 #define CKCU_PLL_16M_56M ((1UL << 28) | ( 7UL << 23) | (0UL << 21)) 686 #endif 687 688 #if (LIBCFG_CKCU_SYS_CK_80M) 689 #define CKCU_PLL_4M_80M ((0UL << 28) | (20UL << 23) | (0UL << 21)) 690 #define CKCU_PLL_8M_80M ((0UL << 28) | (10UL << 23) | (0UL << 21)) 691 #define CKCU_PLL_12M_78M ((1UL << 28) | (13UL << 23) | (0UL << 21)) 692 #define CKCU_PLL_16M_80M ((0UL << 28) | ( 5UL << 23) | (0UL << 21)) 693 #endif 694 695 #define IS_PLL_CFG(CFG) (((CFG & 0xE81FFFFF) == 0x0) && (CFG != 0)) 696 #endif 697 698 #if (LIBCFG_CKCU_USB_PLL) 699 /* Definitions of USBPLL frequency */ 700 #if (LIBCFG_CKCU_USB_PLL_96M) 701 #define CKCU_USBPLL_4M_96M ((24UL << 7) | (0UL << 5)) 702 #define CKCU_USBPLL_8M_96M ((12UL << 7) | (0UL << 5)) 703 #define CKCU_USBPLL_12M_96M (( 8UL << 7) | (0UL << 5)) 704 #define CKCU_USBPLL_16M_96M (( 6UL << 7) | (0UL << 5)) 705 #else 706 #define CKCU_USBPLL_4M_48M ((12UL << 7) | (0UL << 5)) 707 #define CKCU_USBPLL_8M_48M (( 6UL << 7) | (0UL << 5)) 708 #define CKCU_USBPLL_12M_48M (( 4UL << 7) | (0UL << 5)) 709 #define CKCU_USBPLL_16M_48M (( 3UL << 7) | (0UL << 5)) 710 #endif 711 712 #define IS_USBPLL_CFG(CFG) (((CFG & 0xFFFFF81F) == 0x0) && (CFG != 0)) 713 #endif 714 715 /* Definitions of MCU debug control */ 716 #define CKCU_DBG_SLEEP (1UL) 717 #define CKCU_DBG_DEEPSLEEP1 (1UL << 1) 718 #if (!LIBCFG_PWRCU_NO_PD_MODE) 719 #define CKCU_DBG_POWERDOWN (1UL << 2) 720 #endif 721 #define CKCU_DBG_WDT_HALT (1UL << 3) 722 723 #if (LIBCFG_MCTM0) 724 #define CKCU_DBG_MCTM0_HALT (1UL << 4) 725 #endif 726 727 #if (!LIBCFG_NO_GPTM0) 728 #define CKCU_DBG_GPTM0_HALT (1UL << 6) 729 #endif 730 731 #if (LIBCFG_GPTM1) 732 #define CKCU_DBG_GPTM1_HALT (1UL << 7) 733 #endif 734 735 #if (!LIBCFG_NO_USART0) 736 #define CKCU_DBG_USART0_HALT (1UL << 8) 737 #endif 738 739 #if (LIBCFG_USART1) 740 #define CKCU_DBG_USART1_HALT (1UL << 9) 741 #endif 742 743 #define CKCU_DBG_SPI0_HALT (1UL << 10) 744 745 #if (LIBCFG_SPI1) 746 #define CKCU_DBG_SPI1_HALT (1UL << 11) 747 #endif 748 749 #if defined(USE_HT32F0006) || defined(USE_HT32F61244_45) 750 #define CKCU_DBG_QSPI_HALT (1UL << 11) 751 #endif 752 753 #define CKCU_DBG_I2C0_HALT (1UL << 12) 754 755 #if (LIBCFG_I2C1) 756 #define CKCU_DBG_I2C1_HALT (1UL << 13) 757 #endif 758 759 #define CKCU_DBG_DEEPSLEEP2 (1UL << 14) 760 761 #if (LIBCFG_SCI0) 762 #define CKCU_DBG_SCI0_HALT (1UL << 15) 763 #endif 764 765 #define CKCU_DBG_BFTM0_HALT (1UL << 16) 766 767 #if (LIBCFG_BFTM1) 768 #define CKCU_DBG_BFTM1_HALT (1UL << 17) 769 #endif 770 771 #define CKCU_DBG_UART0_HALT (1UL << 18) 772 773 #if (LIBCFG_UART1) 774 #define CKCU_DBG_UART1_HALT (1UL << 19) 775 #endif 776 777 #if (LIBCFG_SCI1) 778 #define CKCU_DBG_SCI1_HALT (1UL << 21) 779 #endif 780 781 #if (LIBCFG_SCTM0) 782 #define CKCU_DBG_SCTM0_HALT (1UL << 22) 783 #endif 784 785 #if (LIBCFG_SCTM1) 786 #define CKCU_DBG_SCTM1_HALT (1UL << 23) 787 #endif 788 789 #if (LIBCFG_SCTM2) 790 #define CKCU_DBG_SCTM2_HALT (1UL << 24) 791 #endif 792 793 #if (LIBCFG_SCTM3) 794 #define CKCU_DBG_SCTM3_HALT (1UL << 25) 795 #endif 796 797 #if (LIBCFG_CAN0) 798 #define CKCU_DBG_CAN0_HALT (1UL << 26) 799 #endif 800 801 #if (LIBCFG_UART2) 802 #define CKCU_DBG_UART2_HALT (1UL << 26) 803 #endif 804 805 #if (LIBCFG_UART3) 806 #define CKCU_DBG_UART3_HALT (1UL << 27) 807 #endif 808 809 #if (LIBCFG_I2C2) 810 #define CKCU_DBG_I2C2_HALT (1UL << 28) 811 #endif 812 813 #if (LIBCFG_PWM2) 814 #define CKCU_DBG_PWM2_HALT (1UL << 29) 815 #endif 816 817 #if defined(USE_HT32F52357_67) 818 #define CKCU_DBG_QSPI_HALT (1UL << 29) 819 #endif 820 821 #if (LIBCFG_PWM0) 822 #define CKCU_DBG_PWM0_HALT (1UL << 30) 823 #endif 824 825 #if (LIBCFG_PWM1) 826 #define CKCU_DBG_PWM1_HALT (1UL << 31) 827 #endif 828 829 #define IS_CKCU_DBG(MODE) (((MODE & ~(0xFFEFFFDF)) == 0) && (MODE != 0)) 830 831 /* Definitions of AHB clock control */ 832 #define CKCU_AHBEN_SLEEP_FMC (1UL) 833 #define CKCU_AHBEN_SLEEP_SRAM (1UL << 2) 834 #define CKCU_AHBEN_SLEEP_BM (1UL << 5) 835 #define CKCU_AHBEN_SLEEP_APB0 (1UL << 6) 836 837 #define IS_CKCU_SLEEP_AHB(PERIPH) (((PERIPH & 0xFFFFFF9A) == 0) && (PERIPH != 0)) 838 839 /* Definitions of HSI Ready Counter Value */ 840 #if (LIBCFG_CKCU_HSIRDYCR) 841 #define IS_COUNTER_VALUE(VALUE) ((VALUE) < 0x20) 842 #endif 843 844 /* HSE Gain mode */ 845 #define CKCU_HSE_LOW_GAIN_MODE (0UL << 8) 846 #define CKCU_HSE_HIGH_GAIN_MODE (1UL << 8) 847 848 #define IS_GAINMODE(GanMode) ((GanMode == CKCU_HSE_LOW_GAIN_MODE) || \ 849 (GanMode == CKCU_HSE_HIGH_GAIN_MODE)) 850 851 /** 852 * @} 853 */ 854 855 /* Exported functions --------------------------------------------------------------------------------------*/ 856 /** @defgroup CKCU_Exported_Functions CKCU exported functions 857 * @{ 858 */ 859 void CKCU_DeInit(void); 860 861 void CKCU_HSICmd(ControlStatus Cmd); 862 void CKCU_HSECmd(ControlStatus Cmd); 863 bool CKCU_IS_HSI_USED(CKCU_HSIST_TypeDef Target); 864 bool CKCU_IS_HSE_USED(CKCU_HSEST_TypeDef Target); 865 FlagStatus CKCU_GetClockReadyStatus(u32 CKCU_FLAG); 866 ErrStatus CKCU_WaitHSEReady(void); 867 868 ErrStatus CKCU_SysClockConfig(CKCU_SW_TypeDef CLKSRC); 869 u32 CKCU_GetSysClockSource(void); 870 871 void CKCU_PeripClockConfig(CKCU_PeripClockConfig_TypeDef Clock, ControlStatus Cmd); 872 873 #if (LIBCFG_NO_PLL) 874 #else 875 void CKCU_PLLInit(CKCU_PLLInitTypeDef *PLL_InitStruct); 876 void CKCU_PLLCmd(ControlStatus Cmd); 877 bool CKCU_IS_PLL_USED(CKCU_PLLST_TypeDef Target); 878 #endif 879 880 #if (LIBCFG_CKCU_USB_PLL) 881 void CKCU_USBPLLInit(CKCU_PLLInitTypeDef *USBPLL_InitStruct); 882 void CKCU_USBPLLCmd(ControlStatus Cmd); 883 void CKCU_USBClockConfig(CKCU_USBSRC_TypeDef USBSRC); 884 #endif 885 886 #if (LIBCFG_CKCU_LCD_SRC) 887 void CKCU_LCDClockConfig(CKCU_LCDSRC_TypeDef LCDSRC); 888 #endif 889 890 #if (LIBCFG_CKCU_MCTM_SRC) 891 void CKCU_MCTMClockConfig(CKCU_MCTMSRC_TypeDef CKCU_MCTMSRC_x); 892 #endif 893 894 void CKCU_SleepClockConfig(u32 CKCU_CLK, ControlStatus Cmd); 895 896 void CKCU_SetHCLKPrescaler(CKCU_SYSCLKDIV_TypeDef HCLKPRE); 897 void CKCU_SetCKREFPrescaler(CKCU_CKREFPRE_TypeDef CKREFPRE); 898 void CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADCn_TypeDef CKCU_ADCPRE_ADCn, CKCU_ADCPRE_TypeDef CKCU_ADCPRE_DIVn); 899 #define CKCU_SetADCPrescaler(DIV) CKCU_SetADCnPrescaler(CKCU_ADCPRE_ADC0, DIV) 900 901 #if (LIBCFG_MIDI) 902 void CKCU_SetMIDIPrescaler(CKCU_MIDIPRE_TypeDef MIDIPRE); 903 #endif 904 905 #if (!LIBCFG_CKCU_NO_APB_PRESCALER) 906 void CKCU_SetPeripPrescaler(CKCU_PeripPrescaler_TypeDef Perip, CKCU_APBCLKPRE_TypeDef PCLKPRE); 907 #endif 908 909 void CKCU_GetClocksFrequency(CKCU_ClocksTypeDef* CKCU_Clk); 910 u32 CKCU_GetPLLFrequency(void); 911 u32 CKCU_GetPeripFrequency(CKCU_PeripPrescaler_TypeDef Perip); 912 913 void CKCU_CKMCmd(ControlStatus Cmd); 914 void CKCU_PSRCWKUPCmd(ControlStatus Cmd); 915 916 #if (!LIBCFG_CKCU_NO_LPCR) 917 void CKCU_BKISOCmd(ControlStatus Cmd); 918 #endif 919 920 void CKCU_CKOUTConfig(CKCU_CKOUTInitTypeDef *CKOUTInit); 921 void CKCU_MCUDBGConfig(u32 CKCU_DBGx, ControlStatus Cmd); 922 923 void CKCU_IntConfig(u32 CKCU_INT, ControlStatus Cmd); 924 FlagStatus CKCU_GetIntStatus(u32 CKCU_INT); 925 void CKCU_ClearIntFlag(u32 CKCU_INT); 926 927 #if (((LIBCFG_LSE) || (LIBCFG_USBD) || (LIBCFG_CKCU_REFCLK_EXT_PIN)) && (!LIBCFG_CKCU_NO_AUTO_TRIM)) 928 #if (LIBCFG_CKCU_ATM_V01) 929 void CKCU_ATCInit(CKCU_ATCInitTypeDef* ATC_InitStruct); 930 #endif 931 void CKCU_HSIAutoTrimClkConfig(CKCU_ATC_TypeDef CLKSRC); 932 void CKCU_HSIAutoTrimCmd(ControlStatus Cmd); 933 bool CKCU_HSIAutoTrimIsReady(void); 934 #endif 935 936 #if (LIBCFG_CKCU_HSIRDYCR) 937 void CKCU_SetHSIReadyCounter(u8 value); 938 #endif 939 940 void CKCU_SetHSEGainMode(u32 GanMode); 941 942 /** 943 * @} 944 */ 945 946 947 /** 948 * @} 949 */ 950 951 /** 952 * @} 953 */ 954 955 #ifdef __cplusplus 956 } 957 #endif 958 959 #endif 960