1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2019-04-25 tyx the first version 9 */ 10 11 #ifndef __HW_CRC_H__ 12 #define __HW_CRC_H__ 13 14 #include <hwcrypto.h> 15 16 #define CRC_FLAG_REFIN (0x1 << 0) 17 #define CRC_FLAG_REFOUT (0x1 << 1) 18 19 #define HWCRYPTO_CRC8_CFG \ 20 { \ 21 .last_val = 0x00, \ 22 .poly = 0x07, \ 23 .width = 8, \ 24 .xorout = 0x00, \ 25 .flags = 0, \ 26 } 27 28 #define HWCRYPTO_CRC16_CFG \ 29 { \ 30 .last_val = 0x0000, \ 31 .poly = 0x8005, \ 32 .width = 16, \ 33 .xorout = 0x0000, \ 34 .flags = 0, \ 35 } 36 37 #define HWCRYPTO_CRC32_CFG \ 38 { \ 39 .last_val = 0x00000000, \ 40 .poly = 0x04C11DB7, \ 41 .width = 32, \ 42 .xorout = 0x00000000, \ 43 .flags = 0, \ 44 } 45 46 #define HWCRYPTO_CRC_CCITT_CFG \ 47 { \ 48 .last_val = 0x0000, \ 49 .poly = 0x1021, \ 50 .width = 16, \ 51 .xorout = 0x0000, \ 52 .flags = CRC_FLAG_REFIN | CRC_FLAG_REFOUT, \ 53 } 54 55 #define HWCRYPTO_CRC_DNP_CFG \ 56 { \ 57 .last_val = 0x0000, \ 58 .poly = 0x3D65, \ 59 .width = 16, \ 60 .xorout = 0xffff, \ 61 .flags = CRC_FLAG_REFIN | CRC_FLAG_REFOUT, \ 62 } 63 64 #ifdef __cplusplus 65 extern "C" { 66 #endif 67 68 struct hwcrypto_crc; 69 70 typedef enum 71 { 72 HWCRYPTO_CRC_CUSTOM, /**< Custom CRC mode */ 73 HWCRYPTO_CRC_CRC8, /**< poly : 0x07 */ 74 HWCRYPTO_CRC_CRC16, /**< poly : 0x8005 */ 75 HWCRYPTO_CRC_CRC32, /**< poly : 0x04C11DB7 */ 76 HWCRYPTO_CRC_CCITT, /**< poly : 0x1021 */ 77 HWCRYPTO_CRC_DNP, /**< poly : 0x3D65 */ 78 } hwcrypto_crc_mode; 79 80 struct hwcrypto_crc_cfg 81 { 82 rt_uint32_t last_val; /**< Last CRC value cache */ 83 rt_uint32_t poly; /**< CRC polynomial */ 84 rt_uint16_t width; /**< CRC value width */ 85 rt_uint32_t xorout; /**< Result XOR Value */ 86 rt_uint16_t flags; /**< Input or output data reverse. CRC_FLAG_REFIN or CRC_FLAG_REFOUT */ 87 }; 88 89 struct hwcrypto_crc_ops 90 { 91 rt_uint32_t (*update)(struct hwcrypto_crc *ctx, 92 const rt_uint8_t *in, rt_size_t length); /**< Perform a CRC calculation. return CRC value */ 93 }; 94 95 /** 96 * @brief CRC context. Hardware driver usage 97 */ 98 struct hwcrypto_crc 99 { 100 struct rt_hwcrypto_ctx parent; /**< Inherited from the standard device */ 101 struct hwcrypto_crc_cfg crc_cfg; /**< CRC configure */ 102 const struct hwcrypto_crc_ops *ops; /**< !! Hardware initializes this value when creating context !! */ 103 }; 104 105 /** 106 * @brief Creating CRC Context 107 * 108 * @param device Hardware crypto device 109 * @param mode Setting default mode or custom mode 110 * 111 * @return CRC context 112 */ 113 struct rt_hwcrypto_ctx *rt_hwcrypto_crc_create(struct rt_hwcrypto_device *device, 114 hwcrypto_crc_mode mode); 115 116 /** 117 * @brief Destroy CRC Context 118 * 119 * @param ctx CRC context 120 */ 121 void rt_hwcrypto_crc_destroy(struct rt_hwcrypto_ctx *ctx); 122 123 /** 124 * @brief Processing a packet of data 125 * 126 * @param ctx CRC context 127 * @param input Data buffer to be Processed 128 * @param length Data Buffer length 129 * 130 * @return CRC value 131 */ 132 rt_uint32_t rt_hwcrypto_crc_update(struct rt_hwcrypto_ctx *ctx, 133 const rt_uint8_t *input, rt_size_t length); 134 135 /** 136 * @brief CRC context configuration 137 * 138 * @param ctx CRC context 139 * @param cfg CRC config 140 */ 141 void rt_hwcrypto_crc_cfg(struct rt_hwcrypto_ctx *ctx, 142 struct hwcrypto_crc_cfg *cfg); 143 144 #ifdef __cplusplus 145 } 146 #endif 147 148 #endif 149