1 /**
2   ******************************************************************************
3   * @file    i2c_reg.h
4   * @version V1.0
5   * @date    2022-06-16
6   * @brief   This file is the description of.IP register
7   ******************************************************************************
8   * @attention
9   *
10   * <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
11   *
12   * Redistribution and use in source and binary forms, with or without modification,
13   * are permitted provided that the following conditions are met:
14   *   1. Redistributions of source code must retain the above copyright notice,
15   *      this list of conditions and the following disclaimer.
16   *   2. Redistributions in binary form must reproduce the above copyright notice,
17   *      this list of conditions and the following disclaimer in the documentation
18   *      and/or other materials provided with the distribution.
19   *   3. Neither the name of Bouffalo Lab nor the names of its contributors
20   *      may be used to endorse or promote products derived from this software
21   *      without specific prior written permission.
22   *
23   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
27   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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32   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33   *
34   ******************************************************************************
35   */
36 #ifndef __HARDWARE_I2C_H__
37 #define __HARDWARE_I2C_H__
38 
39 /****************************************************************************
40  * Pre-processor Definitions
41 ****************************************************************************/
42 
43 /* Register offsets *********************************************************/
44 
45 #define I2C_CONFIG_OFFSET        (0x0)  /* i2c_config */
46 #define I2C_INT_STS_OFFSET       (0x4)  /* i2c_int_sts */
47 #define I2C_SUB_ADDR_OFFSET      (0x8)  /* i2c_sub_addr */
48 #define I2C_BUS_BUSY_OFFSET      (0xC)  /* i2c_bus_busy */
49 #define I2C_PRD_START_OFFSET     (0x10) /* i2c_prd_start */
50 #define I2C_PRD_STOP_OFFSET      (0x14) /* i2c_prd_stop */
51 #define I2C_PRD_DATA_OFFSET      (0x18) /* i2c_prd_data */
52 #define I2C_FIFO_CONFIG_0_OFFSET (0x80) /* i2c_fifo_config_0 */
53 #define I2C_FIFO_CONFIG_1_OFFSET (0x84) /* i2c_fifo_config_1 */
54 #define I2C_FIFO_WDATA_OFFSET    (0x88) /* i2c_fifo_wdata */
55 #define I2C_FIFO_RDATA_OFFSET    (0x8C) /* i2c_fifo_rdata */
56 
57 /* Register Bitfield definitions *****************************************************/
58 
59 /* 0x0 : i2c_config */
60 #define I2C_CR_I2C_M_EN              (1 << 0U)
61 #define I2C_CR_I2C_PKT_DIR           (1 << 1U)
62 #define I2C_CR_I2C_DEG_EN            (1 << 2U)
63 #define I2C_CR_I2C_SCL_SYNC_EN       (1 << 3U)
64 #define I2C_CR_I2C_SUB_ADDR_EN       (1 << 4U)
65 #define I2C_CR_I2C_SUB_ADDR_BC_SHIFT (5U)
66 #define I2C_CR_I2C_SUB_ADDR_BC_MASK  (0x3 << I2C_CR_I2C_SUB_ADDR_BC_SHIFT)
67 #if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) || defined(BL702L)
68 #define I2C_CR_I2C_10B_ADDR_EN    (1 << 7U)
69 #define I2C_CR_I2C_SLV_ADDR_SHIFT (8U)
70 #define I2C_CR_I2C_SLV_ADDR_MASK  (0x3ff << I2C_CR_I2C_SLV_ADDR_SHIFT)
71 #define I2C_CR_I2C_PKT_LEN_SHIFT  (20U)
72 #define I2C_CR_I2C_PKT_LEN_MASK   (0xff << I2C_CR_I2C_PKT_LEN_SHIFT)
73 #else
74 #define I2C_CR_I2C_SLV_ADDR_SHIFT (8U)
75 #define I2C_CR_I2C_SLV_ADDR_MASK  (0x7f << I2C_CR_I2C_SLV_ADDR_SHIFT)
76 #define I2C_CR_I2C_PKT_LEN_SHIFT  (16U)
77 #define I2C_CR_I2C_PKT_LEN_MASK   (0xff << I2C_CR_I2C_PKT_LEN_SHIFT)
78 #endif
79 
80 #define I2C_CR_I2C_DEG_CNT_SHIFT (28U)
81 #define I2C_CR_I2C_DEG_CNT_MASK  (0xf << I2C_CR_I2C_DEG_CNT_SHIFT)
82 
83 /* 0x4 : i2c_int_sts */
84 #define I2C_END_INT         (1 << 0U)
85 #define I2C_TXF_INT         (1 << 1U)
86 #define I2C_RXF_INT         (1 << 2U)
87 #define I2C_NAK_INT         (1 << 3U)
88 #define I2C_ARB_INT         (1 << 4U)
89 #define I2C_FER_INT         (1 << 5U)
90 #define I2C_CR_I2C_END_MASK (1 << 8U)
91 #define I2C_CR_I2C_TXF_MASK (1 << 9U)
92 #define I2C_CR_I2C_RXF_MASK (1 << 10U)
93 #define I2C_CR_I2C_NAK_MASK (1 << 11U)
94 #define I2C_CR_I2C_ARB_MASK (1 << 12U)
95 #define I2C_CR_I2C_FER_MASK (1 << 13U)
96 #define I2C_CR_I2C_END_CLR  (1 << 16U)
97 #define I2C_CR_I2C_NAK_CLR  (1 << 19U)
98 #define I2C_CR_I2C_ARB_CLR  (1 << 20U)
99 #define I2C_CR_I2C_END_EN   (1 << 24U)
100 #define I2C_CR_I2C_TXF_EN   (1 << 25U)
101 #define I2C_CR_I2C_RXF_EN   (1 << 26U)
102 #define I2C_CR_I2C_NAK_EN   (1 << 27U)
103 #define I2C_CR_I2C_ARB_EN   (1 << 28U)
104 #define I2C_CR_I2C_FER_EN   (1 << 29U)
105 
106 /* 0x8 : i2c_sub_addr */
107 #define I2C_CR_I2C_SUB_ADDR_B0_SHIFT (0U)
108 #define I2C_CR_I2C_SUB_ADDR_B0_MASK  (0xff << I2C_CR_I2C_SUB_ADDR_B0_SHIFT)
109 #define I2C_CR_I2C_SUB_ADDR_B1_SHIFT (8U)
110 #define I2C_CR_I2C_SUB_ADDR_B1_MASK  (0xff << I2C_CR_I2C_SUB_ADDR_B1_SHIFT)
111 #define I2C_CR_I2C_SUB_ADDR_B2_SHIFT (16U)
112 #define I2C_CR_I2C_SUB_ADDR_B2_MASK  (0xff << I2C_CR_I2C_SUB_ADDR_B2_SHIFT)
113 #define I2C_CR_I2C_SUB_ADDR_B3_SHIFT (24U)
114 #define I2C_CR_I2C_SUB_ADDR_B3_MASK  (0xff << I2C_CR_I2C_SUB_ADDR_B3_SHIFT)
115 
116 /* 0xC : i2c_bus_busy */
117 #define I2C_STS_I2C_BUS_BUSY    (1 << 0U)
118 #define I2C_CR_I2C_BUS_BUSY_CLR (1 << 1U)
119 
120 /* 0x10 : i2c_prd_start */
121 #define I2C_CR_I2C_PRD_S_PH_0_SHIFT (0U)
122 #define I2C_CR_I2C_PRD_S_PH_0_MASK  (0xff << I2C_CR_I2C_PRD_S_PH_0_SHIFT)
123 #define I2C_CR_I2C_PRD_S_PH_1_SHIFT (8U)
124 #define I2C_CR_I2C_PRD_S_PH_1_MASK  (0xff << I2C_CR_I2C_PRD_S_PH_1_SHIFT)
125 #define I2C_CR_I2C_PRD_S_PH_2_SHIFT (16U)
126 #define I2C_CR_I2C_PRD_S_PH_2_MASK  (0xff << I2C_CR_I2C_PRD_S_PH_2_SHIFT)
127 #define I2C_CR_I2C_PRD_S_PH_3_SHIFT (24U)
128 #define I2C_CR_I2C_PRD_S_PH_3_MASK  (0xff << I2C_CR_I2C_PRD_S_PH_3_SHIFT)
129 
130 /* 0x14 : i2c_prd_stop */
131 #define I2C_CR_I2C_PRD_P_PH_0_SHIFT (0U)
132 #define I2C_CR_I2C_PRD_P_PH_0_MASK  (0xff << I2C_CR_I2C_PRD_P_PH_0_SHIFT)
133 #define I2C_CR_I2C_PRD_P_PH_1_SHIFT (8U)
134 #define I2C_CR_I2C_PRD_P_PH_1_MASK  (0xff << I2C_CR_I2C_PRD_P_PH_1_SHIFT)
135 #define I2C_CR_I2C_PRD_P_PH_2_SHIFT (16U)
136 #define I2C_CR_I2C_PRD_P_PH_2_MASK  (0xff << I2C_CR_I2C_PRD_P_PH_2_SHIFT)
137 #define I2C_CR_I2C_PRD_P_PH_3_SHIFT (24U)
138 #define I2C_CR_I2C_PRD_P_PH_3_MASK  (0xff << I2C_CR_I2C_PRD_P_PH_3_SHIFT)
139 
140 /* 0x18 : i2c_prd_data */
141 #define I2C_CR_I2C_PRD_D_PH_0_SHIFT (0U)
142 #define I2C_CR_I2C_PRD_D_PH_0_MASK  (0xff << I2C_CR_I2C_PRD_D_PH_0_SHIFT)
143 #define I2C_CR_I2C_PRD_D_PH_1_SHIFT (8U)
144 #define I2C_CR_I2C_PRD_D_PH_1_MASK  (0xff << I2C_CR_I2C_PRD_D_PH_1_SHIFT)
145 #define I2C_CR_I2C_PRD_D_PH_2_SHIFT (16U)
146 #define I2C_CR_I2C_PRD_D_PH_2_MASK  (0xff << I2C_CR_I2C_PRD_D_PH_2_SHIFT)
147 #define I2C_CR_I2C_PRD_D_PH_3_SHIFT (24U)
148 #define I2C_CR_I2C_PRD_D_PH_3_MASK  (0xff << I2C_CR_I2C_PRD_D_PH_3_SHIFT)
149 
150 /* 0x80 : i2c_fifo_config_0 */
151 #define I2C_DMA_TX_EN         (1 << 0U)
152 #define I2C_DMA_RX_EN         (1 << 1U)
153 #define I2C_TX_FIFO_CLR       (1 << 2U)
154 #define I2C_RX_FIFO_CLR       (1 << 3U)
155 #define I2C_TX_FIFO_OVERFLOW  (1 << 4U)
156 #define I2C_TX_FIFO_UNDERFLOW (1 << 5U)
157 #define I2C_RX_FIFO_OVERFLOW  (1 << 6U)
158 #define I2C_RX_FIFO_UNDERFLOW (1 << 7U)
159 
160 /* 0x84 : i2c_fifo_config_1 */
161 #define I2C_TX_FIFO_CNT_SHIFT (0U)
162 #define I2C_TX_FIFO_CNT_MASK  (0x3 << I2C_TX_FIFO_CNT_SHIFT)
163 #define I2C_RX_FIFO_CNT_SHIFT (8U)
164 #define I2C_RX_FIFO_CNT_MASK  (0x3 << I2C_RX_FIFO_CNT_SHIFT)
165 #define I2C_TX_FIFO_TH        (1 << 16U)
166 #define I2C_RX_FIFO_TH        (1 << 24U)
167 
168 /* 0x88 : i2c_fifo_wdata */
169 #define I2C_FIFO_WDATA_SHIFT (0U)
170 #define I2C_FIFO_WDATA_MASK  (0xffffffff << I2C_FIFO_WDATA_SHIFT)
171 
172 /* 0x8C : i2c_fifo_rdata */
173 #define I2C_FIFO_RDATA_SHIFT (0U)
174 #define I2C_FIFO_RDATA_MASK  (0xffffffff << I2C_FIFO_RDATA_SHIFT)
175 
176 #endif /* __HARDWARE_I2C_H__ */
177