1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2018-03-22 quanzhao first version
9 */
10
11 #ifndef __IMX6UL_H__
12 #define __IMX6UL_H__
13
14 #include <rthw.h>
15 #include <rtthread.h>
16
17 #ifdef RT_USING_LWP
18 #include <lwp.h>
19 #include <ioremap.h>
20 #endif
21
22 enum _gic_base_offsets
23 {
24 kGICDBaseOffset = 0x1000, //!< GIC distributor offset.
25 kGICCBaseOffset = 0x2000 //!< GIC CPU interface offset.
26 };
27
28 /* SOC-relative definitions */
29 enum _imx_interrupts
30 {
31 SW_INTERRUPT_0 = 0, //!< Software interrupt 0.
32 SW_INTERRUPT_1 = 1, //!< Software interrupt 1.
33 SW_INTERRUPT_2 = 2, //!< Software interrupt 2.
34 SW_INTERRUPT_3 = 3, //!< Software interrupt 3.
35 SW_INTERRUPT_4 = 4, //!< Software interrupt 4.
36 SW_INTERRUPT_5 = 5, //!< Software interrupt 5.
37 SW_INTERRUPT_6 = 6, //!< Software interrupt 6.
38 SW_INTERRUPT_7 = 7, //!< Software interrupt 7.
39 SW_INTERRUPT_8 = 8, //!< Software interrupt 8.
40 SW_INTERRUPT_9 = 9, //!< Software interrupt 9.
41 SW_INTERRUPT_10 = 10, //!< Software interrupt 10.
42 SW_INTERRUPT_11 = 11, //!< Software interrupt 11.
43 SW_INTERRUPT_12 = 12, //!< Software interrupt 12.
44 SW_INTERRUPT_13 = 13, //!< Software interrupt 13.
45 SW_INTERRUPT_14 = 14, //!< Software interrupt 14.
46 SW_INTERRUPT_15 = 15, //!< Software interrupt 15.
47 RSVD_INTERRUPT_16 = 16, //!< Reserved.
48 RSVD_INTERRUPT_17 = 17, //!< Reserved.
49 RSVD_INTERRUPT_18 = 18, //!< Reserved.
50 RSVD_INTERRUPT_19 = 19, //!< Reserved.
51 RSVD_INTERRUPT_20 = 20, //!< Reserved.
52 RSVD_INTERRUPT_21 = 21, //!< Reserved.
53 RSVD_INTERRUPT_22 = 22, //!< Reserved.
54 RSVD_INTERRUPT_23 = 23, //!< Reserved.
55 RSVD_INTERRUPT_24 = 24, //!< Reserved.
56 RSVD_INTERRUPT_25 = 25, //!< Reserved.
57 RSVD_INTERRUPT_26 = 26, //!< Reserved.
58 RSVD_INTERRUPT_27 = 27, //!< Reserved.
59 RSVD_INTERRUPT_28 = 28, //!< Reserved.
60 RSVD_INTERRUPT_29 = 29, //!< Reserved.
61 RSVD_INTERRUPT_30 = 30, //!< Reserved.
62 RSVD_INTERRUPT_31 = 31, //!< Reserved.
63 IMX_INT_IOMUXC_GPR = 32, //!< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot.
64 IMX_INT_CHEETAH_CSYSPWRUPREQ = 33, //!< @todo Listed as DAP in RM
65 IMX_INT_SDMA = 34, //!< Logical OR of all 48 SDMA interrupt requests/events from all channels.
66 IMX_INT_TSC = 35, //!< TSC
67 IMX_INT_SNVS_LP_SET_PWR_OFF = 36, //!< PMIC power off request.
68 IMX_INT_LCDIF = 37, //!< LCDIF interrupt request.
69 IMX_INT_BEE = 38, //!< BEE interrupt request.
70 IMX_INT_CSI = 39, //!< CMOS Sensor Interface interrupt request.
71 IMX_INT_PXP = 40, //!< PXP interrupt request.
72 IMX_INT_SCTR1 = 41, //!< SCTR1
73 IMX_INT_SCTR2 = 42, //!< SCTR2
74 IMX_INT_WDOG3 = 43, //!< WDOG3 timer reset interrupt request.
75 IMX_INT_INTERRUPT_44 = 44, //!< Reserved.
76 IMX_INT_APBH_DMA = 45, //!< APBH DMA
77 IMX_INT_EIM = 46, //!< EIM interrupt request.
78 IMX_INT_NAND_BCH = 47, //!< Reserved.
79 IMX_INT_NAND_GPMI = 48, //!< Reserved.
80 IMX_INT_UART6 = 49, //!< Logical OR of UART5 interrupt requests.
81 IMX_INT_INTERRUPT_50 = 50, //!< Reserved.
82 IMX_INT_SNVS = 51, //!< SNVS consolidated interrupt.
83 IMX_INT_SNVS_SEC = 52, //!< SNVS security interrupt.
84 IMX_INT_CSU = 53, //!< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted.
85 IMX_INT_USDHC1 = 54, //!< uSDHC1 (Enhanced SDHC) interrupt request.
86 IMX_INT_USDHC2 = 55, //!< uSDHC2 (Enhanced SDHC) interrupt request.
87 IMX_INT_SAI3 = 56, //!< uSDHC3 (Enhanced SDHC) interrupt request.
88 IMX_INT_SAI4 = 57, //!< uSDHC4 (Enhanced SDHC) interrupt request.
89 IMX_INT_UART1 = 58, //!< Logical OR of UART1 interrupt requests.
90 IMX_INT_UART2 = 59, //!< Logical OR of UART2 interrupt requests.
91 IMX_INT_UART3 = 60, //!< Logical OR of UART3 interrupt requests.
92 IMX_INT_UART4 = 61, //!< Logical OR of UART4 interrupt requests.
93 IMX_INT_UART5 = 62, //!< Logical OR of UART5 interrupt requests.
94 IMX_INT_ECSPI1 = 63, //!< eCSPI1 interrupt request.
95 IMX_INT_ECSPI2 = 64, //!< eCSPI2 interrupt request.
96 IMX_INT_ECSPI3 = 65, //!< eCSPI3 interrupt request.
97 IMX_INT_ECSPI4 = 66, //!< eCSPI4 interrupt request.
98 IMX_INT_I2C4 = 67, //!< Reserved.
99 IMX_INT_I2C1 = 68, //!< I2C1 interrupt request.
100 IMX_INT_I2C2 = 69, //!< I2C2 interrupt request.
101 IMX_INT_I2C3 = 70, //!< I2C3 interrupt request.
102 IMX_INT_UART7 = 71, //!< Logical OR of UART5 interrupt requests.
103 IMX_INT_UART8 = 72, //!< Logical OR of UART5 interrupt requests.
104 IMX_INT_INTERRUPT_73 = 73, //!< Reserved.
105 IMX_INT_USB_OTG2 = 74, //!< USB Host 1 interrupt request.
106 IMX_INT_USB_OTG1 = 75, //!< USB OTG1 interrupt request.
107 IMX_INT_USB_UTMI0 = 76, //!< UTMI0 interrupt request.
108 IMX_INT_USB_UTMI1 = 77, //!< UTMI1 interrupt request.
109 IMX_INT_CAAM_JQ2 = 78, //!< SSI1 interrupt request.
110 IMX_INT_CAAM_ERR = 79, //!< SSI2 interrupt request.
111 IMX_INT_CAAM_RTIC = 80, //!< SSI3 interrupt request.
112 IMX_INT_TEMPERATURE = 81, //!< Temperature Sensor (temp. greater than threshold) interrupt request.
113 IMX_INT_ASRC = 82, //!< Reserved.
114 IMX_INT_INTERRUPT_83 = 83, //!< Reserved.
115 IMX_INT_SPDIF = 84, //!< Logical OR of SPDIF TX and SPDIF RX interrupts.
116 IMX_INT_INTERRUPT_85 = 85, //!< Reserved.
117 IMX_INT_PMU_ANA_BO = 86, //!< PMU analog regulator brown-out interrupt request.
118 IMX_INT_GPT1 = 87, //
119 IMX_INT_EPIT1 = 88, //!< EPIT1 output compare interrupt.
120 IMX_INT_EPIT2 = 89, //!< EPIT2 output compare interrupt.
121 IMX_INT_GPIO1_INT7 = 90, //!< INT7 interrupt request.
122 IMX_INT_GPIO1_INT6 = 91, //!< INT6 interrupt request.
123 IMX_INT_GPIO1_INT5 = 92, //!< INT5 interrupt request.
124 IMX_INT_GPIO1_INT4 = 93, //!< INT4 interrupt request.
125 IMX_INT_GPIO1_INT3 = 94, //!< INT3 interrupt request.
126 IMX_INT_GPIO1_INT2 = 95, //!< INT2 interrupt request.
127 IMX_INT_GPIO1_INT1 = 96, //!< INT1 interrupt request.
128 IMX_INT_GPIO1_INT0 = 97, //!< INT0 interrupt request.
129 IMX_INT_GPIO1_INT15_0 = 98, //!< Combined interrupt indication for GPIO1 signals 0 - 15.
130 IMX_INT_GPIO1_INT31_16 = 99, //!< Combined interrupt indication for GPIO1 signals 16 - 31.
131 IMX_INT_GPIO2_INT15_0 = 100, //!< Combined interrupt indication for GPIO2 signals 0 - 15.
132 IMX_INT_GPIO2_INT31_16 = 101, //!< Combined interrupt indication for GPIO2 signals 16 - 31.
133 IMX_INT_GPIO3_INT15_0 = 102, //!< Combined interrupt indication for GPIO3 signals 0 - 15.
134 IMX_INT_GPIO3_INT31_16 = 103, //!< Combined interrupt indication for GPIO3 signals 16 - 31.
135 IMX_INT_GPIO4_INT15_0 = 104, //!< Combined interrupt indication for GPIO4 signals 0 - 15.
136 IMX_INT_GPIO4_INT31_16 = 105, //!< Combined interrupt indication for GPIO4 signals 16 - 31.
137 IMX_INT_GPIO5_INT15_0 = 106, //!< Combined interrupt indication for GPIO5 signals 0 - 15.
138 IMX_INT_GPIO5_INT31_16 = 107, //!< Combined interrupt indication for GPIO5 signals 16 - 31.
139 IMX_INT_INTERRUPT_108 = 108, //!< Reserved.
140 IMX_INT_INTERRUPT_109 = 109, //!< Reserved.
141 IMX_INT_INTERRUPT_110 = 110, //!< Reserved.
142 IMX_INT_INTERRUPT_111 = 111, //!< Reserved.
143 IMX_INT_WDOG1 = 112, //!< WDOG1 timer reset interrupt request.
144 IMX_INT_WDOG2 = 113, //!< WDOG2 timer reset interrupt request.
145 IMX_INT_KPP = 114, //!< Key Pad interrupt request.
146 IMX_INT_PWM1 = 115, //!< Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
147 IMX_INT_PWM2 = 116, //!< Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
148 IMX_INT_PWM3 = 117, //!< Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
149 IMX_INT_PWM4 = 118, //!< Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.
150 IMX_INT_CCM_INT1 = 119, //!< CCM interrupt request 1.
151 IMX_INT_CCM_INT2 = 120, //!< CCM interrupt request 2.
152 IMX_INT_GPC_INT1 = 121, //!< GPC interrupt request 1.
153 IMX_INT_INTERRUPT_122 = 122, //!< Reserved.
154 IMX_INT_SRC = 123, //!< SRC interrupt request.
155 IMX_INT_INTERRUPT_124 = 124, //!< Logical OR of all L2 interrupt requests.
156 IMX_INT_INTERRUPT_125 = 125, //!< Parity Check error interrupt request.
157 IMX_INT_CHEETAH_PERFORM = 126, //!< Logical OR of Performance Unit interrupts.
158 IMX_INT_CHEETAH_TRIGGER = 127, //!< Logical OR of CTI trigger outputs.
159 IMX_INT_SRC_CPU_WDOG = 128, //!< Combined CPU wdog interrupts (4x) out of SRC.
160 IMX_INT_SAI1 = 129, //!< EPDC interrupt request.
161 IMX_INT_SAI2 = 130, //!< EPDC interrupt request.
162 IMX_INT_INTERRUPT_131 = 131, //!< DCP general interrupt request.
163 IMX_INT_ADC1 = 132, //!< DCP channel 0 interrupt request.
164 IMX_INT_ADC2 = 133, //!< DCP secure interrupt request.
165 IMX_INT_INTERRUPT_134 = 134, //!< Reserved.
166 IMX_INT_INTERRUPT_135 = 135, //!< Reserved.
167 IMX_INT_SJC = 136, //!< SJC interrupt from General Purpose register.
168 IMX_INT_CAAM_0 = 137, //!< Reserved.
169 IMX_INT_CAAM_1 = 138, //!< Reserved.
170 IMX_INT_QSPI = 139, //!< Reserved.
171 IMX_INT_TZASC1 = 140, //!< ASC1 interrupt request.
172 IMX_INT_GPT2 = 141, //!< Reserved.
173 IMX_INT_CAN1 = 142, //!< Reserved.
174 IMX_INT_CAN2 = 143, //!< Reserved.
175 IMX_INT_SIM1 = 144, //!< Reserved.
176 IMX_INT_SIM2 = 145, //!< Reserved.
177 IMX_INT_PWM5 = 146, //!< Fast Ethernet Controller interrupt request.
178 IMX_INT_PWM6 = 147, //!< Reserved.
179 IMX_INT_PWM7 = 148, //!< Reserved.
180 IMX_INT_PWM8 = 149, //!< Reserved.
181 IMX_INT_ENET1 = 150, //!< Reserved.
182 IMX_INT_ENET1_TIMER = 151, //!< Reserved.
183 IMX_INT_ENET2 = 152, //!< Reserved.
184 IMX_INT_ENET2_TIMER = 153, //!< Reserved.
185 IMX_INT_INTERRUPT_154 = 154, //!< Reserved.
186 IMX_INT_INTERRUPT_155 = 155, //!< Reserved.
187 IMX_INT_INTERRUPT_156 = 156, //!< Reserved.
188 IMX_INT_INTERRUPT_157 = 157, //!< Reserved.
189 IMX_INT_INTERRUPT_158 = 158, //!< Reserved.
190 IMX_INT_PMU_DIG_BO = 159, //!< //!< PMU digital regulator brown-out interrupt request.
191 IMX_INTERRUPT_COUNT = 160 //!< Total number of interrupts.
192 };
193
194 /* SOC-relative definitions */
195 #include "MCIMX6Y2.h"
196
197 #include "fsl_cache.h"
198 #include "fsl_common.h"
199 #include "fsl_iomuxc.h"
200 #include "fsl_gpio.h"
201 #include "fsl_elcdif.h"
202 #include "fsl_usdhc.h"
203 #include "fsl_card.h"
204 #include "fsl_wdog.h"
205 #include "fsl_i2c.h"
206 #include "fsl_ecspi.h"
207 #include "fsl_snvs_hp.h"
208 #include "fsl_adc.h"
209
210 #define IMX6ULL_PERIPH_SIZE (16 * 1024)
211
212 /* Interrupt Control Interface */
213 #define ARM_GIC_CPU_BASE 0x00A00000
214
215 /*
216 * Peripheral addresses
217 */
218 #define IMX6ULL_UART1_BASE UART1_BASE /* UART 1 */
219 #define IMX6ULL_UART2_BASE UART2_BASE /* UART 2 */
220 #define IMX6ULL_UART3_BASE UART3_BASE /* UART 3 */
221 #define IMX6ULL_UART4_BASE UART4_BASE /* UART 4 */
222 #define IMX6ULL_UART5_BASE UART5_BASE /* UART 5 */
223 #define IMX6ULL_UART6_BASE UART6_BASE /* UART 6 */
224 #define IMX6ULL_UART7_BASE UART7_BASE /* UART 7 */
225 #define IMX6ULL_UART8_BASE UART8_BASE /* UART 8 */
226
227 #define IMX6ULL_WATCHDOG1_BASE WDOG1_BASE /* watchdog 1 */
228 #define IMX6ULL_WATCHDOG2_BASE WDOG2_BASE /* watchdog 2 */
229 #define IMX6ULL_WATCHDOG3_BASE WDOG3_BASE /* watchdog 3 */
230
231 #define IMX6ULL_GPIO1_BASE GPIO1_BASE /* GPIO port 0 */
232 #define IMX6ULL_GPIO2_BASE GPIO2_BASE /* GPIO port 1 */
233 #define IMX6ULL_GPIO3_BASE GPIO3_BASE /* GPIO port 2 */
234 #define IMX6ULL_GPIO4_BASE GPIO4_BASE /* GPIO port 3 */
235 #define IMX6ULL_GPIO5_BASE GPIO5_BASE /* GPIO port 4 */
236
237 #define IMX6ULL_SNVS_BASE SNVS_BASE /* Real Time Clock */
238
239 #define IMX6ULL_SCTL_BASE 0x021DC000u /* System Controller */
240
241 #define IMX6ULL_CLCD_BASE LCDIF_BASE /* CLCD */
242
243 #define IMX6ULL_GIC_DIST_BASE (ARM_GIC_CPU_BASE+kGICDBaseOffset) /* Generic interrupt controller distributor */
244 #define IMX6ULL_GIC_CPU_BASE (ARM_GIC_CPU_BASE+kGICCBaseOffset) /* Generic interrupt controller CPU interface */
245
246 #define IMX6ULL_IOMUXC_BASE IOMUXC_BASE
247 #define IMX6ULL_IOMUXC_SNVS_BASE IOMUXC_SNVS_BASE
248 #define IMX6ULL_IOMUXC_GPR_BASE IOMUXC_GPR_BASE
249
250 #define IMX6ULL_CCM_BASE 0x20C4000u
251 #define IMX6ULL_CCM_ANALOGY_BASE 0x20C8000u
252 #define IMX6ULL_PMU_BASE 0x20C8110u
253
254 #define IMX6ULL_ENET1_BASE ENET1_BASE
255 #define IMX6ULL_ENET2_BASE ENET2_BASE
256
257 #define IMX6ULL_GPT1_BASE GPT1_BASE
258 #define IMX6ULL_GPT2_BASE GPT2_BASE
259
260 #define IMX6ULL_ECSPI1_BASE ECSPI1_BASE
261 #define IMX6ULL_ECSPI2_BASE ECSPI2_BASE
262 #define IMX6ULL_ECSPI3_BASE ECSPI3_BASE
263 #define IMX6ULL_ECSPI4_BASE ECSPI4_BASE
264
265 #define IMX6ULL_I2C1_BASE I2C1_BASE
266 #define IMX6ULL_I2C2_BASE I2C2_BASE
267 #define IMX6ULL_I2C3_BASE I2C3_BASE
268 #define IMX6ULL_I2C4_BASE I2C4_BASE
269
270 #define IMX6ULL_SDMA_BASE SDMAARM_BASE
271
272 #define IMX6ULL_USDHC1_BASE USDHC1_BASE
273 #define IMX6ULL_USDHC2_BASE USDHC2_BASE
274
275 #define IMX6ULL_SRC_BASE SRC_BASE
276
277 #define IMX6ULL_GPMI_BASE GPMI_BASE
278 #define IMX6ULL_BCH_BASE BCH_BASE
279 #define IMX6ULL_APBH_BASE APBH_BASE
280
281 #define IMX6ULL_CSI_BASE CSI_BASE
282
283 #define IMX6ULL_CAN1_BASE CAN1_BASE
284 #define IMX6ULL_CAN2_BASE CAN2_BASE
285
286 #define IMX6ULL_USBPHY1_BASE 0x20C9000u
287 #define IMX6ULL_USBPHY2_BASE 0x20CA000u
288
289 #define IMX6ULL_USB1_BASE 0x2184000u
290 #define IMX6ULL_USB2_BASE 0x2184200u
291
292 #define IMX6ULL_USB_ANALOG_BASE 0x20C81A0u
293 /* the maximum number of gic */
294 #define ARM_GIC_MAX_NR 1
295
296 #define _internal_ro static const
297 #define _internal_rw static
298 #define _internal_zi static
299
300 #define GET_ARRAY_NUM(ins) ((uint32_t)(sizeof(ins)/sizeof(ins[0])))
301
302 #include "bsp_clock.h"
303
304 /* the maximum number of interrupts */
305 #define ARM_GIC_NR_IRQS IMX_INTERRUPT_COUNT
306
307 /* the maximum entries of the interrupt table */
308 #define MAX_HANDLERS IMX_INTERRUPT_COUNT
309
310 /* the basic constants needed by gic */
platform_get_gic_dist_base(void)311 rt_inline rt_uint32_t platform_get_gic_dist_base(void)
312 {
313 rt_uint32_t gic_base;
314 asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base));
315 return gic_base + kGICDBaseOffset;
316 }
317
platform_get_gic_cpu_base(void)318 rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
319 {
320 rt_uint32_t gic_base;
321 asm volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r"(gic_base));
322 return gic_base + kGICCBaseOffset;
323 }
324
platform_get_periph_vaddr(rt_uint32_t paddr)325 rt_inline rt_uint32_t platform_get_periph_vaddr(rt_uint32_t paddr)
326 {
327 #ifdef RT_USING_SMART
328 rt_uint32_t mask = IMX6ULL_PERIPH_SIZE - 1;
329 return (rt_uint32_t)rt_ioremap((void*)(paddr&(~mask)), IMX6ULL_PERIPH_SIZE) + (paddr & mask);
330 #else
331 return paddr;
332 #endif
333 }
334
335 #define GIC_IRQ_START 0
336
337 #define GIC_ACK_INTID_MASK 0x000003ff
338
339 /* the definition needed by gic.c */
340 #define __REG32(x) (*((volatile unsigned int *)(x)))
341
342 /* keep compatible with platform SDK */
343 typedef enum {
344 CPU_0,
345 CPU_1,
346 CPU_2,
347 CPU_3,
348 } cpuid_e;
349
350 enum _gicd_sgi_filter
351 {
352 //! Forward the interrupt to the CPU interfaces specified in the @a target_list parameter.
353 kGicSgiFilter_UseTargetList = 0,
354
355 //! Forward the interrupt to all CPU interfaces except that of the processor that requested
356 //! the interrupt.
357 kGicSgiFilter_AllOtherCPUs = 1,
358
359 //! Forward the interrupt only to the CPU interface of the processor that requested the
360 //! interrupt.
361 kGicSgiFilter_OnlyThisCPU = 2
362 };
363
364 typedef void (*irq_hdlr_t) (void);
365
366 extern void rt_hw_interrupt_mask(int vector);
367 extern void rt_hw_interrupt_umask(int vector);
368 extern rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
369 void *param, const char *name);
370
register_interrupt_routine(uint32_t irq_id,irq_hdlr_t isr)371 rt_inline void register_interrupt_routine(uint32_t irq_id, irq_hdlr_t isr)
372 {
373 rt_hw_interrupt_install(irq_id, (rt_isr_handler_t)isr, RT_NULL, "unknown");
374 }
375
enable_interrupt(uint32_t irq_id,uint32_t cpu_id,uint32_t priority)376 rt_inline void enable_interrupt(uint32_t irq_id, uint32_t cpu_id, uint32_t priority)
377 {
378 rt_hw_interrupt_umask(irq_id);
379 }
380
disable_interrupt(uint32_t irq_id,uint32_t cpu_id)381 rt_inline void disable_interrupt(uint32_t irq_id, uint32_t cpu_id)
382 {
383 rt_hw_interrupt_mask(irq_id);
384 }
385
386 #endif /* __IMX6UL_H__ */
387