1 /*
2 *********************************************************************************************************
3 *                                                AR100 SYSTEM
4 *                                     AR100 Software System Develop Kits
5 *                                              interrupt  module
6 *
7 *                                    (c) Copyright 2012-2016, Sunny China
8 *                                             All Rights Reserved
9 *
10 * File    : intc_i.h
11 * By      : Sunny
12 * Version : v1.0
13 * Date    : 2012-5-3
14 * Descript: interrupt controller internal header.
15 * Update  : date                auther      ver     notes
16 *           2012-5-3 13:27:40   Sunny       1.0     Create this file.
17 *********************************************************************************************************
18 */
19 
20 #ifndef __INTC_I_H__
21 #define __INTC_I_H__
22 
23 #include <hal_interrupt.h>
24 #include <sunxi_hal_common.h>
25 
26 /*interrput controller registers Offset*/
27 typedef struct intc_regs {
28     /*offset 0x00 */
29     volatile u32 vector;
30     volatile u32 base_addr;
31     volatile u32 reserved0;
32     volatile u32 control;
33 
34     /*offset 0x10 */
35     volatile u32 pending;
36     volatile u32 pending1;
37     volatile u32 pending2;
38     volatile u32 reserved1[9];
39 
40     /*offset 0x40 */
41     volatile u32 enable;
42     volatile u32 enable1;
43     volatile u32 enable2;
44     volatile u32 reserved2[1];
45 
46     /*offset 0x50 */
47     volatile u32 mask;
48     volatile u32 mask1;
49     volatile u32 mask2;
50     volatile u32 reserved3[5];
51 
52     /*offset 0x70 */
53     volatile u32 fast_forcing;
54     volatile u32 reserved4[3];
55 
56     /*offset 0x80 */
57     volatile u32 priority0;
58     volatile u32 priority1;
59     volatile u32 reserved5[14];
60 
61     /*offset 0xc0 */
62     volatile u32 group_config0;
63     volatile u32 group_config1;
64     volatile u32 group_config2;
65     volatile u32 group_config3;
66 } intc_regs_t;
67 
68 struct int_isr_node {
69     __pISR_hdle_t pisr;     /*ISR process handler */
70     void *parg;     /*argument for isr process */
71 };
72 
73 /*local functions*/
74 s32 intc_init(void);
75 s32 intc_exit(void);
76 s32 intc_set_fiq_triggermode(u32 triggermode);
77 s32 intc_enable_interrupt(u32 intno);
78 s32 intc_disable_interrupt(u32 intno);
79 u32 intc_get_current_interrupt(void);
80 s32 intc_set_mask(u32 intno, u32 mask);
81 s32 intc_set_group_config(u32 grp_irq_num, u32 mask);
82 
83 s32 isr_default(int dummy, void *arg);
84 
85 /*pointer of register list*/
86 extern struct intc_regs *pintc_regs;
87 
88 #endif /*__INTC_I_H__*/
89