1 /** 2 ****************************************************************************** 3 * @file ir_reg.h 4 * @version V1.0 5 * @date 2022-09-28 6 * @brief This file is the description of.IP register 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2> 11 * 12 * Redistribution and use in source and binary forms, with or without modification, 13 * are permitted provided that the following conditions are met: 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation 18 * and/or other materials provided with the distribution. 19 * 3. Neither the name of Bouffalo Lab nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 ****************************************************************************** 35 */ 36 #ifndef __HARDWARE_IR_H__ 37 #define __HARDWARE_IR_H__ 38 39 /**************************************************************************** 40 * Pre-processor Definitions 41 ****************************************************************************/ 42 43 /* Register offsets *********************************************************/ 44 45 #if !defined(BL616) 46 #define IRTX_CONFIG_OFFSET (0x0) /* irtx_config */ 47 #define IRTX_INT_STS_OFFSET (0x4) /* irtx_int_sts */ 48 #if defined(BL602) || defined(BL702) 49 #define IRTX_DATA_WORD0_OFFSET (0x8) /* irtx_data_word0 */ 50 #define IRTX_DATA_WORD1_OFFSET (0xC) /* irtx_data_word1 */ 51 #endif 52 #define IRTX_PULSE_WIDTH_OFFSET (0x10) /* irtx_pulse_width */ 53 #if defined(BL602) || defined(BL702) 54 #define IRTX_PW_OFFSET (0x14) /* irtx_pw */ 55 #define IRTX_SWM_PW_0_OFFSET (0x40) /* irtx_swm_pw_0 */ 56 #define IRTX_SWM_PW_1_OFFSET (0x44) /* irtx_swm_pw_1 */ 57 #define IRTX_SWM_PW_2_OFFSET (0x48) /* irtx_swm_pw_2 */ 58 #define IRTX_SWM_PW_3_OFFSET (0x4C) /* irtx_swm_pw_3 */ 59 #define IRTX_SWM_PW_4_OFFSET (0x50) /* irtx_swm_pw_4 */ 60 #define IRTX_SWM_PW_5_OFFSET (0x54) /* irtx_swm_pw_5 */ 61 #define IRTX_SWM_PW_6_OFFSET (0x58) /* irtx_swm_pw_6 */ 62 #define IRTX_SWM_PW_7_OFFSET (0x5C) /* irtx_swm_pw_7 */ 63 #else 64 #define IRTX_PW_0_OFFSET (0x14) /* irtx_pw_0 */ 65 #define IRTX_PW_1_OFFSET (0x18) /* irtx_pw_1 */ 66 #endif 67 #endif 68 #if !defined(BL702L) 69 #if defined(BL602) || defined(BL702) 70 #define IRRX_CONFIG_OFFSET (0x80) /* irrx_config */ 71 #define IRRX_INT_STS_OFFSET (0x84) /* irrx_int_sts */ 72 #define IRRX_PW_CONFIG_OFFSET (0x88) /* irrx_pw_config */ 73 #define IRRX_DATA_COUNT_OFFSET (0x90) /* irrx_data_count */ 74 #define IRRX_DATA_WORD0_OFFSET (0x94) /* irrx_data_word0 */ 75 #define IRRX_DATA_WORD1_OFFSET (0x98) /* irrx_data_word1 */ 76 #else 77 #define IRRX_CONFIG_OFFSET (0x40) /* irrx_config */ 78 #define IRRX_INT_STS_OFFSET (0x44) /* irrx_int_sts */ 79 #define IRRX_PW_CONFIG_OFFSET (0x48) /* irrx_pw_config */ 80 #define IRRX_DATA_COUNT_OFFSET (0x50) /* irrx_data_count */ 81 #define IRRX_DATA_WORD0_OFFSET (0x54) /* irrx_data_word0 */ 82 #define IRRX_DATA_WORD1_OFFSET (0x58) /* irrx_data_word1 */ 83 #endif 84 #endif 85 #if defined(BL602) || defined(BL702) 86 #define IRRX_SWM_FIFO_CONFIG_0_OFFSET (0xC0) /* irrx_swm_fifo_config_0 */ 87 #define IRRX_SWM_FIFO_RDATA_OFFSET (0xC4) /* irrx_swm_fifo_rdata */ 88 #else 89 #define IR_FIFO_CONFIG_0_OFFSET (0x80) /* ir_fifo_config_0 */ 90 #define IR_FIFO_CONFIG_1_OFFSET (0x84) /* ir_fifo_config_1 */ 91 #define IR_FIFO_WDATA_OFFSET (0x88) /* ir_fifo_wdata */ 92 #if !defined(BL702L) 93 #define IR_FIFO_RDATA_OFFSET (0x8C) /* ir_fifo_rdata */ 94 #endif 95 #endif 96 97 /* Register Bitfield definitions *****************************************************/ 98 99 #if !defined(BL616) 100 /* 0x0 : irtx_config */ 101 #define IR_CR_IRTX_EN (1 << 0U) 102 #define IR_CR_IRTX_OUT_INV (1 << 1U) 103 #define IR_CR_IRTX_MOD_EN (1 << 2U) 104 #define IR_CR_IRTX_SWM_EN (1 << 3U) 105 #define IR_CR_IRTX_DATA_EN (1 << 4U) 106 #define IR_CR_IRTX_LOGIC0_HL_INV (1 << 5U) 107 #define IR_CR_IRTX_LOGIC1_HL_INV (1 << 6U) 108 #define IR_CR_IRTX_HEAD_EN (1 << 8U) 109 #define IR_CR_IRTX_HEAD_HL_INV (1 << 9U) 110 #define IR_CR_IRTX_TAIL_EN (1 << 10U) 111 #define IR_CR_IRTX_TAIL_HL_INV (1 << 11U) 112 #if defined(BL602) || defined(BL702) 113 #define IR_CR_IRTX_DATA_NUM_SHIFT (12U) 114 #define IR_CR_IRTX_DATA_NUM_MASK (0x3f << IR_CR_IRTX_DATA_NUM_SHIFT) 115 #else 116 #define IR_CR_IRTX_FRM_EN (1 << 12U) 117 #define IR_CR_IRTX_FRM_CONT_EN (1 << 13U) 118 #define IR_CR_IRTX_FRM_FRAME_SIZE_SHIFT (14U) 119 #define IR_CR_IRTX_FRM_FRAME_SIZE_MASK (0x3 << IR_CR_IRTX_FRM_FRAME_SIZE_SHIFT) 120 #define IR_CR_IRTX_DATA_NUM_SHIFT (16U) 121 #define IR_CR_IRTX_DATA_NUM_MASK (0x7f << IR_CR_IRTX_DATA_NUM_SHIFT) 122 #endif 123 124 /* 0x4 : irtx_int_sts */ 125 #define IRTX_END_INT (1 << 0U) 126 #if !defined(BL602) && !defined(BL702) 127 #define IRTX_FRDY_INT (1 << 1U) 128 #define IRTX_FER_INT (1 << 2U) 129 #endif 130 #define IR_CR_IRTX_END_MASK (1 << 8U) 131 #if !defined(BL602) && !defined(BL702) 132 #define IR_CR_IRTX_FRDY_MASK (1 << 9U) 133 #define IR_CR_IRTX_FER_MASK (1 << 10U) 134 #endif 135 #define IR_CR_IRTX_END_CLR (1 << 16U) 136 #define IR_CR_IRTX_END_EN (1 << 24U) 137 #if !defined(BL602) && !defined(BL702) 138 #define IR_CR_IRTX_FRDY_EN (1 << 25U) 139 #define IR_CR_IRTX_FER_EN (1 << 26U) 140 #else 141 /* 0x8 : irtx_data_word0 */ 142 #define IR_CR_IRTX_DATA_WORD0_SHIFT (0U) 143 #define IR_CR_IRTX_DATA_WORD0_MASK (0xffffffff<<IR_CR_IRTX_DATA_WORD0_SHIFT) 144 145 /* 0xC : irtx_data_word1 */ 146 #define IR_CR_IRTX_DATA_WORD1_SHIFT (0U) 147 #define IR_CR_IRTX_DATA_WORD1_MASK (0xffffffff<<IR_CR_IRTX_DATA_WORD1_SHIFT) 148 #endif 149 150 /* 0x10 : irtx_pulse_width */ 151 #define IR_CR_IRTX_PW_UNIT_SHIFT (0U) 152 #define IR_CR_IRTX_PW_UNIT_MASK (0xfff << IR_CR_IRTX_PW_UNIT_SHIFT) 153 #define IR_CR_IRTX_MOD_PH0_W_SHIFT (16U) 154 #define IR_CR_IRTX_MOD_PH0_W_MASK (0xff << IR_CR_IRTX_MOD_PH0_W_SHIFT) 155 #define IR_CR_IRTX_MOD_PH1_W_SHIFT (24U) 156 #define IR_CR_IRTX_MOD_PH1_W_MASK (0xff << IR_CR_IRTX_MOD_PH1_W_SHIFT) 157 158 #if defined(BL602) || defined(BL702) 159 /* 0x14 : irtx_pw */ 160 #define IR_CR_IRTX_LOGIC0_PH0_W_SHIFT (0U) 161 #define IR_CR_IRTX_LOGIC0_PH0_W_MASK (0xf<<IR_CR_IRTX_LOGIC0_PH0_W_SHIFT) 162 #define IR_CR_IRTX_LOGIC0_PH1_W_SHIFT (4U) 163 #define IR_CR_IRTX_LOGIC0_PH1_W_MASK (0xf<<IR_CR_IRTX_LOGIC0_PH1_W_SHIFT) 164 #define IR_CR_IRTX_LOGIC1_PH0_W_SHIFT (8U) 165 #define IR_CR_IRTX_LOGIC1_PH0_W_MASK (0xf<<IR_CR_IRTX_LOGIC1_PH0_W_SHIFT) 166 #define IR_CR_IRTX_LOGIC1_PH1_W_SHIFT (12U) 167 #define IR_CR_IRTX_LOGIC1_PH1_W_MASK (0xf<<IR_CR_IRTX_LOGIC1_PH1_W_SHIFT) 168 #define IR_CR_IRTX_HEAD_PH0_W_SHIFT (16U) 169 #define IR_CR_IRTX_HEAD_PH0_W_MASK (0xf<<IR_CR_IRTX_HEAD_PH0_W_SHIFT) 170 #define IR_CR_IRTX_HEAD_PH1_W_SHIFT (20U) 171 #define IR_CR_IRTX_HEAD_PH1_W_MASK (0xf<<IR_CR_IRTX_HEAD_PH1_W_SHIFT) 172 #define IR_CR_IRTX_TAIL_PH0_W_SHIFT (24U) 173 #define IR_CR_IRTX_TAIL_PH0_W_MASK (0xf<<IR_CR_IRTX_TAIL_PH0_W_SHIFT) 174 #define IR_CR_IRTX_TAIL_PH1_W_SHIFT (28U) 175 #define IR_CR_IRTX_TAIL_PH1_W_MASK (0xf<<IR_CR_IRTX_TAIL_PH1_W_SHIFT) 176 177 /* 0x40 : irtx_swm_pw_0 */ 178 #define IR_CR_IRTX_SWM_PW_0_SHIFT (0U) 179 #define IR_CR_IRTX_SWM_PW_0_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_0_SHIFT) 180 181 /* 0x44 : irtx_swm_pw_1 */ 182 #define IR_CR_IRTX_SWM_PW_1_SHIFT (0U) 183 #define IR_CR_IRTX_SWM_PW_1_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_1_SHIFT) 184 185 /* 0x48 : irtx_swm_pw_2 */ 186 #define IR_CR_IRTX_SWM_PW_2_SHIFT (0U) 187 #define IR_CR_IRTX_SWM_PW_2_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_2_SHIFT) 188 189 /* 0x4C : irtx_swm_pw_3 */ 190 #define IR_CR_IRTX_SWM_PW_3_SHIFT (0U) 191 #define IR_CR_IRTX_SWM_PW_3_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_3_SHIFT) 192 193 /* 0x50 : irtx_swm_pw_4 */ 194 #define IR_CR_IRTX_SWM_PW_4_SHIFT (0U) 195 #define IR_CR_IRTX_SWM_PW_4_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_4_SHIFT) 196 197 /* 0x54 : irtx_swm_pw_5 */ 198 #define IR_CR_IRTX_SWM_PW_5_SHIFT (0U) 199 #define IR_CR_IRTX_SWM_PW_5_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_5_SHIFT) 200 201 /* 0x58 : irtx_swm_pw_6 */ 202 #define IR_CR_IRTX_SWM_PW_6_SHIFT (0U) 203 #define IR_CR_IRTX_SWM_PW_6_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_6_SHIFT) 204 205 /* 0x5C : irtx_swm_pw_7 */ 206 #define IR_CR_IRTX_SWM_PW_7_SHIFT (0U) 207 #define IR_CR_IRTX_SWM_PW_7_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_7_SHIFT) 208 #else 209 /* 0x14 : irtx_pw_0 */ 210 #define IR_CR_IRTX_LOGIC0_PH0_W_SHIFT (0U) 211 #define IR_CR_IRTX_LOGIC0_PH0_W_MASK (0xff << IR_CR_IRTX_LOGIC0_PH0_W_SHIFT) 212 #define IR_CR_IRTX_LOGIC0_PH1_W_SHIFT (8U) 213 #define IR_CR_IRTX_LOGIC0_PH1_W_MASK (0xff << IR_CR_IRTX_LOGIC0_PH1_W_SHIFT) 214 #define IR_CR_IRTX_LOGIC1_PH0_W_SHIFT (16U) 215 #define IR_CR_IRTX_LOGIC1_PH0_W_MASK (0xff << IR_CR_IRTX_LOGIC1_PH0_W_SHIFT) 216 #define IR_CR_IRTX_LOGIC1_PH1_W_SHIFT (24U) 217 #define IR_CR_IRTX_LOGIC1_PH1_W_MASK (0xff << IR_CR_IRTX_LOGIC1_PH1_W_SHIFT) 218 219 /* 0x18 : irtx_pw_1 */ 220 #define IR_CR_IRTX_HEAD_PH0_W_SHIFT (0U) 221 #define IR_CR_IRTX_HEAD_PH0_W_MASK (0xff << IR_CR_IRTX_HEAD_PH0_W_SHIFT) 222 #define IR_CR_IRTX_HEAD_PH1_W_SHIFT (8U) 223 #define IR_CR_IRTX_HEAD_PH1_W_MASK (0xff << IR_CR_IRTX_HEAD_PH1_W_SHIFT) 224 #define IR_CR_IRTX_TAIL_PH0_W_SHIFT (16U) 225 #define IR_CR_IRTX_TAIL_PH0_W_MASK (0xff << IR_CR_IRTX_TAIL_PH0_W_SHIFT) 226 #define IR_CR_IRTX_TAIL_PH1_W_SHIFT (24U) 227 #define IR_CR_IRTX_TAIL_PH1_W_MASK (0xff << IR_CR_IRTX_TAIL_PH1_W_SHIFT) 228 #endif 229 #endif 230 231 #if !defined(BL702L) 232 /* 0x40 : irrx_config */ 233 #define IR_CR_IRRX_EN (1 << 0U) 234 #define IR_CR_IRRX_IN_INV (1 << 1U) 235 #define IR_CR_IRRX_MODE_SHIFT (2U) 236 #define IR_CR_IRRX_MODE_MASK (0x3 << IR_CR_IRRX_MODE_SHIFT) 237 #define IR_CR_IRRX_DEG_EN (1 << 4U) 238 #define IR_CR_IRRX_DEG_CNT_SHIFT (8U) 239 #define IR_CR_IRRX_DEG_CNT_MASK (0xf << IR_CR_IRRX_DEG_CNT_SHIFT) 240 241 /* 0x44 : irrx_int_sts */ 242 #define IRRX_END_INT (1 << 0U) 243 #if !defined(BL602) && !defined(BL702) 244 #define IRRX_FRDY_INT (1 << 1U) 245 #define IRRX_FER_INT (1 << 2U) 246 #endif 247 #define IR_CR_IRRX_END_MASK (1 << 8U) 248 #if !defined(BL602) && !defined(BL702) 249 #define IR_CR_IRRX_FRDY_MASK (1 << 9U) 250 #define IR_CR_IRRX_FER_MASK (1 << 10U) 251 #endif 252 #define IR_CR_IRRX_END_CLR (1 << 16U) 253 #define IR_CR_IRRX_END_EN (1 << 24U) 254 #if !defined(BL602) && !defined(BL702) 255 #define IR_CR_IRRX_FRDY_EN (1 << 25U) 256 #define IR_CR_IRRX_FER_EN (1 << 26U) 257 #endif 258 259 /* 0x48 : irrx_pw_config */ 260 #define IR_CR_IRRX_DATA_TH_SHIFT (0U) 261 #define IR_CR_IRRX_DATA_TH_MASK (0xffff << IR_CR_IRRX_DATA_TH_SHIFT) 262 #define IR_CR_IRRX_END_TH_SHIFT (16U) 263 #define IR_CR_IRRX_END_TH_MASK (0xffff << IR_CR_IRRX_END_TH_SHIFT) 264 265 /* 0x50 : irrx_data_count */ 266 #define IR_STS_IRRX_DATA_CNT_SHIFT (0U) 267 #define IR_STS_IRRX_DATA_CNT_MASK (0x7f << IR_STS_IRRX_DATA_CNT_SHIFT) 268 269 /* 0x54 : irrx_data_word0 */ 270 #define IR_STS_IRRX_DATA_WORD0_SHIFT (0U) 271 #define IR_STS_IRRX_DATA_WORD0_MASK (0xffffffff << IR_STS_IRRX_DATA_WORD0_SHIFT) 272 273 /* 0x58 : irrx_data_word1 */ 274 #define IR_STS_IRRX_DATA_WORD1_SHIFT (0U) 275 #define IR_STS_IRRX_DATA_WORD1_MASK (0xffffffff << IR_STS_IRRX_DATA_WORD1_SHIFT) 276 #endif 277 278 /* 0x80 : ir_fifo_config_0 */ 279 #if !defined(BL616) && !defined(BL602) && !defined(BL702) 280 #define IRTX_DMA_EN (1 << 0U) 281 #define IR_TX_FIFO_CLR (1 << 2U) 282 #endif 283 #if !defined(BL702L) 284 #if defined(BL602) || defined(BL702) 285 #define IR_RX_FIFO_CLR (1 << 0U) 286 #else 287 #define IR_RX_FIFO_CLR (1 << 3U) 288 #endif 289 #endif 290 #if !defined(BL616) && !defined(BL602) && !defined(BL702) 291 #define IR_TX_FIFO_OVERFLOW (1 << 4U) 292 #define IR_TX_FIFO_UNDERFLOW (1 << 5U) 293 #endif 294 #if !defined(BL702L) 295 #if defined(BL602) || defined(BL702) 296 #define IR_RX_FIFO_OVERFLOW (1<<2U) 297 #define IR_RX_FIFO_UNDERFLOW (1<<3U) 298 #else 299 #define IR_RX_FIFO_OVERFLOW (1 << 6U) 300 #define IR_RX_FIFO_UNDERFLOW (1 << 7U) 301 #endif 302 #endif 303 304 /* 0x84 : ir_fifo_config_1 */ 305 #if !defined(BL616) && !defined(BL602) && !defined(BL702) 306 #define IR_TX_FIFO_CNT_SHIFT (0U) 307 #define IR_TX_FIFO_CNT_MASK (0x7 << IR_TX_FIFO_CNT_SHIFT) 308 #endif 309 #if !defined(BL702L) 310 #if defined(BL602) || defined(BL702) 311 #define IR_RX_FIFO_CNT_SHIFT (4U) 312 #else 313 #define IR_RX_FIFO_CNT_SHIFT (8U) 314 #endif 315 #define IR_RX_FIFO_CNT_MASK (0x7f << IR_RX_FIFO_CNT_SHIFT) 316 #endif 317 #if !defined(BL616) && !defined(BL602) && !defined(BL702) 318 #define IR_TX_FIFO_TH_SHIFT (16U) 319 #define IR_TX_FIFO_TH_MASK (0x3 << IR_TX_FIFO_TH_SHIFT) 320 #endif 321 #if !defined(BL702L) && !defined(BL602) && !defined(BL702) 322 #define IR_RX_FIFO_TH_SHIFT (24U) 323 #define IR_RX_FIFO_TH_MASK (0x3f << IR_RX_FIFO_TH_SHIFT) 324 #endif 325 326 #if !defined(BL616) && !defined(BL602) && !defined(BL702) 327 /* 0x88 : ir_fifo_wdata */ 328 #define IR_TX_FIFO_WDATA_SHIFT (0U) 329 #define IR_TX_FIFO_WDATA_MASK (0xffffffff << IR_TX_FIFO_WDATA_SHIFT) 330 #endif 331 332 #if !defined(BL702L) 333 /* 0x8C : ir_fifo_rdata */ 334 #define IR_RX_FIFO_RDATA_SHIFT (0U) 335 #define IR_RX_FIFO_RDATA_MASK (0xffff << IR_RX_FIFO_RDATA_SHIFT) 336 #endif 337 338 #endif /* __HARDWARE_IR_H__ */ 339