1 /**********************************************************************
2 * $Id$      lpc177x_8x_emc.h            2011-06-02
3 *//**
4 * @file     lpc177x_8x_emc.h
5 * @brief    Contains all macro definitions and function prototypes
6 *           support for EMC firmware library on LPC177x_8x
7 * @version  1.0
8 * @date     02. June. 2011
9 * @author   NXP MCU SW Application Team
10 *
11 * Copyright(C) 2011, NXP Semiconductor
12 * All rights reserved.
13 *
14 ***********************************************************************
15 * Software that is described herein is for illustrative purposes only
16 * which provides customers with programming information regarding the
17 * products. This software is supplied "AS IS" without any warranties.
18 * NXP Semiconductors assumes no responsibility or liability for the
19 * use of the software, conveys no license or title under any patent,
20 * copyright, or mask work right to the product. NXP Semiconductors
21 * reserves the right to make changes in the software without
22 * notification. NXP Semiconductors also make no representation or
23 * warranty that such application will be suitable for the specified
24 * use without further testing or modification.
25 **********************************************************************/
26 
27 /* Peripheral group ----------------------------------------------------------- */
28 /** @defgroup EMC   EMC (External Memory Controller)
29  * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
30  * @{
31  */
32 
33 #ifndef __LPC177X_8X_EMC_H_
34 #define __LPC177X_8X_EMC_H_
35 
36 #include "lpc_types.h"
37 #include "LPC177x_8x.h"
38 
39 
40 /** @defgroup EMC_Private_Macros EMC Private Macros
41  * @{
42  */
43 
44 /***********************************************************************
45  * EMC Control Register (EMCControl)
46  **********************************************************************/
47 /* Control register mask */
48 #define EMC_Control_MASK            ((uint32_t )0x07)
49 /* Control register EMC: Enable control. */
50 #define EMC_Control_E               ((uint32_t )(1<<0))
51 /* Control register EMC: Address mirror control. */
52 #define EMC_Control_M               ((uint32_t )(1<<1))
53 /* Control register EMC: Low-power mode control. */
54 #define EMC_Control_L               ((uint32_t )(1<<2))
55 
56 /***********************************************************************
57  * EMC Status Register (EMCStatus)
58  **********************************************************************/
59 /* Status register mask */
60 #define EMC_Status_MASK             ((uint32_t )0x07)
61 /* Status register EMC: Busy. */
62 #define EMC_Status_B                ((uint32_t )(1<<0))
63 /* Status register EMC: Write buffer status. */
64 #define EMC_Status_S                ((uint32_t )(1<<1))
65 /* Status register EMC: Self-refresh acknowledge.. */
66 #define EMC_Status_SA               ((uint32_t )(1<<2))
67 
68 /***********************************************************************
69  * EMC Configuration register (EMCConfig)
70  **********************************************************************/
71 /* EMC Configuration register : Enable control. */
72 #define EMC_Config_Endian_Mode      ((uint32_t )(1<<0))
73 /* EMC Configuration register: CCLK. */
74 #define EMC_Config_CCLK             ((uinr32_t)(1<<8))
75 /* EMC Configuration register mask */
76 #define EMC_Config_MASK             ((uint32_t)(0x101))
77 
78 
79 /***********************************************************************
80  * Dynamic Memory Control register (EMCDynamicControl)
81  **********************************************************************/
82 /* Dynamic Memory Control register EMC: Dynamic memory clock enable. */
83 #define EMC_DynamicControl_CE           ((uint32_t )(1<<0))
84 /* Dynamic Memory Control register EMC: Dynamic memory clock control */
85 #define EMC_DynamicControl_CS           ((uint32_t )(1<<1))
86 /* Dynamic Memory Control register EMC: Self-refresh request, EMCSREFREQ*/
87 #define EMC_DynamicControl_SR           ((uint32_t )(1<<2))
88 /* Dynamic Memory Control register EMC: Memory clock control (MMC)*/
89 #define EMC_DynamicControl_MMC          ((uint32_t )(1<<5))
90 /* Dynamic Memory Control register EMC: SDRAM initialization*/
91 #define EMC_DynamicControl_I(n)         ((uint32_t )(n<<7))
92 /* Dynamic Memory Control register EMC: Low-power SDRAM deep-sleep mode (DP)*/
93 #define EMC_DynamicControl_DP           ((uint32_t ) (1<<13))
94 
95 /***********************************************************************
96  * Dynamic Memory Refresh Timer register (EMCDynamicRefresh)
97  **********************************************************************/
98 /* Dynamic Memory Refresh Timer register EMC: Refresh timer (REFRESH) */
99 #define EMC_DynamicRefresh_REFRESH(n)   ((uint32_t ) (n & 0x3ff))
100 
101 /***********************************************************************
102  * Dynamic Memory Read Configuration register (EMCDynamicReadConfig)
103  **********************************************************************/
104 /* EMCDynamicReadConfig register EMC:Read data strategy (RD) */
105 #define EMC_DynamicReadConfig_RD(n)     ((uint32_t )(n & 0x03))
106 
107 /***********************************************************************
108  * Dynamic Memory Percentage Command Period register (EMCDynamictRP)
109  **********************************************************************/
110 /* EMCDynamictRP register EMC: Precharge command period (tRP). */
111 #define EMC_DynamictRP_tRP(n)           ((uint32_t )(n & 0x0f))
112 
113 /***********************************************************************
114  * Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS)
115  **********************************************************************/
116 /* EMCDynamictRAS register EMC: Active to precharge command period (tRAS) */
117 #define EMC_DynamictRP_tRAS(n)          ((uint32_t )(n & 0x0f))
118 
119 /***********************************************************************
120  * Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR)
121  **********************************************************************/
122 /* EMCDynamictAPR register EMC: Last-data-out to active command time (tAPR) */
123 #define EMC_DynamictAPR_tAPR(n)         ((uint32_t )(n & 0x0f))
124 
125 /***********************************************************************
126  * Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL)
127  **********************************************************************/
128 /* EMCDynamictDAL register EMC: Data-in to active command (tDAL)*/
129 #define EMC_DynamictDAL_tDAL(n)         ((uint32_t )(n & 0x0f))
130 
131 /***********************************************************************
132  * Dynamic Memory Write Recovery Time register (EMCDynamictWR)
133  **********************************************************************/
134 /* EMCDynamictWR register EMC: Write recovery time (tWR)*/
135 #define EMC_DynamictWR_tWR(n)           (uint32_t )(n & 0x0f)
136 
137 /***********************************************************************
138  * Dynamic Memory Active to Active Command Period register (EMCDynamictRC)
139  **********************************************************************/
140 /* EMCDynamictRC register EMC: Active to active command period (tRC)*/
141 #define EMC_DynamictRC_tRC(n)           (uint32_t )(n & 0x1f)
142 
143 /***********************************************************************
144  * Dynamic Memory Auto-refresh Period register (EMCDynamictRFC)
145  **********************************************************************/
146 /* EMCDynamictRFC register EMC: Auto-refresh period and auto-refresh to active command period (tRFC)*/
147 #define EMC_DynamictRFC_tRFC(n)         ((uint32_t )(n & 0x1f))
148 
149 /***********************************************************************
150  * Dynamic Memory Exit Self-refresh register (EMCDynamictXSR)
151  **********************************************************************/
152 /* EMCDynamictXSR register EMC: Exit self-refresh to active command time (tXSR)*/
153 #define EMC_DynamictXSR_tXSR(n)         ((uint32_t )(n & 0x1f))
154 
155 /***********************************************************************
156  * Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD)
157  **********************************************************************/
158 /* EMCDynamictRRD register EMC: Active bank A to active bank B latency (tRRD )*/
159 #define EMC_DynamictRRD_tRRD(n)         ((uint32_t )(n & 0x0f))
160 
161 /***********************************************************************
162  Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD)
163  **********************************************************************/
164 /* EMCDynamictMRD register EMC: Load mode register to active command time (tMRD)*/
165 #define EMC_DynamictMRD_tMRD(n)         ((uint32_t )(n & 0x1f))
166 
167 /***********************************************************************
168  * Static Memory Extended Wait Register (EMCStaticExtendedWait)
169  **********************************************************************/
170 /* StaticExtendedWait register EMC: External wait time out. */
171 #define EMC_StaticExtendedWait_EXTENDEDWAIT(n)          ((uint32_t )(n & 0x3ff))
172 
173 
174 /***********************************************************************
175  * Dynamic Memory Configuration registers (EMCDynamicConfig0-3)
176  **********************************************************************/
177 /* DynamicConfig register EMC: Memory device (MD). */
178 #define EMC_DynamicConfig_MD(n)         ((uint32_t )(n << 3))
179 /* DynamicConfig register EMC: Address mapping (AM) */
180 #define EMC_DynamicConfig_AM1(n)        ((uint32_t )(n << 7))
181 /* DynamicConfig register EMC: Address mapping (AM) */
182 #define EMC_DynamicConfig_AM2(n)        ((uint32_t )(1 << 14))
183 /* DynamicConfig register EMC: Buffer enable */
184 #define EMC_DynamicConfig_B             ((uint32_t )(1 << 19))
185 /* DynamicConfig register EMC: Write protect (P) */
186 #define EMC_DynamicConfig_P             ((uint32_t )(1 << 20))
187 
188 /***********************************************************************
189  * Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3)
190  **********************************************************************/
191 /* DynamicRASCAS register EMC: RAS latency (active to read/write delay) (RAS). */
192 #define EMC_DynamicConfig_RAS(n)            ((uint32_t )(n & 0x03))
193 /* DynamicRASCAS register EMC: CAS latency (CAS)*/
194 #define EMC_DynamicConfig_CAS(n)            ((uint32_t )(n << 8))
195 
196 /***********************************************************************
197  * Static Memory Configuration registers (EMCStaticConfig0-3)
198  **********************************************************************/
199 /* StaticConfig register EMC: Memory width (MW). */
200 #define EMC_StaticConfig_MW(n)          ((uint32_t )(n & 0x03))
201 /* StaticConfig register EMC: Memory width 8bit . */
202 #define EMC_StaticConfig_MW_8BITS       (EMC_StaticConfig_MW(0))
203 /* StaticConfig register EMC: Memory width 16bit . */
204 #define EMC_StaticConfig_MW_16BITS      (EMC_StaticConfig_MW(1))
205 /* StaticConfig register EMC: Memory width 32bit . */
206 #define EMC_StaticConfig_MW_32BITS      (EMC_StaticConfig_MW(2))
207 /* StaticConfig register EMC: Page mode (PM) */
208 #define EMC_StaticConfig_PM             ((uint32_t )(1 << 3))
209 /* StaticConfig register EMC: Chip select polarity (PC) */
210 #define EMC_StaticConfig_PC             ((uint32_t )(1 << 6))
211 /* StaticConfig register EMC: Byte lane state (PB) */
212 #define EMC_StaticConfig_PB             ((uint32_t )(1 << 7))
213 /* StaticConfig register EMC: Extended wait (EW) */
214 #define EMC_StaticConfig_EW             ((uint32_t )(1 << 8))
215 /* StaticConfig register EMC: Buffer enable (B) */
216 #define EMC_StaticConfig_B              ((uint32_t )(1 << 19))
217 /* StaticConfig register EMC: Write protect (P) */
218 #define EMC_StaticConfig_P              ((uint32_t )(1 << 20))
219 
220 /***********************************************************************
221  * Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3)
222  **********************************************************************/
223 /* StaticWaitWen register EMC: Wait write enable (WAITWEN). */
224 #define EMC_StaticWaitWen_WAITWEN(n)    ((uint32_t )(n & 0x0f))
225 
226 /***********************************************************************
227  * Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3)
228  **********************************************************************/
229 /* StaticWaitOen register EMC: Wait output enable (WAITOEN). */
230 #define EMC_StaticWaitOen_WAITOEN(n)    ((uint32_t )(n & 0x0f))
231 
232 /***********************************************************************
233  * Static Memory Read Delay registers (EMCStaticWaitRd0-3)
234  **********************************************************************/
235 /* StaticWaitRd register EMC: Non-page mode read wait states or asynchronous page mode
236 read first access wait state (WAITRD) */
237 #define EMC_StaticWaitRd_WAITRD(n)      ((uint32_t )(n & 0x1f))
238 
239 /***********************************************************************
240  * Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3)
241  **********************************************************************/
242 /* StaticwaitPage register EMC: Asynchronous page mode read after the first
243 read wait states (WAITPAGE). */
244 #define EMC_StaticwaitPage_WAITPAGE(n)  ((uint32_t )(n & 0x1f))
245 
246 /***********************************************************************
247  * Static Memory Write Delay registers (EMCStaticWaitwr0-3)
248  **********************************************************************/
249 /* StaticWaitwr register EMC: Write wait states (WAITWR). */
250 #define EMC_StaticWaitwr_WAITWR(n)      ((uint32_t )(n & 0x1f))
251 
252 /***********************************************************************
253  * Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3)
254  **********************************************************************/
255 /* StaticWaitTurn register EMC: Bus turnaround cycles (WAITTURN). */
256 #define EMC_StaticWaitTurn_WAITTURN(n)  ((uint32_t )(n & 0x0f))
257 
258 /***********************************************************************
259  * Delay Control register (EMCDLYCTL)
260  **********************************************************************/
261 #define EMC_DLYCTL_CMDDLY(n)        ((uint32_t)(n&0x1F))
262 #define EMC_DLYCTL_FBCLKDLY(n)      ((uint32_t)((n&0x1F)<<8))
263 #define EMC_DLYCTL_CLKOUT0DLY(n)    ((uint32_t)((n&0x1F)<<16))
264 #define EMC_DLYCTL_CLKOUT1DLY(n)    ((uint32_t)((n&0x1F)<<24))
265 
266 /***********************************************************************
267  * EMC Calibration register (EMCCAL)
268  **********************************************************************/
269 #define EMC_CAL_CALVALUE(n)         ((uint32_t)(n&0xFF))
270 #define EMC_CAL_START               ((uint32_t)(1<<14))
271 #define EMC_CAL_DONE                ((uint32_t)(1<<15))
272 
273 #define EMC_LITTLE_ENDIAN_MODE      ((uint32_t)(0))
274 #define EMC_BIG_ENDIAN_MODE         ((uint32_t)(1))
275 
276 /**
277  * @}
278  */
279 
280 
281 /* Public Types --------------------------------------------------------------- */
282 /** @defgroup EMC_Public_Types EMC Public Types
283  * @{
284  */
285 /*EMC dynamic memory registers enum*/
286 typedef enum
287 {
288   EMC_DYN_MEM_REFRESH_TIMER,
289   EMC_DYN_MEM_READ_CONFIG,
290   EMC_DYN_MEM_TRP,
291   EMC_DYN_MEM_TRAS,
292   EMC_DYN_MEM_TSREX,
293   EMC_DYN_MEM_TAPR,
294   EMC_DYN_MEM_TDAL,
295   EMC_DYN_MEM_TWR,
296   EMC_DYN_MEM_TRC,
297   EMC_DYN_MEM_TRFC,
298   EMC_DYN_MEM_TXSR,
299   EMC_DYN_MEM_TRRD,
300   EMC_DYN_MEM_TMRD
301 } EMC_DYN_MEM_PAR;
302 
303 /*EMC static memory registers enum*/
304 typedef enum
305 {
306   EMC_STA_MEM_WAITWEN,
307   EMC_STA_MEM_WAITOEN,
308   EMC_STA_MEM_WAITRD,
309   EMC_STA_MEM_WAITPAGE,
310   EMC_STA_MEM_WAITWR,
311   EMC_STA_MEM_WAITTURN,
312 } EMC_STA_MEM_PAR;
313 
314 /**
315  * @}
316  */
317 
318 
319 /* Public Functions ----------------------------------------------------------- */
320 /** @defgroup EMC_Public_Functions EMC Public Functions
321  * @{
322  */
323 
324 extern void EMC_Init(void);
325 extern void EMC_ConfigEndianMode(uint32_t endian_mode);
326 extern void EMC_DynCtrlClockEnable(uint32_t clock_enable);
327 extern void EMC_DynCtrlClockControl(int32_t clock_control);
328 extern void EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode);
329 extern void EMC_DynCtrlMMC(uint32_t MMC_val);
330 extern void EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command);
331 extern void EMC_DynCtrlPowerDownMode(uint32_t SDRAM_command);
332 extern void EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val);
333 extern void EMC_StaticExtendedWait(uint32_t Extended_wait_time_out);
334 extern void EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev);
335 extern void EMC_DynMemConfigAM(uint32_t index , uint32_t add_mapped);
336 extern void EMC_DynMemConfigB(uint32_t index , uint32_t buff_control);
337 extern void EMC_DynMemConfigP(uint32_t index , uint32_t permission);
338 extern void EMC_DynMemRAS(uint32_t index , uint32_t ras_val);
339 extern void EMC_DynMemCAS(uint32_t index , uint32_t cas_val);
340 extern void EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width);
341 extern void EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode);
342 extern void EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val);
343 extern void EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val);
344 extern void EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait);
345 extern void EMC_StaMemConfigB(uint32_t index , uint32_t buf_val);
346 extern void EMC_StaMemConfigpP(uint32_t index , uint32_t per_val);
347 extern void EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val);
348 
349 /**
350  * @}
351  */
352 
353 
354 #endif /* __LPC177X_8X_EMC_H_ */
355 
356 /**
357  * @}
358  */
359 
360 
361 
362