1/*
2 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6/**
7 *                    ESP32-C3 Linker Script Memory Layout
8 * This file describes the memory layout (memory blocks) by virtual memory addresses.
9 * This linker script is passed through the C preprocessor to include configuration options.
10 * Please use preprocessor features sparingly!
11 * Restrict to simple macros with numeric values, and/or #if/#endif blocks.
12 */
13/*
14 * Automatically generated file. DO NOT EDIT.
15 * Espressif IoT Development Framework (ESP-IDF) Configuration Header
16 */
17
18/* List of deprecated options */
19/*
20 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
21 *
22 * SPDX-License-Identifier: Apache-2.0
23 */
24/* CPU instruction prefetch padding size for flash mmap scenario */
25_esp_flash_mmap_prefetch_pad_size = 16;
26/* CPU instruction prefetch padding size for memory protection scenario */
27_esp_memprot_prefetch_pad_size = 16;
28/* Memory alignment size for PMS */
29_esp_memprot_align_size = 512;
30_esp_mmu_block_size = (0x10000);
31/**
32 * physical memory is mapped twice to the vritual address (IRAM and DRAM).
33 * `I_D_SRAM_OFFSET` is the offset between the two locations of the same physical memory
34 */
35MEMORY
36{
37  /**
38   *  All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
39   *  of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
40   *  are connected to the data port of the CPU and eg allow byte-wise access.
41   */
42  /* IRAM for PRO CPU. */
43  iram0_0_seg (RX) : org = (0x4037C000 + 0x4000), len = 0x403CF600 - (0x4037C000 - 0x3FC7C000) - (0x3FC7C000 + 0x4000)
44  /* Flash mapped instruction data */
45  iram0_2_seg (RX) : org = 0x42000020, len = 0x800000-0x20
46  /**
47   * (0x20 offset above is a convenience for the app binary image generation.
48   * Flash cache has 64KB pages. The .bin file which is flashed to the chip
49   * has a 0x18 byte file header, and each segment has a 0x08 byte segment
50   * header. Setting this offset makes it simple to meet the flash cache MMU's
51   * constraint that (paddr % 64KB == vaddr % 64KB).)
52   */
53  /**
54   * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
55   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
56   */
57  dram0_0_seg (RW) : org = (0x3FC7C000 + 0x4000), len = 0x403CF600 - (0x4037C000 - 0x3FC7C000) - (0x3FC7C000 + 0x4000)
58  /* Flash mapped constant data */
59  drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20
60  /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
61  /**
62   * RTC fast memory (executable). Persists over deep sleep.
63   */
64  rtc_iram_seg(RWX) : org = 0x50000000, len = 0x2000 - 0
65}
66_static_data_end = _bss_end;
67/* Heap ends at top of dram0_0_seg */
68_heap_end = 0x40000000;
69_data_seg_org = ORIGIN(rtc_data_seg);
70/**
71 *  The lines below define location alias for .rtc.data section
72 *  As C3 only has RTC fast memory, this is not configurable like on other targets
73 */
74REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
75REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
76REGION_ALIAS("rtc_data_location", rtc_iram_seg );
77  REGION_ALIAS("default_code_seg", iram0_2_seg);
78  REGION_ALIAS("default_rodata_seg", drom0_0_seg);
79/**
80 *  If rodata default segment is placed in `drom0_0_seg`, then flash's first rodata section must
81 *  also be first in the segment.
82 */
83  ASSERT(_flash_rodata_dummy_start == ORIGIN(default_rodata_seg),
84         ".flash_rodata_dummy section must be placed at the beginning of the rodata segment.")
85    ASSERT ((__eh_frame_end > __eh_frame), "Error: eh_frame size is null!");
86    ASSERT ((__eh_frame_hdr_end > __eh_frame_hdr), "Error: eh_frame_hdr size is null!");
87