1 /***************************************************************************** 2 * Copyright (c) 2022, Nations Technologies Inc. 3 * 4 * All rights reserved. 5 * **************************************************************************** 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * - Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the disclaimer below. 12 * 13 * Nations' name may not be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 19 * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 22 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 23 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 24 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 25 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * ****************************************************************************/ 27 28 /** 29 * @file n32g43x_dma.h 30 * @author Nations 31 * @version v1.2.0 32 * 33 * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. 34 */ 35 #ifndef __N32G43X_DMA_H__ 36 #define __N32G43X_DMA_H__ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include "n32g43x.h" 43 44 /** @addtogroup N32G43x_StdPeriph_Driver 45 * @{ 46 */ 47 48 /** @addtogroup DMA 49 * @{ 50 */ 51 52 /** @addtogroup DMA_Exported_Types 53 * @{ 54 */ 55 56 /** 57 * @brief DMA Init structure definition 58 */ 59 60 typedef struct 61 { 62 uint32_t PeriphAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ 63 64 uint32_t MemAddr; /*!< Specifies the memory base address for DMAy Channelx. */ 65 66 uint32_t Direction; /*!< Specifies if the peripheral is the source or destination. 67 This parameter can be a value of @ref DMA_data_transfer_direction */ 68 69 uint32_t BufSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. 70 The data unit is equal to the configuration set in PeriphDataSize 71 or MemDataSize members depending in the transfer direction. */ 72 73 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register is incremented or not. 74 This parameter can be a value of @ref DMA_peripheral_incremented_mode */ 75 76 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. 77 This parameter can be a value of @ref DMA_memory_incremented_mode */ 78 79 uint32_t PeriphDataSize; /*!< Specifies the Peripheral data width. 80 This parameter can be a value of @ref DMA_peripheral_data_size */ 81 82 uint32_t MemDataSize; /*!< Specifies the Memory data width. 83 This parameter can be a value of @ref DMA_memory_data_size */ 84 85 uint32_t CircularMode; /*!< Specifies the operation mode of the DMAy Channelx. 86 This parameter can be a value of @ref DMA_circular_normal_mode. 87 @note: The circular buffer mode cannot be used if the memory-to-memory 88 data transfer is configured on the selected Channel */ 89 90 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 91 This parameter can be a value of @ref DMA_priority_level */ 92 93 uint32_t Mem2Mem; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. 94 This parameter can be a value of @ref DMA_memory_to_memory */ 95 } DMA_InitType; 96 97 /** 98 * @} 99 */ 100 101 /** @addtogroup DMA_Exported_Constants 102 * @{ 103 */ 104 105 #define IS_DMA_ALL_PERIPH(PERIPH) \ 106 (((PERIPH) == DMA_CH1) || ((PERIPH) == DMA_CH2) || ((PERIPH) == DMA_CH3) || ((PERIPH) == DMA_CH4) \ 107 || ((PERIPH) == DMA_CH5) || ((PERIPH) == DMA_CH6) || ((PERIPH) == DMA_CH7) || ((PERIPH) == DMA_CH8)) 108 109 /** @addtogroup DMA_data_transfer_direction 110 * @{ 111 */ 112 113 #define DMA_DIR_PERIPH_DST ((uint32_t)0x00000010) 114 #define DMA_DIR_PERIPH_SRC ((uint32_t)0x00000000) 115 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PERIPH_DST) || ((DIR) == DMA_DIR_PERIPH_SRC)) 116 /** 117 * @} 118 */ 119 120 /** @addtogroup DMA_peripheral_incremented_mode 121 * @{ 122 */ 123 124 #define DMA_PERIPH_INC_ENABLE ((uint32_t)0x00000040) 125 #define DMA_PERIPH_INC_DISABLE ((uint32_t)0x00000000) 126 #define IS_DMA_PERIPH_INC_STATE(STATE) (((STATE) == DMA_PERIPH_INC_ENABLE) || ((STATE) == DMA_PERIPH_INC_DISABLE)) 127 /** 128 * @} 129 */ 130 131 /** @addtogroup DMA_memory_incremented_mode 132 * @{ 133 */ 134 135 #define DMA_MEM_INC_ENABLE ((uint32_t)0x00000080) 136 #define DMA_MEM_INC_DISABLE ((uint32_t)0x00000000) 137 #define IS_DMA_MEM_INC_STATE(STATE) (((STATE) == DMA_MEM_INC_ENABLE) || ((STATE) == DMA_MEM_INC_DISABLE)) 138 /** 139 * @} 140 */ 141 142 /** @addtogroup DMA_peripheral_data_size 143 * @{ 144 */ 145 146 #define DMA_PERIPH_DATA_SIZE_BYTE ((uint32_t)0x00000000) 147 #define DMA_PERIPH_DATA_SIZE_HALFWORD ((uint32_t)0x00000100) 148 #define DMA_PERIPH_DATA_SIZE_WORD ((uint32_t)0x00000200) 149 #define IS_DMA_PERIPH_DATA_SIZE(SIZE) \ 150 (((SIZE) == DMA_PERIPH_DATA_SIZE_BYTE) || ((SIZE) == DMA_PERIPH_DATA_SIZE_HALFWORD) \ 151 || ((SIZE) == DMA_PERIPH_DATA_SIZE_WORD)) 152 /** 153 * @} 154 */ 155 156 /** @addtogroup DMA_memory_data_size 157 * @{ 158 */ 159 160 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) 161 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) 162 #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) 163 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) \ 164 (((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) \ 165 || ((SIZE) == DMA_MemoryDataSize_Word)) 166 /** 167 * @} 168 */ 169 170 /** @addtogroup DMA_circular_normal_mode 171 * @{ 172 */ 173 174 #define DMA_MODE_CIRCULAR ((uint32_t)0x00000020) 175 #define DMA_MODE_NORMAL ((uint32_t)0x00000000) 176 #define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL)) 177 /** 178 * @} 179 */ 180 181 /** @addtogroup DMA_priority_level 182 * @{ 183 */ 184 185 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)0x00003000) 186 #define DMA_PRIORITY_HIGH ((uint32_t)0x00002000) 187 #define DMA_PRIORITY_MEDIUM ((uint32_t)0x00001000) 188 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) 189 #define IS_DMA_PRIORITY(PRIORITY) \ 190 (((PRIORITY) == DMA_PRIORITY_VERY_HIGH) || ((PRIORITY) == DMA_PRIORITY_HIGH) \ 191 || ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_LOW)) 192 /** 193 * @} 194 */ 195 196 /** @addtogroup DMA_memory_to_memory 197 * @{ 198 */ 199 200 #define DMA_M2M_ENABLE ((uint32_t)0x00004000) 201 #define DMA_M2M_DISABLE ((uint32_t)0x00000000) 202 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_ENABLE) || ((STATE) == DMA_M2M_DISABLE)) 203 204 /** 205 * @} 206 */ 207 208 /** @addtogroup DMA_interrupts_definition 209 * @{ 210 */ 211 212 #define DMA_INT_TXC ((uint32_t)0x00000002) 213 #define DMA_INT_HTX ((uint32_t)0x00000004) 214 #define DMA_INT_ERR ((uint32_t)0x00000008) 215 #define IS_DMA_CONFIG_INT(IT) ((((IT)&0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) 216 217 #define DMA_INT_GLB1 ((uint32_t)0x00000001) 218 #define DMA_INT_TXC1 ((uint32_t)0x00000002) 219 #define DMA_INT_HTX1 ((uint32_t)0x00000004) 220 #define DMA_INT_ERR1 ((uint32_t)0x00000008) 221 #define DMA_INT_GLB2 ((uint32_t)0x00000010) 222 #define DMA_INT_TXC2 ((uint32_t)0x00000020) 223 #define DMA_INT_HTX2 ((uint32_t)0x00000040) 224 #define DMA_INT_ERR2 ((uint32_t)0x00000080) 225 #define DMA_INT_GLB3 ((uint32_t)0x00000100) 226 #define DMA_INT_TXC3 ((uint32_t)0x00000200) 227 #define DMA_INT_HTX3 ((uint32_t)0x00000400) 228 #define DMA_INT_ERR3 ((uint32_t)0x00000800) 229 #define DMA_INT_GLB4 ((uint32_t)0x00001000) 230 #define DMA_INT_TXC4 ((uint32_t)0x00002000) 231 #define DMA_INT_HTX4 ((uint32_t)0x00004000) 232 #define DMA_INT_ERR4 ((uint32_t)0x00008000) 233 #define DMA_INT_GLB5 ((uint32_t)0x00010000) 234 #define DMA_INT_TXC5 ((uint32_t)0x00020000) 235 #define DMA_INT_HTX5 ((uint32_t)0x00040000) 236 #define DMA_INT_ERR5 ((uint32_t)0x00080000) 237 #define DMA_INT_GLB6 ((uint32_t)0x00100000) 238 #define DMA_INT_TXC6 ((uint32_t)0x00200000) 239 #define DMA_INT_HTX6 ((uint32_t)0x00400000) 240 #define DMA_INT_ERR6 ((uint32_t)0x00800000) 241 #define DMA_INT_GLB7 ((uint32_t)0x01000000) 242 #define DMA_INT_TXC7 ((uint32_t)0x02000000) 243 #define DMA_INT_HTX7 ((uint32_t)0x04000000) 244 #define DMA_INT_ERR7 ((uint32_t)0x08000000) 245 #define DMA_INT_GLB8 ((uint32_t)0x10000000) 246 #define DMA_INT_TXC8 ((uint32_t)0x20000000) 247 #define DMA_INT_HTX8 ((uint32_t)0x40000000) 248 #define DMA_INT_ERR8 ((uint32_t)0x80000000) 249 250 251 #define IS_DMA_CLR_INT(IT) ((IT) != 0x00) 252 253 #define IS_DMA_GET_IT(IT) \ 254 (((IT) == DMA_INT_GLB1) || ((IT) == DMA_INT_TXC1) || ((IT) == DMA_INT_HTX1) || ((IT) == DMA_INT_ERR1) \ 255 || ((IT) == DMA_INT_GLB2) || ((IT) == DMA_INT_TXC2) || ((IT) == DMA_INT_HTX2) || ((IT) == DMA_INT_ERR2) \ 256 || ((IT) == DMA_INT_GLB3) || ((IT) == DMA_INT_TXC3) || ((IT) == DMA_INT_HTX3) || ((IT) == DMA_INT_ERR3) \ 257 || ((IT) == DMA_INT_GLB4) || ((IT) == DMA_INT_TXC4) || ((IT) == DMA_INT_HTX4) || ((IT) == DMA_INT_ERR4) \ 258 || ((IT) == DMA_INT_GLB5) || ((IT) == DMA_INT_TXC5) || ((IT) == DMA_INT_HTX5) || ((IT) == DMA_INT_ERR5) \ 259 || ((IT) == DMA_INT_GLB6) || ((IT) == DMA_INT_TXC6) || ((IT) == DMA_INT_HTX6) || ((IT) == DMA_INT_ERR6) \ 260 || ((IT) == DMA_INT_GLB7) || ((IT) == DMA_INT_TXC7) || ((IT) == DMA_INT_HTX7) || ((IT) == DMA_INT_ERR7) \ 261 || ((IT) == DMA_INT_GLB8) || ((IT) == DMA_INT_TXC8) || ((IT) == DMA_INT_HTX8) || ((IT) == DMA_INT_ERR8)) 262 263 /** 264 * @} 265 */ 266 267 /** @addtogroup DMA_flags_definition 268 * @{ 269 */ 270 #define DMA_FLAG_GL1 ((uint32_t)0x00000001) 271 #define DMA_FLAG_TC1 ((uint32_t)0x00000002) 272 #define DMA_FLAG_HT1 ((uint32_t)0x00000004) 273 #define DMA_FLAG_TE1 ((uint32_t)0x00000008) 274 #define DMA_FLAG_GL2 ((uint32_t)0x00000010) 275 #define DMA_FLAG_TC2 ((uint32_t)0x00000020) 276 #define DMA_FLAG_HT2 ((uint32_t)0x00000040) 277 #define DMA_FLAG_TE2 ((uint32_t)0x00000080) 278 #define DMA_FLAG_GL3 ((uint32_t)0x00000100) 279 #define DMA_FLAG_TC3 ((uint32_t)0x00000200) 280 #define DMA_FLAG_HT3 ((uint32_t)0x00000400) 281 #define DMA_FLAG_TE3 ((uint32_t)0x00000800) 282 #define DMA_FLAG_GL4 ((uint32_t)0x00001000) 283 #define DMA_FLAG_TC4 ((uint32_t)0x00002000) 284 #define DMA_FLAG_HT4 ((uint32_t)0x00004000) 285 #define DMA_FLAG_TE4 ((uint32_t)0x00008000) 286 #define DMA_FLAG_GL5 ((uint32_t)0x00010000) 287 #define DMA_FLAG_TC5 ((uint32_t)0x00020000) 288 #define DMA_FLAG_HT5 ((uint32_t)0x00040000) 289 #define DMA_FLAG_TE5 ((uint32_t)0x00080000) 290 #define DMA_FLAG_GL6 ((uint32_t)0x00100000) 291 #define DMA_FLAG_TC6 ((uint32_t)0x00200000) 292 #define DMA_FLAG_HT6 ((uint32_t)0x00400000) 293 #define DMA_FLAG_TE6 ((uint32_t)0x00800000) 294 #define DMA_FLAG_GL7 ((uint32_t)0x01000000) 295 #define DMA_FLAG_TC7 ((uint32_t)0x02000000) 296 #define DMA_FLAG_HT7 ((uint32_t)0x04000000) 297 #define DMA_FLAG_TE7 ((uint32_t)0x08000000) 298 #define DMA_FLAG_GL8 ((uint32_t)0x10000000) 299 #define DMA_FLAG_TC8 ((uint32_t)0x20000000) 300 #define DMA_FLAG_HT8 ((uint32_t)0x40000000) 301 #define DMA_FLAG_TE8 ((uint32_t)0x80000000) 302 303 #define IS_DMA_CLEAR_FLAG(FLAG) ((FLAG) != 0x00) 304 305 #define IS_DMA_GET_FLAG(FLAG) \ 306 (((FLAG) == DMA_FLAG_GL1) || ((FLAG) == DMA_FLAG_TC1) || ((FLAG) == DMA_FLAG_HT1) || ((FLAG) == DMA_FLAG_TE1) \ 307 || ((FLAG) == DMA_FLAG_GL2) || ((FLAG) == DMA_FLAG_TC2) || ((FLAG) == DMA_FLAG_HT2) \ 308 || ((FLAG) == DMA_FLAG_TE2) || ((FLAG) == DMA_FLAG_GL3) || ((FLAG) == DMA_FLAG_TC3) \ 309 || ((FLAG) == DMA_FLAG_HT3) || ((FLAG) == DMA_FLAG_TE3) || ((FLAG) == DMA_FLAG_GL4) \ 310 || ((FLAG) == DMA_FLAG_TC4) || ((FLAG) == DMA_FLAG_HT4) || ((FLAG) == DMA_FLAG_TE4) \ 311 || ((FLAG) == DMA_FLAG_GL5) || ((FLAG) == DMA_FLAG_TC5) || ((FLAG) == DMA_FLAG_HT5) \ 312 || ((FLAG) == DMA_FLAG_TE5) || ((FLAG) == DMA_FLAG_GL6) || ((FLAG) == DMA_FLAG_TC6) \ 313 || ((FLAG) == DMA_FLAG_HT6) || ((FLAG) == DMA_FLAG_TE6) || ((FLAG) == DMA_FLAG_GL7) \ 314 || ((FLAG) == DMA_FLAG_TC7) || ((FLAG) == DMA_FLAG_HT7) || ((FLAG) == DMA_FLAG_TE7) \ 315 || ((FLAG) == DMA_FLAG_GL8) || ((FLAG) == DMA_FLAG_TC8) || ((FLAG) == DMA_FLAG_HT8) \ 316 || ((FLAG) == DMA_FLAG_TE8)) 317 /** 318 * @} 319 */ 320 321 /** @addtogroup DMA_Buffer_Size 322 * @{ 323 */ 324 325 #define IS_DMA_BUF_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) 326 327 /** 328 * @} 329 */ 330 331 /** @addtogroup DMA_remap_request_definition 332 * @{ 333 */ 334 #define DMA_REMAP_ADC1 ((uint32_t)0x00000000) 335 #define DMA_REMAP_USART1_TX ((uint32_t)0x00000001) 336 #define DMA_REMAP_USART1_RX ((uint32_t)0x00000002) 337 #define DMA_REMAP_USART2_TX ((uint32_t)0x00000003) 338 #define DMA_REMAP_USART2_RX ((uint32_t)0x00000004) 339 #define DMA_REMAP_USART3_TX ((uint32_t)0x00000005) 340 #define DMA_REMAP_USART3_RX ((uint32_t)0x00000006) 341 #define DMA_REMAP_UART4_TX ((uint32_t)0x00000007) 342 #define DMA_REMAP_UART4_RX ((uint32_t)0x00000008) 343 #define DMA_REMAP_UART5_TX ((uint32_t)0x00000009) 344 #define DMA_REMAP_UART5_RX ((uint32_t)0x0000000A) 345 #define DMA_REMAP_LPUART_TX ((uint32_t)0x0000000B) 346 #define DMA_REMAP_LPUART_RX ((uint32_t)0x0000000C) 347 #define DMA_REMAP_SPI1_TX ((uint32_t)0x0000000D) 348 #define DMA_REMAP_SPI1_RX ((uint32_t)0x0000000E) 349 #define DMA_REMAP_SPI2_TX ((uint32_t)0x0000000F) 350 #define DMA_REMAP_SPI2_RX ((uint32_t)0x00000010) 351 #define DMA_REMAP_I2C1_TX ((uint32_t)0x00000011) 352 #define DMA_REMAP_I2C1_RX ((uint32_t)0x00000012) 353 #define DMA_REMAP_I2C2_TX ((uint32_t)0x00000013) 354 #define DMA_REMAP_I2C2_RX ((uint32_t)0x00000014) 355 #define DMA_REMAP_DAC1 ((uint32_t)0x00000015) 356 #define DMA_REMAP_TIM1_CH1 ((uint32_t)0x00000016) 357 #define DMA_REMAP_TIM1_CH2 ((uint32_t)0x00000017) 358 #define DMA_REMAP_TIM1_CH3 ((uint32_t)0x00000018) 359 #define DMA_REMAP_TIM1_CH4 ((uint32_t)0x00000019) 360 #define DMA_REMAP_TIM1_COM ((uint32_t)0x0000001A) 361 #define DMA_REMAP_TIM1_UP ((uint32_t)0x0000001B) 362 #define DMA_REMAP_TIM1_TRIG ((uint32_t)0x0000001C) 363 #define DMA_REMAP_TIM2_CH1 ((uint32_t)0x0000001D) 364 #define DMA_REMAP_TIM2_CH2 ((uint32_t)0x0000001E) 365 #define DMA_REMAP_TIM2_CH3 ((uint32_t)0x0000001F) 366 #define DMA_REMAP_TIM2_CH4 ((uint32_t)0x00000020) 367 #define DMA_REMAP_TIM2_UP ((uint32_t)0x00000021) 368 #define DMA_REMAP_TIM3_CH1 ((uint32_t)0x00000022) 369 #define DMA_REMAP_TIM3_CH3 ((uint32_t)0x00000023) 370 #define DMA_REMAP_TIM3_CH4 ((uint32_t)0x00000024) 371 #define DMA_REMAP_TIM3_UP ((uint32_t)0x00000025) 372 #define DMA_REMAP_TIM3_TRIG ((uint32_t)0x00000026) 373 #define DMA_REMAP_TIM4_CH1 ((uint32_t)0x00000027) 374 #define DMA_REMAP_TIM4_CH2 ((uint32_t)0x00000028) 375 #define DMA_REMAP_TIM4_CH3 ((uint32_t)0x00000029) 376 #define DMA_REMAP_TIM4_UP ((uint32_t)0x0000002A) 377 #define DMA_REMAP_TIM5_CH1 ((uint32_t)0x0000002B) 378 #define DMA_REMAP_TIM5_CH2 ((uint32_t)0x0000002C) 379 #define DMA_REMAP_TIM5_CH3 ((uint32_t)0x0000002D) 380 #define DMA_REMAP_TIM5_CH4 ((uint32_t)0x0000002E) 381 #define DMA_REMAP_TIM5_UP ((uint32_t)0x0000002F) 382 #define DMA_REMAP_TIM5_TRIG ((uint32_t)0x00000030) 383 #define DMA_REMAP_TIM6_UP ((uint32_t)0x00000031) 384 #define DMA_REMAP_TIM7_UP ((uint32_t)0x00000032) 385 #define DMA_REMAP_TIM8_CH1 ((uint32_t)0x00000033) 386 #define DMA_REMAP_TIM8_CH2 ((uint32_t)0x00000034) 387 #define DMA_REMAP_TIM8_CH3 ((uint32_t)0x00000035) 388 #define DMA_REMAP_TIM8_CH4 ((uint32_t)0x00000036) 389 #define DMA_REMAP_TIM8_COM ((uint32_t)0x00000037) 390 #define DMA_REMAP_TIM8_UP ((uint32_t)0x00000038) 391 #define DMA_REMAP_TIM8_TRIG ((uint32_t)0x00000039) 392 #define DMA_REMAP_TIM9_CH1 ((uint32_t)0x0000003A) 393 #define DMA_REMAP_TIM9_TRIG ((uint32_t)0x0000003B) 394 #define DMA_REMAP_TIM9_CH3 ((uint32_t)0x0000003C) 395 #define DMA_REMAP_TIM9_CH4 ((uint32_t)0x0000003D) 396 #define DMA_REMAP_TIM9_UP ((uint32_t)0x0000003E) 397 398 399 #define IS_DMA_REMAP(FLAG) \ 400 (((FLAG) == DMA_REMAP_ADC1) || ((FLAG) == DMA_REMAP_USART1_TX) || ((FLAG) == DMA_REMAP_USART1_RX) \ 401 || ((FLAG) == DMA_REMAP_USART2_TX) || ((FLAG) == DMA_REMAP_USART2_RX) || ((FLAG) == DMA_REMAP_USART3_TX) \ 402 || ((FLAG) == DMA_REMAP_USART3_RX) || ((FLAG) == DMA_REMAP_UART4_TX) || ((FLAG) == DMA_REMAP_UART4_RX) \ 403 || ((FLAG) == DMA_REMAP_UART5_TX) || ((FLAG) == DMA_REMAP_UART5_RX) || ((FLAG) == DMA_REMAP_LPUART_TX) \ 404 || ((FLAG) == DMA_REMAP_LPUART_RX) || ((FLAG) == DMA_REMAP_SPI1_TX) || ((FLAG) == DMA_REMAP_SPI1_RX) \ 405 || ((FLAG) == DMA_REMAP_SPI2_TX) || ((FLAG) == DMA_REMAP_SPI2_RX) || ((FLAG) == DMA_REMAP_I2C1_TX) \ 406 || ((FLAG) == DMA_REMAP_I2C1_RX) || ((FLAG) == DMA_REMAP_I2C2_TX) || ((FLAG) == DMA_REMAP_I2C2_RX) \ 407 || ((FLAG) == DMA_REMAP_DAC1) || ((FLAG) == DMA_REMAP_TIM1_CH1) || ((FLAG) == DMA_REMAP_TIM1_CH2) \ 408 || ((FLAG) == DMA_REMAP_TIM1_CH3) || ((FLAG) == DMA_REMAP_TIM1_CH4) || ((FLAG) == DMA_REMAP_TIM1_COM) \ 409 || ((FLAG) == DMA_REMAP_TIM1_UP) || ((FLAG) == DMA_REMAP_TIM1_TRIG)|| ((FLAG) == DMA_REMAP_TIM2_CH1) \ 410 || ((FLAG) == DMA_REMAP_TIM2_CH2) || ((FLAG) == DMA_REMAP_TIM2_CH3) || ((FLAG) == DMA_REMAP_TIM2_CH4) \ 411 || ((FLAG) == DMA_REMAP_TIM2_UP) || ((FLAG) == DMA_REMAP_TIM3_CH1) || ((FLAG) == DMA_REMAP_TIM3_CH3) \ 412 || ((FLAG) == DMA_REMAP_TIM3_CH4) || ((FLAG) == DMA_REMAP_TIM3_UP) || ((FLAG) == DMA_REMAP_TIM3_TRIG) \ 413 || ((FLAG) == DMA_REMAP_TIM4_CH1) || ((FLAG) == DMA_REMAP_TIM4_CH2) || ((FLAG) == DMA_REMAP_TIM4_CH3) \ 414 || ((FLAG) == DMA_REMAP_TIM4_UP) || ((FLAG) == DMA_REMAP_TIM5_CH1) || ((FLAG) == DMA_REMAP_TIM5_CH2) \ 415 || ((FLAG) == DMA_REMAP_TIM5_CH3) || ((FLAG) == DMA_REMAP_TIM5_CH4) || ((FLAG) == DMA_REMAP_TIM5_UP) \ 416 || ((FLAG) == DMA_REMAP_TIM5_TRIG)|| ((FLAG) == DMA_REMAP_TIM6_UP) || ((FLAG) == DMA_REMAP_TIM7_UP) \ 417 || ((FLAG) == DMA_REMAP_TIM8_CH1) || ((FLAG) == DMA_REMAP_TIM8_CH2) || ((FLAG) == DMA_REMAP_TIM8_CH3) \ 418 || ((FLAG) == DMA_REMAP_TIM8_CH4) || ((FLAG) == DMA_REMAP_TIM8_COM) || ((FLAG) == DMA_REMAP_TIM8_UP) \ 419 || ((FLAG) == DMA_REMAP_TIM8_TRIG)|| ((FLAG) == DMA_REMAP_TIM9_CH1) || ((FLAG) == DMA_REMAP_TIM9_TRIG) \ 420 || ((FLAG) == DMA_REMAP_TIM9_CH3) || ((FLAG) == DMA_REMAP_TIM9_CH4) || ((FLAG) == DMA_REMAP_TIM9_UP)) 421 /** 422 * @} 423 */ 424 425 /** 426 * @} 427 */ 428 429 /** @addtogroup DMA_Exported_Macros 430 * @{ 431 */ 432 433 /** 434 * @} 435 */ 436 437 /** @addtogroup DMA_Exported_Functions 438 * @{ 439 */ 440 441 void DMA_DeInit(DMA_ChannelType* DMAChx); 442 void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam); 443 void DMA_StructInit(DMA_InitType* DMA_InitParam); 444 void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd); 445 void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd); 446 void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber); 447 uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx); 448 FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy); 449 void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy); 450 INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy); 451 void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy); 452 void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd); 453 454 #ifdef __cplusplus 455 } 456 #endif 457 458 #endif /*__N32G43X_DMA_H__ */ 459 /** 460 * @} 461 */ 462 463 /** 464 * @} 465 */ 466 467 /** 468 * @} 469 */ 470