1 /***************************************************************************** 2 * Copyright (c) 2022, Nations Technologies Inc. 3 * 4 * All rights reserved. 5 * **************************************************************************** 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * - Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the disclaimer below. 12 * 13 * Nations' name may not be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 19 * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 22 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 23 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 24 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 25 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * ****************************************************************************/ 27 28 /** 29 * @file n32g43x_i2c.h 30 * @author Nations 31 * @version v1.2.0 32 * 33 * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. 34 */ 35 #ifndef __N32G43X_I2C_H__ 36 #define __N32G43X_I2C_H__ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include "n32g43x.h" 43 44 /** @addtogroup N32G43x_StdPeriph_Driver 45 * @{ 46 */ 47 48 /** @addtogroup I2C 49 * @{ 50 */ 51 52 /** @addtogroup I2C_Exported_Types 53 * @{ 54 */ 55 56 /** 57 * @brief I2C Init structure definition 58 */ 59 60 typedef struct 61 { 62 uint32_t ClkSpeed; /*!< Specifies the clock frequency. 63 This parameter must be set to a value lower than 400kHz */ 64 65 uint16_t BusMode; /*!< Specifies the I2C mode. 66 This parameter can be a value of @ref I2C_BusMode */ 67 68 uint16_t FmDutyCycle; /*!< Specifies the I2C fast mode duty cycle. 69 This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ 70 71 uint16_t OwnAddr1; /*!< Specifies the first device own address. 72 This parameter can be a 7-bit or 10-bit address. */ 73 74 uint16_t AckEnable; /*!< Enables or disables the acknowledgement. 75 This parameter can be a value of @ref I2C_acknowledgement */ 76 77 uint16_t AddrMode; /*!< Specifies if 7-bit or 10-bit address is acknowledged. 78 This parameter can be a value of @ref I2C_acknowledged_address */ 79 } I2C_InitType; 80 81 /** 82 * @} 83 */ 84 85 /** @addtogroup I2C_Exported_Constants 86 * @{ 87 */ 88 89 #define IS_I2C_PERIPH(PERIPH) (((PERIPH) == I2C1) || ((PERIPH) == I2C2)) 90 /** @addtogroup I2C_BusMode 91 * @{ 92 */ 93 94 #define I2C_BUSMODE_I2C ((uint16_t)0x0000) 95 #define I2C_BUSMODE_SMBDEVICE ((uint16_t)0x0002) 96 #define I2C_BUSMODE_SMBHOST ((uint16_t)0x000A) 97 #define IS_I2C_BUS_MODE(MODE) \ 98 (((MODE) == I2C_BUSMODE_I2C) || ((MODE) == I2C_BUSMODE_SMBDEVICE) || ((MODE) == I2C_BUSMODE_SMBHOST)) 99 /** 100 * @} 101 */ 102 103 /** @addtogroup I2C_duty_cycle_in_fast_mode 104 * @{ 105 */ 106 107 #define I2C_FMDUTYCYCLE_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ 108 #define I2C_FMDUTYCYCLE_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ 109 #define IS_I2C_FM_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_FMDUTYCYCLE_16_9) || ((CYCLE) == I2C_FMDUTYCYCLE_2)) 110 /** 111 * @} 112 */ 113 114 /** @addtogroup I2C_acknowledgement 115 * @{ 116 */ 117 118 #define I2C_ACKEN ((uint16_t)0x0400) 119 #define I2C_ACKDIS ((uint16_t)0x0000) 120 #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_ACKEN) || ((STATE) == I2C_ACKDIS)) 121 /** 122 * @} 123 */ 124 125 /** @addtogroup I2C_transfer_direction 126 * @{ 127 */ 128 129 #define I2C_DIRECTION_SEND ((uint8_t)0x00) 130 #define I2C_DIRECTION_RECV ((uint8_t)0x01) 131 #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_DIRECTION_SEND) || ((DIRECTION) == I2C_DIRECTION_RECV)) 132 /** 133 * @} 134 */ 135 136 /** @addtogroup I2C_acknowledged_address 137 * @{ 138 */ 139 140 #define I2C_ADDR_MODE_7BIT ((uint16_t)0x4000) 141 #define I2C_ADDR_MODE_10BIT ((uint16_t)0xC000) 142 #define IS_I2C_ADDR_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_MODE_7BIT) || ((ADDRESS) == I2C_ADDR_MODE_10BIT)) 143 /** 144 * @} 145 */ 146 147 /** @addtogroup I2C_registers 148 * @{ 149 */ 150 151 #define I2C_REG_CTRL1 ((uint8_t)0x00) 152 #define I2C_REG_CTRL2 ((uint8_t)0x04) 153 #define I2C_REG_OADDR1 ((uint8_t)0x08) 154 #define I2C_REG_OADDR2 ((uint8_t)0x0C) 155 #define I2C_REG_DAT ((uint8_t)0x10) 156 #define I2C_REG_STS1 ((uint8_t)0x14) 157 #define I2C_REG_STS2 ((uint8_t)0x18) 158 #define I2C_REG_CLKCTRL ((uint8_t)0x1C) 159 #define I2C_REG_TMRISE ((uint8_t)0x20) 160 #define IS_I2C_REG(REGISTER) \ 161 (((REGISTER) == I2C_REG_CTRL1) || ((REGISTER) == I2C_REG_CTRL2) || ((REGISTER) == I2C_REG_OADDR1) \ 162 || ((REGISTER) == I2C_REG_OADDR2) || ((REGISTER) == I2C_REG_DAT) || ((REGISTER) == I2C_REG_STS1) \ 163 || ((REGISTER) == I2C_REG_STS2) || ((REGISTER) == I2C_REG_CLKCTRL) || ((REGISTER) == I2C_REG_TMRISE)) 164 /** 165 * @} 166 */ 167 168 /** @addtogroup I2C_SMBus_alert_pin_level 169 * @{ 170 */ 171 172 #define I2C_SMBALERT_LOW ((uint16_t)0x2000) 173 #define I2C_SMBALERT_HIGH ((uint16_t)0xDFFF) 174 #define IS_I2C_SMB_ALERT(ALERT) (((ALERT) == I2C_SMBALERT_LOW) || ((ALERT) == I2C_SMBALERT_HIGH)) 175 /** 176 * @} 177 */ 178 179 /** @addtogroup I2C_PEC_position 180 * @{ 181 */ 182 183 #define I2C_PEC_POS_NEXT ((uint16_t)0x0800) 184 #define I2C_PEC_POS_CURRENT ((uint16_t)0xF7FF) 185 #define IS_I2C_PEC_POS(POSITION) (((POSITION) == I2C_PEC_POS_NEXT) || ((POSITION) == I2C_PEC_POS_CURRENT)) 186 /** 187 * @} 188 */ 189 190 /** @addtogroup I2C_NCAK_position 191 * @{ 192 */ 193 194 #define I2C_NACK_POS_NEXT ((uint16_t)0x0800) 195 #define I2C_NACK_POS_CURRENT ((uint16_t)0xF7FF) 196 #define IS_I2C_NACK_POS(POSITION) (((POSITION) == I2C_NACK_POS_NEXT) || ((POSITION) == I2C_NACK_POS_CURRENT)) 197 /** 198 * @} 199 */ 200 201 /** @addtogroup I2C_interrupts_definition 202 * @{ 203 */ 204 205 #define I2C_INT_BUF ((uint16_t)0x0400) 206 #define I2C_INT_EVENT ((uint16_t)0x0200) 207 #define I2C_INT_ERR ((uint16_t)0x0100) 208 #define IS_I2C_CFG_INT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) 209 /** 210 * @} 211 */ 212 213 /** @addtogroup I2C_interrupts_definition 214 * @{ 215 */ 216 217 #define I2C_INT_SMBALERT ((uint32_t)0x01008000) 218 #define I2C_INT_TIMOUT ((uint32_t)0x01004000) 219 #define I2C_INT_PECERR ((uint32_t)0x01001000) 220 #define I2C_INT_OVERRUN ((uint32_t)0x01000800) 221 #define I2C_INT_ACKFAIL ((uint32_t)0x01000400) 222 #define I2C_INT_ARLOST ((uint32_t)0x01000200) 223 #define I2C_INT_BUSERR ((uint32_t)0x01000100) 224 #define I2C_INT_TXDATE ((uint32_t)0x06000080) 225 #define I2C_INT_RXDATNE ((uint32_t)0x06000040) 226 #define I2C_INT_STOPF ((uint32_t)0x02000010) 227 #define I2C_INT_ADDR10F ((uint32_t)0x02000008) 228 #define I2C_INT_BYTEF ((uint32_t)0x02000004) 229 #define I2C_INT_ADDRF ((uint32_t)0x02000002) 230 #define I2C_INT_STARTBF ((uint32_t)0x02000001) 231 232 #define IS_I2C_CLR_INT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) 233 234 #define IS_I2C_GET_INT(IT) \ 235 (((IT) == I2C_INT_SMBALERT) || ((IT) == I2C_INT_TIMOUT) || ((IT) == I2C_INT_PECERR) || ((IT) == I2C_INT_OVERRUN) \ 236 || ((IT) == I2C_INT_ACKFAIL) || ((IT) == I2C_INT_ARLOST) || ((IT) == I2C_INT_BUSERR) || ((IT) == I2C_INT_TXDATE) \ 237 || ((IT) == I2C_INT_RXDATNE) || ((IT) == I2C_INT_STOPF) || ((IT) == I2C_INT_ADDR10F) || ((IT) == I2C_INT_BYTEF) \ 238 || ((IT) == I2C_INT_ADDRF) || ((IT) == I2C_INT_STARTBF)) 239 /** 240 * @} 241 */ 242 243 /** @addtogroup I2C_flags_definition 244 * @{ 245 */ 246 247 /** 248 * @brief STS2 register flags 249 */ 250 251 #define I2C_FLAG_DUALFLAG ((uint32_t)0x00800000) 252 #define I2C_FLAG_SMBHADDR ((uint32_t)0x00400000) 253 #define I2C_FLAG_SMBDADDR ((uint32_t)0x00200000) 254 #define I2C_FLAG_GCALLADDR ((uint32_t)0x00100000) 255 #define I2C_FLAG_TRF ((uint32_t)0x00040000) 256 #define I2C_FLAG_BUSY ((uint32_t)0x00020000) 257 #define I2C_FLAG_MSMODE ((uint32_t)0x00010000) 258 259 /** 260 * @brief STS1 register flags 261 */ 262 263 #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) 264 #define I2C_FLAG_TIMOUT ((uint32_t)0x10004000) 265 #define I2C_FLAG_PECERR ((uint32_t)0x10001000) 266 #define I2C_FLAG_OVERRUN ((uint32_t)0x10000800) 267 #define I2C_FLAG_ACKFAIL ((uint32_t)0x10000400) 268 #define I2C_FLAG_ARLOST ((uint32_t)0x10000200) 269 #define I2C_FLAG_BUSERR ((uint32_t)0x10000100) 270 #define I2C_FLAG_TXDATE ((uint32_t)0x10000080) 271 #define I2C_FLAG_RXDATNE ((uint32_t)0x10000040) 272 #define I2C_FLAG_STOPF ((uint32_t)0x10000010) 273 #define I2C_FLAG_ADDR10F ((uint32_t)0x10000008) 274 #define I2C_FLAG_BYTEF ((uint32_t)0x10000004) 275 #define I2C_FLAG_ADDRF ((uint32_t)0x10000002) 276 #define I2C_FLAG_STARTBF ((uint32_t)0x10000001) 277 278 #define IS_I2C_CLR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) 279 280 #define IS_I2C_GET_FLAG(FLAG) \ 281 (((FLAG) == I2C_FLAG_DUALFLAG) || ((FLAG) == I2C_FLAG_SMBHADDR) || ((FLAG) == I2C_FLAG_SMBDADDR) \ 282 || ((FLAG) == I2C_FLAG_GCALLADDR) || ((FLAG) == I2C_FLAG_TRF) || ((FLAG) == I2C_FLAG_BUSY) \ 283 || ((FLAG) == I2C_FLAG_MSMODE) || ((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMOUT) \ 284 || ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVERRUN) || ((FLAG) == I2C_FLAG_ACKFAIL) \ 285 || ((FLAG) == I2C_FLAG_ARLOST) || ((FLAG) == I2C_FLAG_BUSERR) || ((FLAG) == I2C_FLAG_TXDATE) \ 286 || ((FLAG) == I2C_FLAG_RXDATNE) || ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADDR10F) \ 287 || ((FLAG) == I2C_FLAG_BYTEF) || ((FLAG) == I2C_FLAG_ADDRF) || ((FLAG) == I2C_FLAG_STARTBF)) 288 /** 289 * @} 290 */ 291 292 /** @addtogroup I2C_Events 293 * @{ 294 */ 295 296 /*======================================== 297 298 I2C Master Events (Events grouped in order of communication) 299 ==========================================*/ 300 /** 301 * @brief Communication start 302 * 303 * After sending the START condition (I2C_GenerateStart() function) the master 304 * has to wait for this event. It means that the Start condition has been correctly 305 * released on the I2C bus (the bus is free, no other devices is communicating). 306 * 307 */ 308 /* Master mode */ 309 #define I2C_ROLE_MASTER ((uint32_t)0x00010000) /* MSMODE */ 310 /* --EV5 */ 311 #define I2C_EVT_MASTER_MODE_FLAG ((uint32_t)0x00030001) /* BUSY, MSMODE and SB flag */ 312 313 /** 314 * @brief Address Acknowledge 315 * 316 * After checking on EV5 (start condition correctly released on the bus), the 317 * master sends the address of the slave(s) with which it will communicate 318 * (I2C_SendAddr7bit() function, it also determines the direction of the communication: 319 * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges 320 * his address. If an acknowledge is sent on the bus, one of the following events will 321 * be set: 322 * 323 * 1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG 324 * event is set. 325 * 326 * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG 327 * is set 328 * 329 * 3) In case of 10-Bit addressing mode, the master (just after generating the START 330 * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() 331 * function). Then master should wait on EV9. It means that the 10-bit addressing 332 * header has been correctly sent on the bus. Then master should send the second part of 333 * the 10-bit address (LSB) using the function I2C_SendAddr7bit(). Then master 334 * should wait for event EV6. 335 * 336 */ 337 338 /* --EV6 */ 339 #define I2C_EVT_MASTER_TXMODE_FLAG ((uint32_t)0x00070082) /* BUSY, MSMODE, ADDRF, TXDATE and TRF flags */ 340 #define I2C_EVT_MASTER_RXMODE_FLAG ((uint32_t)0x00030002) /* BUSY, MSMODE and ADDRF flags */ 341 /* --EV9 */ 342 #define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG ((uint32_t)0x00030008) /* BUSY, MSMODE and ADDR10F flags */ 343 344 /** 345 * @brief Communication events 346 * 347 * If a communication is established (START condition generated and slave address 348 * acknowledged) then the master has to check on one of the following events for 349 * communication procedures: 350 * 351 * 1) Master Receiver mode: The master has to wait on the event EV7 then to read 352 * the data received from the slave (I2C_RecvData() function). 353 * 354 * 2) Master Transmitter mode: The master has to send data (I2C_SendData() 355 * function) then to wait on event EV8 or EV8_2. 356 * These two events are similar: 357 * - EV8 means that the data has been written in the data register and is 358 * being shifted out. 359 * - EV8_2 means that the data has been physically shifted out and output 360 * on the bus. 361 * In most cases, using EV8 is sufficient for the application. 362 * Using EV8_2 leads to a slower communication but ensure more reliable test. 363 * EV8_2 is also more suitable than EV8 for testing on the last data transmission 364 * (before Stop condition generation). 365 * 366 * @note In case the user software does not guarantee that this event EV7 is 367 * managed before the current byte end of transfer, then user may check on EV7 368 * and BSF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)). 369 * In this case the communication may be slower. 370 * 371 */ 372 373 /* Master RECEIVER mode -----------------------------*/ 374 /* --EV7 */ 375 #define I2C_EVT_MASTER_DATA_RECVD_FLAG ((uint32_t)0x00030040) /* BUSY, MSMODE and RXDATNE flags */ 376 /* EV7x shifter register full */ 377 #define I2C_EVT_MASTER_SFT_DATA_RECVD_FLAG ((uint32_t)0x00030044) /* BUSY, MSMODE, BSF and RXDATNE flags */ 378 379 /* Master TRANSMITTER mode --------------------------*/ 380 /* --EV8 */ 381 #define I2C_EVT_MASTER_DATA_SENDING ((uint32_t)0x00070080) /* TRF, BUSY, MSMODE, TXDATE flags */ 382 /* --EV8_2 */ 383 #define I2C_EVT_MASTER_DATA_SENDED ((uint32_t)0x00070084) /* TRF, BUSY, MSMODE, TXDATE and BSF flags */ 384 385 /*======================================== 386 387 I2C Slave Events (Events grouped in order of communication) 388 ==========================================*/ 389 390 /** 391 * @brief Communication start events 392 * 393 * Wait on one of these events at the start of the communication. It means that 394 * the I2C peripheral detected a Start condition on the bus (generated by master 395 * device) followed by the peripheral address. The peripheral generates an ACK 396 * condition on the bus (if the acknowledge feature is enabled through function 397 * I2C_ConfigAck()) and the events listed above are set : 398 * 399 * 1) In normal case (only one address managed by the slave), when the address 400 * sent by the master matches the own address of the peripheral (configured by 401 * OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set 402 * (where XXX could be TRANSMITTER or RECEIVER). 403 * 404 * 2) In case the address sent by the master matches the second address of the 405 * peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled 406 * by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 407 * (where XXX could be TRANSMITTER or RECEIVER) are set. 408 * 409 * 3) In case the address sent by the master is General Call (address 0x00) and 410 * if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall()) 411 * the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED. 412 * 413 */ 414 415 /* --EV1 (all the events below are variants of EV1) */ 416 /* 1) Case of One Single Address managed by the slave */ 417 #define I2C_EVT_SLAVE_RECV_ADDR_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDRF flags */ 418 #define I2C_EVT_SLAVE_SEND_ADDR_MATCHED ((uint32_t)0x00060082) /* TRF, BUSY, TXDATE and ADDRF flags */ 419 420 /* 2) Case of Dual address managed by the slave */ 421 #define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ 422 #define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED ((uint32_t)0x00860080) /* DUALF, TRF, BUSY and TXDATE flags */ 423 424 /* 3) Case of General Call enabled for the slave */ 425 #define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ 426 427 /** 428 * @brief Communication events 429 * 430 * Wait on one of these events when EV1 has already been checked and: 431 * 432 * - Slave RECEIVER mode: 433 * - EV2: When the application is expecting a data byte to be received. 434 * - EV4: When the application is expecting the end of the communication: master 435 * sends a stop condition and data transmission is stopped. 436 * 437 * - Slave Transmitter mode: 438 * - EV3: When a byte has been transmitted by the slave and the application is expecting 439 * the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and 440 * I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be 441 * used when the user software doesn't guarantee the EV3 is managed before the 442 * current byte end of transfer. 443 * - EV3_2: When the master sends a NACK in order to tell slave that data transmission 444 * shall end (before sending the STOP condition). In this case slave has to stop sending 445 * data bytes and expect a Stop condition on the bus. 446 * 447 * @note In case the user software does not guarantee that the event EV2 is 448 * managed before the current byte end of transfer, then user may check on EV2 449 * and BSF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)). 450 * In this case the communication may be slower. 451 * 452 */ 453 454 /* Slave RECEIVER mode --------------------------*/ 455 /* --EV2 */ 456 #define I2C_EVT_SLAVE_DATA_RECVD ((uint32_t)0x00020040) /* BUSY and RXDATNE flags */ 457 /* --EV2x */ 458 #define I2C_EVT_SLAVE_DATA_RECVD_NOBUSY ((uint32_t)0x00000040) /* no BUSY and RXDATNE flags */ 459 /* --EV4 */ 460 #define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)0x00000010) /* STOPF flag */ 461 462 /* Slave TRANSMITTER mode -----------------------*/ 463 /* --EV3 */ 464 #define I2C_EVT_SLAVE_DATA_SENDED ((uint32_t)0x00060084) /* TRF, BUSY, TXDATE and BSF flags */ 465 #define I2C_EVT_SLAVE_DATA_SENDING ((uint32_t)0x00060080) /* TRF, BUSY and TXDATE flags */ 466 /* --EV3_2 */ 467 #define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)0x00000400) /* AF flag */ 468 469 /*=========================== End of Events Description ==========================================*/ 470 471 #define IS_I2C_EVT(EVENT) \ 472 (((EVENT) == I2C_EVT_SLAVE_SEND_ADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR_MATCHED) \ 473 || ((EVENT) == I2C_EVT_SLAVE_SEND_ADDR2_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR2_MATCHED) \ 474 || ((EVENT) == I2C_EVT_SLAVE_GCALLADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD) \ 475 || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG)) \ 476 || ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_DATA_SENDED) \ 477 || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG)) \ 478 || ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_STOP_RECVD) \ 479 || ((EVENT) == I2C_EVT_MASTER_MODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_TXMODE_FLAG) \ 480 || ((EVENT) == I2C_EVT_MASTER_RXMODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_DATA_RECVD_FLAG) \ 481 || ((EVENT) == I2C_EVT_MASTER_DATA_SENDED) || ((EVENT) == I2C_EVT_MASTER_DATA_SENDING) \ 482 || ((EVENT) == I2C_EVT_MASTER_MODE_ADDRESS10_FLAG) || ((EVENT) == I2C_EVT_SLAVE_ACK_MISS) \ 483 || ((EVENT) == I2C_EVT_MASTER_SFT_DATA_RECVD_FLAG) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD_NOBUSY)) 484 /** 485 * @} 486 */ 487 488 /** @addtogroup I2C_own_address1 489 * @{ 490 */ 491 492 #define IS_I2C_OWN_ADDR1(ADDRESS1) ((ADDRESS1) <= 0x3FF) 493 /** 494 * @} 495 */ 496 497 /** @addtogroup I2C_clock_speed 498 * @{ 499 */ 500 501 //#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) 502 #define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 1000000)) 503 504 /** 505 * @} 506 */ 507 508 /** 509 * @} 510 */ 511 512 /** @addtogroup I2C_Exported_Macros 513 * @{ 514 */ 515 516 /** 517 * @} 518 */ 519 520 /** @addtogroup I2C_Exported_Functions 521 * @{ 522 */ 523 524 void I2C_DeInit(I2C_Module* I2Cx); 525 void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct); 526 void I2C_InitStruct(I2C_InitType* I2C_InitStruct); 527 void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd); 528 void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd); 529 void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd); 530 void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd); 531 void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd); 532 void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd); 533 void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address); 534 void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd); 535 void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd); 536 void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd); 537 void I2C_SendData(I2C_Module* I2Cx, uint8_t Data); 538 uint8_t I2C_RecvData(I2C_Module* I2Cx); 539 void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction); 540 uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register); 541 void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd); 542 void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition); 543 void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert); 544 void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd); 545 void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition); 546 void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd); 547 uint8_t I2C_GetPec(I2C_Module* I2Cx); 548 void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd); 549 void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd); 550 void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle); 551 552 /** 553 * @brief 554 **************************************************************************************** 555 * 556 * I2C State Monitoring Functions 557 * 558 **************************************************************************************** 559 * This I2C driver provides three different ways for I2C state monitoring 560 * depending on the application requirements and constraints: 561 * 562 * 563 * 1) Basic state monitoring: 564 * Using I2C_CheckEvent() function: 565 * It compares the status registers (STS1 and STS2) content to a given event 566 * (can be the combination of one or more flags). 567 * It returns SUCCESS if the current status includes the given flags 568 * and returns ERROR if one or more flags are missing in the current status. 569 * - When to use: 570 * - This function is suitable for most applications as well as for startup 571 * activity since the events are fully described in the product reference manual 572 * (RM0008). 573 * - It is also suitable for users who need to define their own events. 574 * - Limitations: 575 * - If an error occurs (ie. error flags are set besides to the monitored flags), 576 * the I2C_CheckEvent() function may return SUCCESS despite the communication 577 * hold or corrupted real state. 578 * In this case, it is advised to use error interrupts to monitor the error 579 * events and handle them in the interrupt IRQ handler. 580 * 581 * @note 582 * For error management, it is advised to use the following functions: 583 * - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR). 584 * - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. 585 * Where x is the peripheral instance (I2C1, I2C2 ...) 586 * - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler() 587 * in order to determine which error occurred. 588 * - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset() 589 * and/or I2C_GenerateStop() in order to clear the error flag and source, 590 * and return to correct communication status. 591 * 592 * 593 * 2) Advanced state monitoring: 594 * Using the function I2C_GetLastEvent() which returns the image of both status 595 * registers in a single word (uint32_t) (Status Register 2 value is shifted left 596 * by 16 bits and concatenated to Status Register 1). 597 * - When to use: 598 * - This function is suitable for the same applications above but it allows to 599 * overcome the limitations of I2C_GetFlag() function (see below). 600 * The returned value could be compared to events already defined in the 601 * library (n32g43x_i2c.h) or to custom values defined by user. 602 * - This function is suitable when multiple flags are monitored at the same time. 603 * - At the opposite of I2C_CheckEvent() function, this function allows user to 604 * choose when an event is accepted (when all events flags are set and no 605 * other flags are set or just when the needed flags are set like 606 * I2C_CheckEvent() function). 607 * - Limitations: 608 * - User may need to define his own events. 609 * - Same remark concerning the error management is applicable for this 610 * function if user decides to check only regular communication flags (and 611 * ignores error flags). 612 * 613 * 614 * 3) Flag-based state monitoring: 615 * Using the function I2C_GetFlag() which simply returns the status of 616 * one single flag (ie. I2C_FLAG_RXDATNE ...). 617 * - When to use: 618 * - This function could be used for specific applications or in debug phase. 619 * - It is suitable when only one flag checking is needed (most I2C events 620 * are monitored through multiple flags). 621 * - Limitations: 622 * - When calling this function, the Status register is accessed. Some flags are 623 * cleared when the status register is accessed. So checking the status 624 * of one Flag, may clear other ones. 625 * - Function may need to be called twice or more in order to monitor one 626 * single event. 627 * 628 */ 629 630 /** 631 * 632 * 1) Basic state monitoring 633 ******************************************************************************* 634 */ 635 ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT); 636 /** 637 * 638 * 2) Advanced state monitoring 639 ******************************************************************************* 640 */ 641 uint32_t I2C_GetLastEvent(I2C_Module* I2Cx); 642 /** 643 * 644 * 3) Flag-based state monitoring 645 ******************************************************************************* 646 */ 647 FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG); 648 /** 649 * 650 ******************************************************************************* 651 */ 652 653 void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG); 654 INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT); 655 void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT); 656 657 #ifdef __cplusplus 658 } 659 #endif 660 661 #endif /*__N32G43X_I2C_H */ 662 /** 663 * @} 664 */ 665 666 /** 667 * @} 668 */ 669 670 /** 671 * @} 672 */ 673