1 /*****************************************************************************
2 * Copyright (c) 2019, Nations Technologies Inc.
3 *
4 * All rights reserved.
5 * ****************************************************************************
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * - Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the disclaimer below.
12 *
13 * Nations' name may not be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
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19 * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
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27
28 /**
29 * @file n32g45x_xfmc.c
30 * @author Nations
31 * @version v1.0.1
32 *
33 * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
34 */
35 #include "n32g45x_xfmc.h"
36 #include "n32g45x_rcc.h"
37
38 /** @addtogroup N32G45X_StdPeriph_Driver
39 * @{
40 */
41
42 /** @addtogroup XFMC
43 * @brief XFMC driver modules
44 * @{
45 */
46
47 /** @addtogroup XFMC_Private_TypesDefinitions
48 * @{
49 */
50 /**
51 * @}
52 */
53
54 /** @addtogroup XFMC_Private_Defines
55 * @{
56 */
57
58 /**
59 * @}
60 */
61
62 /** @addtogroup XFMC_Private_Macros
63 * @{
64 */
65
66 /**
67 * @}
68 */
69
70 /** @addtogroup XFMC_Private_Variables
71 * @{
72 */
73
74 /**
75 * @}
76 */
77
78 /** @addtogroup XFMC_Private_FunctionPrototypes
79 * @{
80 */
81
82 /**
83 * @}
84 */
85
86 /** @addtogroup XFMC_Private_Functions
87 * @{
88 */
89
90 /**
91 * @brief Deinitializes the XFMC NOR/SRAM Banks registers to their default
92 * reset values.
93 * @param Bank specifies the XFMC Bank to be used
94 * This parameter can be one of the following values:
95 * @arg XFMC_BANK1_BLOCK1 XFMC Bank1 NOR/SRAM1
96 * @arg XFMC_BANK1_BLOCK2 XFMC Bank1 NOR/SRAM2
97 * @retval None
98 */
XFMC_DeInitNorSram(XFMC_Bank1_Block * Block)99 void XFMC_DeInitNorSram(XFMC_Bank1_Block *Block)
100 {
101 /* Check the parameter */
102 assert_param(IS_XFMC_NOR_SRAM_BLOCK(Block));
103
104 /* XFMC_BANK1_BLOCK1 */
105 if (Block == XFMC_BANK1_BLOCK1)
106 {
107 Block->CRx = XFMC_NOR_SRAM_CR1_RESET;
108 }
109 /* XFMC_BANK1_BLOCK2 */
110 else
111 {
112 Block->CRx = XFMC_NOR_SRAM_CR2_RESET;
113 }
114
115 Block->TRx = XFMC_NOR_SRAM_TR_RESET;
116 Block->WTRx = XFMC_NOR_SRAM_WTR_RESET;
117 }
118
119 /**
120 * @brief Deinitializes the XFMC NAND Banks registers to their default reset values.
121 * @param Bank specifies the XFMC Bank to be used
122 * This parameter can be one of the following values:
123 * @arg XFMC_BANK2_NAND XFMC Bank2 NAND
124 * @arg XFMC_BANK3_NAND XFMC Bank3 NAND
125 * @retval None
126 */
XFMC_DeInitNand(XFMC_Bank23_Module * Bank)127 void XFMC_DeInitNand(XFMC_Bank23_Module *Bank)
128 {
129 /* Check the parameter */
130 assert_param(IS_XFMC_NAND_BANK(Bank));
131
132 Bank->CTRLx = XFMC_NAND_CTRL_RESET;
133 Bank->STSx = XFMC_NAND_STS_RESET;
134 Bank->CMEMTMx = XFMC_NAND_CMEMTM_RESET;
135 Bank->ATTMEMTMx = XFMC_NAND_ATTMEMTM_RESET;
136 }
137
138 /**
139 * @brief Initializes the XFMC NOR/SRAM Banks according to the specified
140 * parameters in the XFMC_NORSRAMInitStruct.
141 * @param XFMC_NORSRAMInitStruct pointer to a XFMC_NorSramInitTpye
142 * structure that contains the configuration information for
143 * the XFMC NOR/SRAM specified Banks.
144 * @retval None
145 */
XFMC_InitNorSram(XFMC_NorSramInitTpye * XFMC_NORSRAMInitStruct)146 void XFMC_InitNorSram(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct)
147 {
148 /* Check the parameters */
149 assert_param(IS_XFMC_NOR_SRAM_BLOCK(XFMC_NORSRAMInitStruct->Block));
150 assert_param(IS_XFMC_NOR_SRAM_MUX(XFMC_NORSRAMInitStruct->DataAddrMux));
151 assert_param(IS_XFMC_NOR_SRAM_MEMORY(XFMC_NORSRAMInitStruct->MemType));
152 assert_param(IS_XFMC_NOR_SRAM_MEMORY_WIDTH(XFMC_NORSRAMInitStruct->MemDataWidth));
153 assert_param(IS_XFMC_NOR_SRAM_BURSTMODE(XFMC_NORSRAMInitStruct->BurstAccMode));
154 assert_param(IS_XFMC_NOR_SRAM_ASYNWAIT(XFMC_NORSRAMInitStruct->AsynchroWait));
155 assert_param(IS_XFMC_NOR_SRAM_WAIT_POLARITY(XFMC_NORSRAMInitStruct->WaitSigPolarity));
156 assert_param(IS_XFMC_NOR_SRAM_WRAP_MODE(XFMC_NORSRAMInitStruct->WrapMode));
157 assert_param(IS_XFMC_NOR_SRAM_WAIT_SIGNAL_ACTIVE(XFMC_NORSRAMInitStruct->WaitSigConfig));
158 assert_param(IS_XFMC_NOR_SRAM_WRITE_OPERATION(XFMC_NORSRAMInitStruct->WriteEnable));
159 assert_param(IS_XFMC_NOR_SRAM_WAITE_SIGNAL(XFMC_NORSRAMInitStruct->WaitSigEnable));
160 assert_param(IS_XFMC_NOR_SRAM_EXTENDED_MODE(XFMC_NORSRAMInitStruct->ExtModeEnable));
161 assert_param(IS_XFMC_NOR_SRAM_WRITE_BURST(XFMC_NORSRAMInitStruct->WriteBurstEnable));
162 assert_param(IS_XFMC_NOR_SRAM_ADDR_SETUP_TIME(XFMC_NORSRAMInitStruct->RWTimingStruct->AddrSetTime));
163 assert_param(IS_XFMC_NOR_SRAM_ADDR_HOLD_TIME(XFMC_NORSRAMInitStruct->RWTimingStruct->AddrHoldTime));
164 assert_param(IS_XFMC_NOR_SRAM_DATASETUP_TIME(XFMC_NORSRAMInitStruct->RWTimingStruct->DataSetTime));
165 assert_param(IS_XFMC_NOR_SRAM_BUSRECOVERY_TIME(XFMC_NORSRAMInitStruct->RWTimingStruct->BusRecoveryCycle));
166 assert_param(IS_XFMC_NOR_SRAM_CLK_DIV(XFMC_NORSRAMInitStruct->RWTimingStruct->ClkDiv));
167 assert_param(IS_XFMC_NOR_SRAM_DATA_LATENCY(XFMC_NORSRAMInitStruct->RWTimingStruct->DataLatency));
168 assert_param(IS_XFMC_NOR_SRAM_ACCESS_MODE(XFMC_NORSRAMInitStruct->RWTimingStruct->AccMode));
169
170 /* Bank1 NOR/SRAM control register configuration */
171 XFMC_NORSRAMInitStruct->Block->CRx = XFMC_NORSRAMInitStruct->DataAddrMux
172 | XFMC_NORSRAMInitStruct->MemType
173 | XFMC_NORSRAMInitStruct->MemDataWidth
174 | XFMC_NORSRAMInitStruct->BurstAccMode
175 | XFMC_NORSRAMInitStruct->AsynchroWait
176 | XFMC_NORSRAMInitStruct->WaitSigPolarity
177 | XFMC_NORSRAMInitStruct->WrapMode
178 | XFMC_NORSRAMInitStruct->WaitSigConfig
179 | XFMC_NORSRAMInitStruct->WriteEnable
180 | XFMC_NORSRAMInitStruct->WaitSigEnable
181 | XFMC_NORSRAMInitStruct->ExtModeEnable
182 | XFMC_NORSRAMInitStruct->WriteBurstEnable;
183
184 if (XFMC_NORSRAMInitStruct->MemType == XFMC_MEM_TYPE_NOR)
185 {
186 XFMC_NORSRAMInitStruct->Block->CRx |= (uint32_t)XFMC_NOR_SRAM_ACC_ENABLE;
187 }
188
189 /* Bank1 NOR/SRAM timing register configuration */
190 XFMC_NORSRAMInitStruct->Block->TRx = XFMC_NORSRAMInitStruct->RWTimingStruct->AddrSetTime
191 | XFMC_NORSRAMInitStruct->RWTimingStruct->AddrHoldTime
192 | XFMC_NORSRAMInitStruct->RWTimingStruct->DataSetTime
193 | XFMC_NORSRAMInitStruct->RWTimingStruct->BusRecoveryCycle
194 | XFMC_NORSRAMInitStruct->RWTimingStruct->ClkDiv
195 | XFMC_NORSRAMInitStruct->RWTimingStruct->DataLatency
196 | XFMC_NORSRAMInitStruct->RWTimingStruct->AccMode;
197
198 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
199 if (XFMC_NORSRAMInitStruct->ExtModeEnable == XFMC_NOR_SRAM_EXTENDED_ENABLE)
200 {
201 assert_param(IS_XFMC_NOR_SRAM_ADDR_SETUP_TIME(XFMC_NORSRAMInitStruct->WTimingStruct->AddrSetTime));
202 assert_param(IS_XFMC_NOR_SRAM_ADDR_HOLD_TIME(XFMC_NORSRAMInitStruct->WTimingStruct->AddrHoldTime));
203 assert_param(IS_XFMC_NOR_SRAM_DATASETUP_TIME(XFMC_NORSRAMInitStruct->WTimingStruct->DataSetTime));
204 assert_param(IS_XFMC_NOR_SRAM_CLK_DIV(XFMC_NORSRAMInitStruct->WTimingStruct->ClkDiv));
205 assert_param(IS_XFMC_NOR_SRAM_DATA_LATENCY(XFMC_NORSRAMInitStruct->WTimingStruct->DataLatency));
206 assert_param(IS_XFMC_NOR_SRAM_ACCESS_MODE(XFMC_NORSRAMInitStruct->WTimingStruct->AccMode));
207 XFMC_NORSRAMInitStruct->Block->WTRx = XFMC_NORSRAMInitStruct->WTimingStruct->AddrSetTime
208 | XFMC_NORSRAMInitStruct->WTimingStruct->AddrHoldTime
209 | (XFMC_NORSRAMInitStruct->WTimingStruct->DataSetTime << XFMC_BANK1_WTR_DATABLD_SHIFT)
210 | XFMC_NORSRAMInitStruct->WTimingStruct->ClkDiv
211 | XFMC_NORSRAMInitStruct->WTimingStruct->DataLatency
212 | XFMC_NORSRAMInitStruct->WTimingStruct->AccMode;
213 }
214 else
215 {
216 XFMC_NORSRAMInitStruct->Block->WTRx = XFMC_NOR_SRAM_WTR_RESET;
217 }
218 }
219
220 /**
221 * @brief Initializes the XFMC NAND Banks according to the specified
222 * parameters in the XFMC_NANDInitStruct.
223 * @param XFMC_NANDInitStruct pointer to a XFMC_NandInitType
224 * structure that contains the configuration information for the XFMC
225 * NAND specified Banks.
226 * @retval None
227 */
XFMC_InitNand(XFMC_NandInitType * XFMC_NANDInitStruct)228 void XFMC_InitNand(XFMC_NandInitType* XFMC_NANDInitStruct)
229 {
230 uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
231
232 /* Check the parameters */
233 assert_param(IS_XFMC_NAND_BANK(XFMC_NANDInitStruct->Bank));
234 assert_param(IS_XFMC_NAND_WAIT_FEATURE(XFMC_NANDInitStruct->WaitFeatureEnable));
235 assert_param(IS_XFMC_NAND_BUS_WIDTH(XFMC_NANDInitStruct->MemDataWidth));
236 assert_param(IS_XFMC_ECC_STATE(XFMC_NANDInitStruct->EccEnable));
237 assert_param(IS_XFMC_NAND_ECC_PAGE_SIZE(XFMC_NANDInitStruct->EccPageSize));
238 assert_param(IS_XFMC_NAND_CLE_DELAY(XFMC_NANDInitStruct->TCLRSetTime));
239 assert_param(IS_XFMC_NAND_ALE_DELAY(XFMC_NANDInitStruct->TARSetTime));
240 assert_param(IS_XFMC_NAND_SETUP_TIME(XFMC_NANDInitStruct->CommSpaceTimingStruct->SetTime));
241 assert_param(IS_XFMC_NAND_WAIT_TIME(XFMC_NANDInitStruct->CommSpaceTimingStruct->WaitSetTime));
242 assert_param(IS_XFMC_NAND_HOLD_TIME(XFMC_NANDInitStruct->CommSpaceTimingStruct->HoldSetTime));
243 assert_param(IS_XFMC_NAND_HIZ_TIME(XFMC_NANDInitStruct->CommSpaceTimingStruct->HiZSetTime));
244 assert_param(IS_XFMC_NAND_SETUP_TIME(XFMC_NANDInitStruct->AttrSpaceTimingStruct->SetTime));
245 assert_param(IS_XFMC_NAND_WAIT_TIME(XFMC_NANDInitStruct->AttrSpaceTimingStruct->WaitSetTime));
246 assert_param(IS_XFMC_NAND_HOLD_TIME(XFMC_NANDInitStruct->AttrSpaceTimingStruct->HoldSetTime));
247 assert_param(IS_XFMC_NAND_HIZ_TIME(XFMC_NANDInitStruct->AttrSpaceTimingStruct->HiZSetTime));
248
249 /* Set the tmppcr value according to XFMC_NANDInitStruct parameters */
250 tmppcr = XFMC_BANK23_MEM_TYPE_NAND
251 | XFMC_NANDInitStruct->WaitFeatureEnable
252 | XFMC_NANDInitStruct->MemDataWidth
253 | XFMC_NANDInitStruct->EccEnable
254 | XFMC_NANDInitStruct->EccPageSize
255 | XFMC_NANDInitStruct->TCLRSetTime
256 | XFMC_NANDInitStruct->TARSetTime;
257
258 /* Set tmppmem value according to XFMC_CommonSpaceTimingStructure parameters */
259 tmppmem = (XFMC_NANDInitStruct->CommSpaceTimingStruct->SetTime << XFMC_CMEMTM_SET_SHIFT)
260 | (XFMC_NANDInitStruct->CommSpaceTimingStruct->WaitSetTime << XFMC_CMEMTM_WAIT_SHIFT)
261 | (XFMC_NANDInitStruct->CommSpaceTimingStruct->HoldSetTime << XFMC_CMEMTM_HLD_SHIFT)
262 | (XFMC_NANDInitStruct->CommSpaceTimingStruct->HiZSetTime << XFMC_CMEMTM_HIZ_SHIFT);
263
264 /* Set tmppatt value according to XFMC_AttributeSpaceTimingStructure parameters */
265 tmppatt = (XFMC_NANDInitStruct->AttrSpaceTimingStruct->SetTime <<XFMC_ATTMEMTM_SET_SHIFT)
266 | (XFMC_NANDInitStruct->AttrSpaceTimingStruct->WaitSetTime << XFMC_ATTMEMTM_WAIT_SHIFT)
267 | (XFMC_NANDInitStruct->AttrSpaceTimingStruct->HoldSetTime << XFMC_ATTMEMTM_HLD_SHIFT)
268 | (XFMC_NANDInitStruct->AttrSpaceTimingStruct->HiZSetTime << XFMC_ATTMEMTM_HIZ_SHIFT);
269
270 XFMC_NANDInitStruct->Bank->CTRLx = tmppcr;
271 XFMC_NANDInitStruct->Bank->CMEMTMx = tmppmem;
272 XFMC_NANDInitStruct->Bank->ATTMEMTMx = tmppatt;
273 }
274
275 /**
276 * @brief Fills each XFMC_NORSRAMInitStruct member with its default value.
277 * @param XFMC_NORSRAMInitStruct pointer to a XFMC_NorSramInitTpye
278 * structure which will be initialized.
279 * @retval None
280 */
XFMC_InitNorSramStruct(XFMC_NorSramInitTpye * XFMC_NORSRAMInitStruct)281 void XFMC_InitNorSramStruct(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct)
282 {
283 /* Reset NOR/SRAM Init structure parameters values */
284 XFMC_NORSRAMInitStruct->Block = XFMC_BANK1_BLOCK1;
285 XFMC_NORSRAMInitStruct->DataAddrMux = XFMC_NOR_SRAM_MUX_ENABLE;
286 XFMC_NORSRAMInitStruct->MemType = XFMC_MEM_TYPE_SRAM;
287 XFMC_NORSRAMInitStruct->MemDataWidth = XFMC_NOR_SRAM_DATA_WIDTH_8B;
288 XFMC_NORSRAMInitStruct->BurstAccMode = XFMC_NOR_SRAM_BURST_MODE_DISABLE;
289 XFMC_NORSRAMInitStruct->AsynchroWait = XFMC_NOR_SRAM_ASYNC_NWAIT_DISABLE;
290 XFMC_NORSRAMInitStruct->WaitSigPolarity = XFMC_NOR_SRAM_WAIT_SIGNAL_LOW;
291 XFMC_NORSRAMInitStruct->WrapMode = XFMC_NOR_SRAM_WRAP_DISABLE;
292 XFMC_NORSRAMInitStruct->WaitSigConfig = XFMC_NOR_SRAM_NWAIT_BEFORE_STATE;
293 XFMC_NORSRAMInitStruct->WriteEnable = XFMC_NOR_SRAM_WRITE_ENABLE;
294 XFMC_NORSRAMInitStruct->WaitSigEnable = XFMC_NOR_SRAM_NWAIT_ENABLE;
295 XFMC_NORSRAMInitStruct->ExtModeEnable = XFMC_NOR_SRAM_EXTENDED_DISABLE;
296 XFMC_NORSRAMInitStruct->WriteBurstEnable = XFMC_NOR_SRAM_BURST_WRITE_DISABLE;
297 XFMC_NORSRAMInitStruct->RWTimingStruct->AddrSetTime = XFMC_NOR_SRAM_ADDR_SETUP_TIME_16HCLK;
298 XFMC_NORSRAMInitStruct->RWTimingStruct->AddrHoldTime = XFMC_NOR_SRAM_ADDR_HOLD_TIME_16HCLK;
299 XFMC_NORSRAMInitStruct->RWTimingStruct->DataSetTime = XFMC_NOR_SRAM_DATA_SETUP_TIME_MAX;
300 XFMC_NORSRAMInitStruct->RWTimingStruct->BusRecoveryCycle = XFMC_NOR_SRAM_BUSRECOVERY_TIME_16HCLK;
301 XFMC_NORSRAMInitStruct->RWTimingStruct->ClkDiv = XFMC_NOR_SRAM_CLK_DIV_16;
302 XFMC_NORSRAMInitStruct->RWTimingStruct->DataLatency = XFMC_NOR_SRAM_DATA_LATENCY_17CLK;
303 XFMC_NORSRAMInitStruct->RWTimingStruct->AccMode = XFMC_NOR_SRAM_ACC_MODE_A;
304 XFMC_NORSRAMInitStruct->WTimingStruct->AddrSetTime = XFMC_NOR_SRAM_ADDR_SETUP_TIME_16HCLK;
305 XFMC_NORSRAMInitStruct->WTimingStruct->AddrHoldTime = XFMC_NOR_SRAM_ADDR_HOLD_TIME_16HCLK;
306 XFMC_NORSRAMInitStruct->WTimingStruct->DataSetTime = XFMC_NOR_SRAM_DATA_SETUP_TIME_MAX;
307 XFMC_NORSRAMInitStruct->WTimingStruct->BusRecoveryCycle = XFMC_NOR_SRAM_BUSRECOVERY_TIME_16HCLK;
308 XFMC_NORSRAMInitStruct->WTimingStruct->ClkDiv = XFMC_NOR_SRAM_CLK_DIV_16;
309 XFMC_NORSRAMInitStruct->WTimingStruct->DataLatency = XFMC_NOR_SRAM_DATA_LATENCY_17CLK;
310 XFMC_NORSRAMInitStruct->WTimingStruct->AccMode = XFMC_NOR_SRAM_ACC_MODE_A;
311 }
312
313 /**
314 * @brief Fills each XFMC_NANDInitStruct member with its default value.
315 * @param XFMC_NANDInitStruct pointer to a XFMC_NandInitType
316 * structure which will be initialized.
317 * @retval None
318 */
XFMC_InitNandStruct(XFMC_NandInitType * XFMC_NANDInitStruct)319 void XFMC_InitNandStruct(XFMC_NandInitType* XFMC_NANDInitStruct)
320 {
321 /* Reset NAND Init structure parameters values */
322 XFMC_NANDInitStruct->Bank = XFMC_BANK2;
323 XFMC_NANDInitStruct->WaitFeatureEnable = XFMC_NAND_NWAIT_DISABLE;
324 XFMC_NANDInitStruct->MemDataWidth = XFMC_NAND_BUS_WIDTH_8B;
325 XFMC_NANDInitStruct->EccEnable = XFMC_NAND_ECC_DISABLE;
326 XFMC_NANDInitStruct->EccPageSize = XFMC_NAND_ECC_PAGE_256BYTES;
327 XFMC_NANDInitStruct->TCLRSetTime = XFMC_NAND_CLE_DELAY_1HCLK;
328 XFMC_NANDInitStruct->TARSetTime = XFMC_NAND_ALE_DELAY_1HCLK;
329 XFMC_NANDInitStruct->CommSpaceTimingStruct->SetTime = XFMC_NAND_SETUP_TIME_DEFAULT;
330 XFMC_NANDInitStruct->CommSpaceTimingStruct->WaitSetTime = XFMC_NAND_WAIT_TIME_DEFAULT;
331 XFMC_NANDInitStruct->CommSpaceTimingStruct->HoldSetTime = XFMC_NAND_HOLD_TIME_DEFAULT;
332 XFMC_NANDInitStruct->CommSpaceTimingStruct->HiZSetTime = XFMC_NAND_HIZ_TIME_DEFAULT;
333 XFMC_NANDInitStruct->AttrSpaceTimingStruct->SetTime = XFMC_NAND_SETUP_TIME_DEFAULT;
334 XFMC_NANDInitStruct->AttrSpaceTimingStruct->WaitSetTime = XFMC_NAND_WAIT_TIME_DEFAULT;
335 XFMC_NANDInitStruct->AttrSpaceTimingStruct->HoldSetTime = XFMC_NAND_HOLD_TIME_DEFAULT;
336 XFMC_NANDInitStruct->AttrSpaceTimingStruct->HiZSetTime = XFMC_NAND_HIZ_TIME_DEFAULT;
337 }
338
339 /**
340 * @brief Enables or disables the specified NOR/SRAM Memory Bank.
341 * @param Bank specifies the XFMC Bank to be used
342 * This parameter can be one of the following values:
343 * @arg XFMC_BANK1_BLOCK1 XFMC Bank1 NOR/SRAM block1
344 * @arg XFMC_BANK1_BLOCK2 XFMC Bank1 NOR/SRAM block2
345 * @param Cmd new state of the Bank. This parameter can be: ENABLE or DISABLE.
346 * @retval None
347 */
XFMC_EnableNorSram(XFMC_Bank1_Block * Block,FunctionalState Cmd)348 void XFMC_EnableNorSram(XFMC_Bank1_Block *Block, FunctionalState Cmd)
349 {
350 assert_param(IS_XFMC_NOR_SRAM_BLOCK(Block));
351 assert_param(IS_FUNCTIONAL_STATE(Cmd));
352
353 if (Cmd != DISABLE)
354 {
355 /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
356 Block->CRx |= XFMC_NOR_SRAM_ENABLE;
357 }
358 else
359 {
360 /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
361 Block->CRx &= ~XFMC_NOR_SRAM_ENABLE;
362 }
363 }
364
365 /**
366 * @brief Enables or disables the specified NAND Memory Bank.
367 * @param Bank specifies the XFMC Bank to be used
368 * This parameter can be one of the following values:
369 * @arg XFMC_BANK2 XFMC Bank2 NAND
370 * @arg XFMC_BANK3 XFMC Bank3 NAND
371 * @param Cmd new state of the Bank. This parameter can be: ENABLE or DISABLE.
372 * @retval None
373 */
XFMC_EnableNand(XFMC_Bank23_Module * Bank,FunctionalState Cmd)374 void XFMC_EnableNand(XFMC_Bank23_Module *Bank, FunctionalState Cmd)
375 {
376 assert_param(IS_XFMC_NAND_BANK(Bank));
377 assert_param(IS_FUNCTIONAL_STATE(Cmd));
378
379 if (Cmd != DISABLE)
380 {
381 /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
382 Bank->CTRLx |= XFMC_NAND_BANK_ENABLE;
383 }
384 else
385 {
386 /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
387 Bank->CTRLx &= ~XFMC_NAND_BANK_ENABLE;
388 }
389 }
390
391 /**
392 * @brief Enables or disables the XFMC NAND ECC feature.
393 * @param Bank specifies the XFMC Bank to be used
394 * This parameter can be one of the following values:
395 * @arg XFMC_BANK2 XFMC Bank2 NAND
396 * @arg XFMC_BANK3 XFMC Bank3 NAND
397 * @param Cmd new state of the XFMC NAND ECC feature.
398 * This parameter can be: ENABLE or DISABLE.
399 * @retval None
400 */
XFMC_EnableNandEcc(XFMC_Bank23_Module * Bank,FunctionalState Cmd)401 void XFMC_EnableNandEcc(XFMC_Bank23_Module *Bank, FunctionalState Cmd)
402 {
403 assert_param(IS_XFMC_NAND_BANK(Bank));
404 assert_param(IS_FUNCTIONAL_STATE(Cmd));
405
406 if (Cmd != DISABLE)
407 {
408 /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
409 Bank->CTRLx |= XFMC_NAND_ECC_ENABLE;
410 }
411 else
412 {
413 /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
414 Bank->CTRLx &= ~XFMC_NAND_ECC_ENABLE;
415 }
416 }
417
418 /**
419 * @brief Clear ECC result and start a new ECC process.
420 * @param Bank specifies the XFMC Bank to be used
421 * This parameter can be one of the following values:
422 * @arg XFMC_BANK2 XFMC Bank2 NAND
423 * @arg XFMC_BANK3 XFMC Bank3 NAND
424 * @retval None
425 */
XFMC_RestartNandEcc(XFMC_Bank23_Module * Bank)426 void XFMC_RestartNandEcc(XFMC_Bank23_Module *Bank)
427 {
428 Bank->CTRLx &= ~XFMC_NAND_ECC_ENABLE;
429 Bank->CTRLx |= XFMC_NAND_ECC_ENABLE;
430 }
431
432 /**
433 * @brief Returns the error correction code register value.
434 * @param Bank specifies the XFMC Bank to be used
435 * This parameter can be one of the following values:
436 * @arg XFMC_BANK2 XFMC Bank2 NAND
437 * @arg XFMC_BANK3 XFMC Bank3 NAND
438 * @retval The Error Correction Code (ECC) value.
439 */
XFMC_GetEcc(XFMC_Bank23_Module * Bank)440 uint32_t XFMC_GetEcc(XFMC_Bank23_Module *Bank)
441 {
442 uint32_t tEccPageSize,tECC = 0;
443
444 assert_param(IS_XFMC_NAND_BANK(Bank));
445
446 tEccPageSize = Bank->CTRLx & XFMC_CTRL_ECCPGS_MASK;
447
448 switch(tEccPageSize)
449 {
450 case XFMC_NAND_ECC_PAGE_256BYTES:
451 tECC = Bank->ECCx & XFMC_ECC_PAGE_256BYTE_MASK;
452 break;
453 case XFMC_NAND_ECC_PAGE_512BYTES:
454 tECC = Bank->ECCx & XFMC_ECC_PAGE_512BYTE_MASK;
455 break;
456 case XFMC_NAND_ECC_PAGE_1024BYTES:
457 tECC = Bank->ECCx & XFMC_ECC_PBAE_1024BYTE_MASK;
458 break;
459 case XFMC_NAND_ECC_PAGE_2048BYTES:
460 tECC = Bank->ECCx & XFMC_ECC_PBAE_2048BYTE_MASK;
461 break;
462 case XFMC_NAND_ECC_PAGE_4096BYTES:
463 tECC = Bank->ECCx & XFMC_ECC_PBAE_4096BYTE_MASK;
464 break;
465 case XFMC_NAND_ECC_PAGE_8192BYTES:
466 tECC = Bank->ECCx & XFMC_ECC_PBAE_8192BYTE_MASK;
467 break;
468 default:
469 break;
470 }
471
472 /* Return the error correction code value */
473 return (tECC);
474 }
475
476 /**
477 * @brief Checks whether the specified XFMC flag is set or not.
478 * @param Bank specifies the XFMC Bank to be used
479 * This parameter can be one of the following values:
480 * @arg XFMC_BANK2 XFMC Bank2 NAND
481 * @arg XFMC_BANK3 XFMC Bank3 NAND
482 * @param XFMC_FLAG specifies the flag to check.
483 * This parameter can be one of the following values:
484 * @arg XFMC_FLAG_FIFO_EMPTY Fifo empty Flag.
485 * @retval The new state of XFMC_FLAG (SET or RESET).
486 */
XFMC_GetFlag(XFMC_Bank23_Module * Bank,uint32_t XFMC_FLAG)487 FlagStatus XFMC_GetFlag(XFMC_Bank23_Module *Bank, uint32_t XFMC_FLAG)
488 {
489 FlagStatus bitstatus = RESET;
490
491 /* Check the parameters */
492 assert_param(IS_XFMC_NAND_BANK(Bank));
493 assert_param(IS_XFMC_NAND_FLAG(XFMC_FLAG));
494
495 /* Get the flag status */
496 if ((Bank->STSx & XFMC_FLAG) != (uint16_t)RESET)
497 {
498 bitstatus = SET;
499 }
500 else
501 {
502 bitstatus = RESET;
503 }
504 /* Return the flag status */
505 return bitstatus;
506 }
507
508 /**
509 * @brief Clears the XFMC's pending flags.
510 * @param Bank specifies the XFMC Bank to be used
511 * This parameter can be one of the following values:
512 * @arg XFMC_BANK2 XFMC Bank2 NAND
513 * @arg XFMC_BANK3 XFMC Bank3 NAND
514 * @param XFMC_FLAG specifies the flag to clear.
515 * This parameter can be one of the following values:
516 * @arg XFMC_FLAG_FIFO_EMPTY Fifo empty Flag.
517 * @retval None
518 */
XFMC_ClrFlag(XFMC_Bank23_Module * Bank,uint32_t XFMC_FLAG)519 void XFMC_ClrFlag(XFMC_Bank23_Module *Bank, uint32_t XFMC_FLAG)
520 {
521 /* Check the parameters */
522 assert_param(IS_XFMC_NAND_BANK(Bank));
523 assert_param(IS_XFMC_NAND_FLAG(XFMC_FLAG));
524
525 Bank->STSx &= ~XFMC_FLAG;
526 }
527
528 /**
529 * @}
530 */
531 /**
532 * @}
533 */
534 /**
535 * @}
536 */
537