1 /***************************************************************************** 2 * Copyright (c) 2019, Nations Technologies Inc. 3 * 4 * All rights reserved. 5 * **************************************************************************** 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * - Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the disclaimer below. 12 * 13 * Nations' name may not be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 19 * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 22 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 23 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 24 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 25 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * ****************************************************************************/ 27 28 /** 29 * @file n32g4fr_rcc.h 30 * @author Nations 31 * @version v1.0.3 32 * 33 * @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved. 34 */ 35 #ifndef __N32G4FR_RCC_H__ 36 #define __N32G4FR_RCC_H__ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include "n32g4fr.h" 43 44 /** @addtogroup N32G4FR_StdPeriph_Driver 45 * @{ 46 */ 47 48 /** @addtogroup RCC 49 * @{ 50 */ 51 52 /** @addtogroup RCC_Exported_Types 53 * @{ 54 */ 55 56 typedef struct 57 { 58 uint32_t SysclkFreq; /*!< returns SYSCLK clock frequency expressed in Hz */ 59 uint32_t HclkFreq; /*!< returns HCLK clock frequency expressed in Hz */ 60 uint32_t Pclk1Freq; /*!< returns PCLK1 clock frequency expressed in Hz */ 61 uint32_t Pclk2Freq; /*!< returns PCLK2 clock frequency expressed in Hz */ 62 uint32_t AdcPllClkFreq; /*!< returns ADCPLLCLK clock frequency expressed in Hz */ 63 uint32_t AdcHclkFreq; /*!< returns ADCHCLK clock frequency expressed in Hz */ 64 } RCC_ClocksType; 65 66 /** 67 * @} 68 */ 69 70 /** @addtogroup RCC_Exported_Constants 71 * @{ 72 */ 73 74 /** @addtogroup HSE_configuration 75 * @{ 76 */ 77 78 #define RCC_HSE_DISABLE ((uint32_t)0x00000000) 79 #define RCC_HSE_ENABLE ((uint32_t)0x00010000) 80 #define RCC_HSE_BYPASS ((uint32_t)0x00040000) 81 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_DISABLE) || ((HSE) == RCC_HSE_ENABLE) || ((HSE) == RCC_HSE_BYPASS)) 82 83 /** 84 * @} 85 */ 86 87 /** @addtogroup PLL_entry_clock_source 88 * @{ 89 */ 90 91 #define RCC_PLL_SRC_HSI_DIV2 ((uint32_t)0x00000000) 92 93 #define RCC_PLL_SRC_HSE_DIV1 ((uint32_t)0x00010000) 94 #define RCC_PLL_SRC_HSE_DIV2 ((uint32_t)0x00030000) 95 #define IS_RCC_PLL_SRC(SOURCE) \ 96 (((SOURCE) == RCC_PLL_SRC_HSI_DIV2) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV1) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV2)) 97 98 /** 99 * @} 100 */ 101 102 /** @addtogroup PLL_multiplication_factor 103 * @{ 104 */ 105 #define RCC_PLL_MUL_2 ((uint32_t)0x00000000) 106 #define RCC_PLL_MUL_3 ((uint32_t)0x00040000) 107 #define RCC_PLL_MUL_4 ((uint32_t)0x00080000) 108 #define RCC_PLL_MUL_5 ((uint32_t)0x000C0000) 109 #define RCC_PLL_MUL_6 ((uint32_t)0x00100000) 110 #define RCC_PLL_MUL_7 ((uint32_t)0x00140000) 111 #define RCC_PLL_MUL_8 ((uint32_t)0x00180000) 112 #define RCC_PLL_MUL_9 ((uint32_t)0x001C0000) 113 #define RCC_PLL_MUL_10 ((uint32_t)0x00200000) 114 #define RCC_PLL_MUL_11 ((uint32_t)0x00240000) 115 #define RCC_PLL_MUL_12 ((uint32_t)0x00280000) 116 #define RCC_PLL_MUL_13 ((uint32_t)0x002C0000) 117 #define RCC_PLL_MUL_14 ((uint32_t)0x00300000) 118 #define RCC_PLL_MUL_15 ((uint32_t)0x00340000) 119 #define RCC_PLL_MUL_16 ((uint32_t)0x00380000) 120 #define RCC_PLL_MUL_17 ((uint32_t)0x08000000) 121 #define RCC_PLL_MUL_18 ((uint32_t)0x08040000) 122 #define RCC_PLL_MUL_19 ((uint32_t)0x08080000) 123 #define RCC_PLL_MUL_20 ((uint32_t)0x080C0000) 124 #define RCC_PLL_MUL_21 ((uint32_t)0x08100000) 125 #define RCC_PLL_MUL_22 ((uint32_t)0x08140000) 126 #define RCC_PLL_MUL_23 ((uint32_t)0x08180000) 127 #define RCC_PLL_MUL_24 ((uint32_t)0x081C0000) 128 #define RCC_PLL_MUL_25 ((uint32_t)0x08200000) 129 #define RCC_PLL_MUL_26 ((uint32_t)0x08240000) 130 #define RCC_PLL_MUL_27 ((uint32_t)0x08280000) 131 #define RCC_PLL_MUL_28 ((uint32_t)0x082C0000) 132 #define RCC_PLL_MUL_29 ((uint32_t)0x08300000) 133 #define RCC_PLL_MUL_30 ((uint32_t)0x08340000) 134 #define RCC_PLL_MUL_31 ((uint32_t)0x08380000) 135 #define RCC_PLL_MUL_32 ((uint32_t)0x083C0000) 136 #define IS_RCC_PLL_MUL(MUL) \ 137 (((MUL) == RCC_PLL_MUL_2) || ((MUL) == RCC_PLL_MUL_3) || ((MUL) == RCC_PLL_MUL_4) || ((MUL) == RCC_PLL_MUL_5) \ 138 || ((MUL) == RCC_PLL_MUL_6) || ((MUL) == RCC_PLL_MUL_7) || ((MUL) == RCC_PLL_MUL_8) || ((MUL) == RCC_PLL_MUL_9) \ 139 || ((MUL) == RCC_PLL_MUL_10) || ((MUL) == RCC_PLL_MUL_11) || ((MUL) == RCC_PLL_MUL_12) \ 140 || ((MUL) == RCC_PLL_MUL_13) || ((MUL) == RCC_PLL_MUL_14) || ((MUL) == RCC_PLL_MUL_15) \ 141 || ((MUL) == RCC_PLL_MUL_16) || ((MUL) == RCC_PLL_MUL_17) || ((MUL) == RCC_PLL_MUL_18) \ 142 || ((MUL) == RCC_PLL_MUL_19) || ((MUL) == RCC_PLL_MUL_20) || ((MUL) == RCC_PLL_MUL_21) \ 143 || ((MUL) == RCC_PLL_MUL_22) || ((MUL) == RCC_PLL_MUL_23) || ((MUL) == RCC_PLL_MUL_24) \ 144 || ((MUL) == RCC_PLL_MUL_25) || ((MUL) == RCC_PLL_MUL_26) || ((MUL) == RCC_PLL_MUL_27) \ 145 || ((MUL) == RCC_PLL_MUL_28) || ((MUL) == RCC_PLL_MUL_29) || ((MUL) == RCC_PLL_MUL_30) \ 146 || ((MUL) == RCC_PLL_MUL_31) || ((MUL) == RCC_PLL_MUL_32)) 147 148 /** 149 * @} 150 */ 151 152 /** @addtogroup System_clock_source 153 * @{ 154 */ 155 156 #define RCC_SYSCLK_SRC_HSI ((uint32_t)0x00000000) 157 #define RCC_SYSCLK_SRC_HSE ((uint32_t)0x00000001) 158 #define RCC_SYSCLK_SRC_PLLCLK ((uint32_t)0x00000002) 159 #define IS_RCC_SYSCLK_SRC(SOURCE) \ 160 (((SOURCE) == RCC_SYSCLK_SRC_HSI) || ((SOURCE) == RCC_SYSCLK_SRC_HSE) || ((SOURCE) == RCC_SYSCLK_SRC_PLLCLK)) 161 /** 162 * @} 163 */ 164 165 /** @addtogroup AHB_clock_source 166 * @{ 167 */ 168 169 #define RCC_SYSCLK_DIV1 ((uint32_t)0x00000000) 170 #define RCC_SYSCLK_DIV2 ((uint32_t)0x00000080) 171 #define RCC_SYSCLK_DIV4 ((uint32_t)0x00000090) 172 #define RCC_SYSCLK_DIV8 ((uint32_t)0x000000A0) 173 #define RCC_SYSCLK_DIV16 ((uint32_t)0x000000B0) 174 #define RCC_SYSCLK_DIV64 ((uint32_t)0x000000C0) 175 #define RCC_SYSCLK_DIV128 ((uint32_t)0x000000D0) 176 #define RCC_SYSCLK_DIV256 ((uint32_t)0x000000E0) 177 #define RCC_SYSCLK_DIV512 ((uint32_t)0x000000F0) 178 #define IS_RCC_SYSCLK_DIV(HCLK) \ 179 (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) \ 180 || ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) \ 181 || ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512)) 182 /** 183 * @} 184 */ 185 186 /** @addtogroup APB1_APB2_clock_source 187 * @{ 188 */ 189 190 #define RCC_HCLK_DIV1 ((uint32_t)0x00000000) 191 #define RCC_HCLK_DIV2 ((uint32_t)0x00000400) 192 #define RCC_HCLK_DIV4 ((uint32_t)0x00000500) 193 #define RCC_HCLK_DIV8 ((uint32_t)0x00000600) 194 #define RCC_HCLK_DIV16 ((uint32_t)0x00000700) 195 #define IS_RCC_HCLK_DIV(PCLK) \ 196 (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) \ 197 || ((PCLK) == RCC_HCLK_DIV16)) 198 /** 199 * @} 200 */ 201 202 /** @addtogroup RCC_Interrupt_source 203 * @{ 204 */ 205 206 #define RCC_INT_LSIRDIF ((uint8_t)0x01) 207 #define RCC_INT_LSERDIF ((uint8_t)0x02) 208 #define RCC_INT_HSIRDIF ((uint8_t)0x04) 209 #define RCC_INT_HSERDIF ((uint8_t)0x08) 210 #define RCC_INT_PLLRDIF ((uint8_t)0x10) 211 #define RCC_INT_CLKSSIF ((uint8_t)0x80) 212 213 #define IS_RCC_INT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) 214 #define IS_RCC_GET_INT(IT) \ 215 (((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \ 216 || ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_CLKSSIF)) 217 #define IS_RCC_CLR_INT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) 218 219 /** 220 * @} 221 */ 222 223 /** @addtogroup USB_Device_clock_source 224 * @{ 225 */ 226 227 #define RCC_USBCLK_SRC_PLLCLK_DIV1_5 ((uint8_t)0x00) 228 #define RCC_USBCLK_SRC_PLLCLK_DIV1 ((uint8_t)0x01) 229 #define RCC_USBCLK_SRC_PLLCLK_DIV2 ((uint8_t)0x02) 230 #define RCC_USBCLK_SRC_PLLCLK_DIV3 ((uint8_t)0x03) 231 232 #define IS_RCC_USBCLK_SRC(SOURCE) \ 233 (((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1_5) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1) \ 234 || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV2) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV3)) 235 /** 236 * @} 237 */ 238 239 /** @addtogroup ADC_clock_source 240 * @{ 241 */ 242 243 #define RCC_PCLK2_DIV2 ((uint32_t)0x00000000) 244 #define RCC_PCLK2_DIV4 ((uint32_t)0x00004000) 245 #define RCC_PCLK2_DIV6 ((uint32_t)0x00008000) 246 #define RCC_PCLK2_DIV8 ((uint32_t)0x0000C000) 247 #define IS_RCC_PCLK2_DIV(ADCCLK) \ 248 (((ADCCLK) == RCC_PCLK2_DIV2) || ((ADCCLK) == RCC_PCLK2_DIV4) || ((ADCCLK) == RCC_PCLK2_DIV6) \ 249 || ((ADCCLK) == RCC_PCLK2_DIV8)) 250 251 /** 252 * @} 253 */ 254 255 /** @addtogroup RCC_CFGR2_Config 256 * @{ 257 */ 258 #define RCC_TIM18CLK_SRC_TIM18CLK ((uint32_t)0x00000000) 259 #define RCC_TIM18CLK_SRC_SYSCLK ((uint32_t)0x20000000) 260 #define IS_RCC_TIM18CLKSRC(TIM18CLK) \ 261 (((TIM18CLK) == RCC_TIM18CLK_SRC_TIM18CLK) || ((TIM18CLK) == RCC_TIM18CLK_SRC_SYSCLK)) 262 263 #define RCC_RNGCCLK_SYSCLK_DIV1 ((uint32_t)0x00000000) 264 #define RCC_RNGCCLK_SYSCLK_DIV2 ((uint32_t)0x01000000) 265 #define RCC_RNGCCLK_SYSCLK_DIV3 ((uint32_t)0x02000000) 266 #define RCC_RNGCCLK_SYSCLK_DIV4 ((uint32_t)0x03000000) 267 #define RCC_RNGCCLK_SYSCLK_DIV5 ((uint32_t)0x04000000) 268 #define RCC_RNGCCLK_SYSCLK_DIV6 ((uint32_t)0x05000000) 269 #define RCC_RNGCCLK_SYSCLK_DIV7 ((uint32_t)0x06000000) 270 #define RCC_RNGCCLK_SYSCLK_DIV8 ((uint32_t)0x07000000) 271 #define RCC_RNGCCLK_SYSCLK_DIV9 ((uint32_t)0x08000000) 272 #define RCC_RNGCCLK_SYSCLK_DIV10 ((uint32_t)0x09000000) 273 #define RCC_RNGCCLK_SYSCLK_DIV11 ((uint32_t)0x0A000000) 274 #define RCC_RNGCCLK_SYSCLK_DIV12 ((uint32_t)0x0B000000) 275 #define RCC_RNGCCLK_SYSCLK_DIV13 ((uint32_t)0x0C000000) 276 #define RCC_RNGCCLK_SYSCLK_DIV14 ((uint32_t)0x0D000000) 277 #define RCC_RNGCCLK_SYSCLK_DIV15 ((uint32_t)0x0E000000) 278 #define RCC_RNGCCLK_SYSCLK_DIV16 ((uint32_t)0x0F000000) 279 #define RCC_RNGCCLK_SYSCLK_DIV17 ((uint32_t)0x10000000) 280 #define RCC_RNGCCLK_SYSCLK_DIV18 ((uint32_t)0x11000000) 281 #define RCC_RNGCCLK_SYSCLK_DIV19 ((uint32_t)0x12000000) 282 #define RCC_RNGCCLK_SYSCLK_DIV20 ((uint32_t)0x13000000) 283 #define RCC_RNGCCLK_SYSCLK_DIV21 ((uint32_t)0x14000000) 284 #define RCC_RNGCCLK_SYSCLK_DIV22 ((uint32_t)0x15000000) 285 #define RCC_RNGCCLK_SYSCLK_DIV23 ((uint32_t)0x16000000) 286 #define RCC_RNGCCLK_SYSCLK_DIV24 ((uint32_t)0x17000000) 287 #define RCC_RNGCCLK_SYSCLK_DIV25 ((uint32_t)0x18000000) 288 #define RCC_RNGCCLK_SYSCLK_DIV26 ((uint32_t)0x19000000) 289 #define RCC_RNGCCLK_SYSCLK_DIV27 ((uint32_t)0x1A000000) 290 #define RCC_RNGCCLK_SYSCLK_DIV28 ((uint32_t)0x1B000000) 291 #define RCC_RNGCCLK_SYSCLK_DIV29 ((uint32_t)0x1C000000) 292 #define RCC_RNGCCLK_SYSCLK_DIV30 ((uint32_t)0x1D000000) 293 #define RCC_RNGCCLK_SYSCLK_DIV31 ((uint32_t)0x1E000000) 294 #define RCC_RNGCCLK_SYSCLK_DIV32 ((uint32_t)0x1F000000) 295 #define IS_RCC_RNGCCLKPRE(DIV) \ 296 (((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV3) \ 297 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV6) \ 298 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV9) \ 299 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV10) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV11) \ 300 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV12) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV13) \ 301 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV14) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV15) \ 302 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV16) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV17) \ 303 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV18) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV19) \ 304 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV20) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV21) \ 305 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV22) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV23) \ 306 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV24) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV25) \ 307 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV26) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV27) \ 308 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV28) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV29) \ 309 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV30) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV31) \ 310 || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV32)) 311 312 #define RCC_ADC1MCLK_SRC_HSI ((uint32_t)0x00000000) 313 #define RCC_ADC1MCLK_SRC_HSE ((uint32_t)0x00000400) 314 #define IS_RCC_ADC1MCLKSRC(ADC1MCLK) (((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSI) || ((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSE)) 315 316 #define RCC_ADC1MCLK_DIV1 ((uint32_t)0x00000000) 317 #define RCC_ADC1MCLK_DIV2 ((uint32_t)0x00000800) 318 #define RCC_ADC1MCLK_DIV3 ((uint32_t)0x00001000) 319 #define RCC_ADC1MCLK_DIV4 ((uint32_t)0x00001800) 320 #define RCC_ADC1MCLK_DIV5 ((uint32_t)0x00002000) 321 #define RCC_ADC1MCLK_DIV6 ((uint32_t)0x00002800) 322 #define RCC_ADC1MCLK_DIV7 ((uint32_t)0x00003000) 323 #define RCC_ADC1MCLK_DIV8 ((uint32_t)0x00003800) 324 #define RCC_ADC1MCLK_DIV9 ((uint32_t)0x00004000) 325 #define RCC_ADC1MCLK_DIV10 ((uint32_t)0x00004800) 326 #define RCC_ADC1MCLK_DIV11 ((uint32_t)0x00005000) 327 #define RCC_ADC1MCLK_DIV12 ((uint32_t)0x00005800) 328 #define RCC_ADC1MCLK_DIV13 ((uint32_t)0x00006000) 329 #define RCC_ADC1MCLK_DIV14 ((uint32_t)0x00006800) 330 #define RCC_ADC1MCLK_DIV15 ((uint32_t)0x00007000) 331 #define RCC_ADC1MCLK_DIV16 ((uint32_t)0x00007800) 332 #define RCC_ADC1MCLK_DIV17 ((uint32_t)0x00008000) 333 #define RCC_ADC1MCLK_DIV18 ((uint32_t)0x00008800) 334 #define RCC_ADC1MCLK_DIV19 ((uint32_t)0x00009000) 335 #define RCC_ADC1MCLK_DIV20 ((uint32_t)0x00009800) 336 #define RCC_ADC1MCLK_DIV21 ((uint32_t)0x0000A000) 337 #define RCC_ADC1MCLK_DIV22 ((uint32_t)0x0000A800) 338 #define RCC_ADC1MCLK_DIV23 ((uint32_t)0x0000B000) 339 #define RCC_ADC1MCLK_DIV24 ((uint32_t)0x0000B800) 340 #define RCC_ADC1MCLK_DIV25 ((uint32_t)0x0000C000) 341 #define RCC_ADC1MCLK_DIV26 ((uint32_t)0x0000C800) 342 #define RCC_ADC1MCLK_DIV27 ((uint32_t)0x0000D000) 343 #define RCC_ADC1MCLK_DIV28 ((uint32_t)0x0000D800) 344 #define RCC_ADC1MCLK_DIV29 ((uint32_t)0x0000E000) 345 #define RCC_ADC1MCLK_DIV30 ((uint32_t)0x0000E800) 346 #define RCC_ADC1MCLK_DIV31 ((uint32_t)0x0000F000) 347 #define RCC_ADC1MCLK_DIV32 ((uint32_t)0x0000F800) 348 #define IS_RCC_ADC1MCLKPRE(DIV) \ 349 (((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) \ 350 || ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) \ 351 || ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) \ 352 || ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12) \ 353 || ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15) \ 354 || ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18) \ 355 || ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21) \ 356 || ((DIV) == RCC_ADC1MCLK_DIV22) || ((DIV) == RCC_ADC1MCLK_DIV23) || ((DIV) == RCC_ADC1MCLK_DIV24) \ 357 || ((DIV) == RCC_ADC1MCLK_DIV25) || ((DIV) == RCC_ADC1MCLK_DIV26) || ((DIV) == RCC_ADC1MCLK_DIV27) \ 358 || ((DIV) == RCC_ADC1MCLK_DIV28) || ((DIV) == RCC_ADC1MCLK_DIV29) || ((DIV) == RCC_ADC1MCLK_DIV30) \ 359 || ((DIV) == RCC_ADC1MCLK_DIV31) || ((DIV) == RCC_ADC1MCLK_DIV32)) 360 361 #define RCC_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF) 362 #define RCC_ADCPLLCLK_DIV1 ((uint32_t)0x00000100) 363 #define RCC_ADCPLLCLK_DIV2 ((uint32_t)0x00000110) 364 #define RCC_ADCPLLCLK_DIV4 ((uint32_t)0x00000120) 365 #define RCC_ADCPLLCLK_DIV6 ((uint32_t)0x00000130) 366 #define RCC_ADCPLLCLK_DIV8 ((uint32_t)0x00000140) 367 #define RCC_ADCPLLCLK_DIV10 ((uint32_t)0x00000150) 368 #define RCC_ADCPLLCLK_DIV12 ((uint32_t)0x00000160) 369 #define RCC_ADCPLLCLK_DIV16 ((uint32_t)0x00000170) 370 #define RCC_ADCPLLCLK_DIV32 ((uint32_t)0x00000180) 371 #define RCC_ADCPLLCLK_DIV64 ((uint32_t)0x00000190) 372 #define RCC_ADCPLLCLK_DIV128 ((uint32_t)0x000001A0) 373 #define RCC_ADCPLLCLK_DIV256 ((uint32_t)0x000001B0) 374 #define RCC_ADCPLLCLK_DIV_OTHERS ((uint32_t)0x000001C0) 375 #define IS_RCC_ADCPLLCLKPRE(DIV) \ 376 (((DIV) == RCC_ADCPLLCLK_DIV1) || ((DIV) == RCC_ADCPLLCLK_DIV2) || ((DIV) == RCC_ADCPLLCLK_DIV4) \ 377 || ((DIV) == RCC_ADCPLLCLK_DIV6) || ((DIV) == RCC_ADCPLLCLK_DIV8) || ((DIV) == RCC_ADCPLLCLK_DIV10) \ 378 || ((DIV) == RCC_ADCPLLCLK_DIV12) || ((DIV) == RCC_ADCPLLCLK_DIV16) || ((DIV) == RCC_ADCPLLCLK_DIV32) \ 379 || ((DIV) == RCC_ADCPLLCLK_DIV64) || ((DIV) == RCC_ADCPLLCLK_DIV128) || ((DIV) == RCC_ADCPLLCLK_DIV256) \ 380 || ((DIV) == RCC_ADC1MCLK_DIV15) || ((DIV) == RCC_ADCPLLCLK_DIV16) \ 381 || (((DIV)&RCC_ADCPLLCLK_DIV_OTHERS) == 0x000001C0)) 382 383 #define RCC_ADCHCLK_DIV1 ((uint32_t)0x00000000) 384 #define RCC_ADCHCLK_DIV2 ((uint32_t)0x00000001) 385 #define RCC_ADCHCLK_DIV4 ((uint32_t)0x00000002) 386 #define RCC_ADCHCLK_DIV6 ((uint32_t)0x00000003) 387 #define RCC_ADCHCLK_DIV8 ((uint32_t)0x00000004) 388 #define RCC_ADCHCLK_DIV10 ((uint32_t)0x00000005) 389 #define RCC_ADCHCLK_DIV12 ((uint32_t)0x00000006) 390 #define RCC_ADCHCLK_DIV16 ((uint32_t)0x00000007) 391 #define RCC_ADCHCLK_DIV32 ((uint32_t)0x00000008) 392 #define RCC_ADCHCLK_DIV_OTHERS ((uint32_t)0x00000008) 393 #define IS_RCC_ADCHCLKPRE(DIV) \ 394 (((DIV) == RCC_ADCHCLK_DIV1) || ((DIV) == RCC_ADCHCLK_DIV2) || ((DIV) == RCC_ADCHCLK_DIV4) \ 395 || ((DIV) == RCC_ADCHCLK_DIV6) || ((DIV) == RCC_ADCHCLK_DIV8) || ((DIV) == RCC_ADCHCLK_DIV10) \ 396 || ((DIV) == RCC_ADCHCLK_DIV12) || ((DIV) == RCC_ADCHCLK_DIV16) || ((DIV) == RCC_ADCHCLK_DIV32) \ 397 || (((DIV)&RCC_ADCHCLK_DIV_OTHERS) != 0x00)) 398 /** 399 * @} 400 */ 401 402 /** @addtogroup RCC_CFGR3_Config 403 * @{ 404 */ 405 #define RCC_BOR_RST_ENABLE ((uint32_t)0x00000040) 406 407 #define RCC_TRNG1MCLK_ENABLE ((uint32_t)0x00040000) 408 #define RCC_TRNG1MCLK_DISABLE ((uint32_t)0xFFFBFFFF) 409 410 #define RCC_TRNG1MCLK_SRC_HSI ((uint32_t)0x00000000) 411 #define RCC_TRNG1MCLK_SRC_HSE ((uint32_t)0x00020000) 412 #define IS_RCC_TRNG1MCLK_SRC(TRNG1MCLK) \ 413 (((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSI) || ((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSE)) 414 415 #define RCC_TRNG1MCLK_DIV2 ((uint32_t)0x00000800) 416 #define RCC_TRNG1MCLK_DIV4 ((uint32_t)0x00001800) 417 #define RCC_TRNG1MCLK_DIV6 ((uint32_t)0x00002800) 418 #define RCC_TRNG1MCLK_DIV8 ((uint32_t)0x00003800) 419 #define RCC_TRNG1MCLK_DIV10 ((uint32_t)0x00004800) 420 #define RCC_TRNG1MCLK_DIV12 ((uint32_t)0x00005800) 421 #define RCC_TRNG1MCLK_DIV14 ((uint32_t)0x00006800) 422 #define RCC_TRNG1MCLK_DIV16 ((uint32_t)0x00007800) 423 #define RCC_TRNG1MCLK_DIV18 ((uint32_t)0x00008800) 424 #define RCC_TRNG1MCLK_DIV20 ((uint32_t)0x00009800) 425 #define RCC_TRNG1MCLK_DIV22 ((uint32_t)0x0000A800) 426 #define RCC_TRNG1MCLK_DIV24 ((uint32_t)0x0000B800) 427 #define RCC_TRNG1MCLK_DIV26 ((uint32_t)0x0000C800) 428 #define RCC_TRNG1MCLK_DIV28 ((uint32_t)0x0000D800) 429 #define RCC_TRNG1MCLK_DIV30 ((uint32_t)0x0000E800) 430 #define RCC_TRNG1MCLK_DIV32 ((uint32_t)0x0000F800) 431 #define IS_RCC_TRNG1MCLKPRE(VAL) \ 432 (((VAL) == RCC_TRNG1MCLK_DIV2) || ((VAL) == RCC_TRNG1MCLK_DIV4) || ((VAL) == RCC_TRNG1MCLK_DIV6) \ 433 || ((VAL) == RCC_TRNG1MCLK_DIV8) || ((VAL) == RCC_TRNG1MCLK_DIV10) || ((VAL) == RCC_TRNG1MCLK_DIV12) \ 434 || ((VAL) == RCC_TRNG1MCLK_DIV14) || ((VAL) == RCC_TRNG1MCLK_DIV16) || ((VAL) == RCC_TRNG1MCLK_DIV18) \ 435 || ((VAL) == RCC_TRNG1MCLK_DIV20) || ((VAL) == RCC_TRNG1MCLK_DIV22) || ((VAL) == RCC_TRNG1MCLK_DIV24) \ 436 || ((VAL) == RCC_TRNG1MCLK_DIV26) || ((VAL) == RCC_TRNG1MCLK_DIV28) || ((VAL) == RCC_TRNG1MCLK_DIV30) \ 437 || ((VAL) == RCC_TRNG1MCLK_DIV32)) 438 439 /** 440 * @} 441 */ 442 443 /** @addtogroup LSE_configuration 444 * @{ 445 */ 446 447 #define RCC_LSE_DISABLE ((uint8_t)0x00) 448 #define RCC_LSE_ENABLE ((uint8_t)0x01) 449 #define RCC_LSE_BYPASS ((uint8_t)0x04) 450 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_DISABLE) || ((LSE) == RCC_LSE_ENABLE) || ((LSE) == RCC_LSE_BYPASS)) 451 /** 452 * @} 453 */ 454 455 /** @addtogroup RTC_clock_source 456 * @{ 457 */ 458 459 #define RCC_RTCCLK_SRC_LSE ((uint32_t)0x00000100) 460 #define RCC_RTCCLK_SRC_LSI ((uint32_t)0x00000200) 461 #define RCC_RTCCLK_SRC_HSE_DIV128 ((uint32_t)0x00000300) 462 #define IS_RCC_RTCCLK_SRC(SOURCE) \ 463 (((SOURCE) == RCC_RTCCLK_SRC_LSE) || ((SOURCE) == RCC_RTCCLK_SRC_LSI) || ((SOURCE) == RCC_RTCCLK_SRC_HSE_DIV128)) 464 /** 465 * @} 466 */ 467 468 /** @addtogroup AHB_peripheral 469 * @{ 470 */ 471 472 #define RCC_AHB_PERIPH_DMA1 ((uint32_t)0x00000001) 473 #define RCC_AHB_PERIPH_DMA2 ((uint32_t)0x00000002) 474 #define RCC_AHB_PERIPH_SRAM ((uint32_t)0x00000004) 475 #define RCC_AHB_PERIPH_FLITF ((uint32_t)0x00000010) 476 #define RCC_AHB_PERIPH_CRC ((uint32_t)0x00000040) 477 #define RCC_AHB_PERIPH_RNGC ((uint32_t)0x00000200) 478 #define RCC_AHB_PERIPH_SDIO ((uint32_t)0x00000400) 479 #define RCC_AHB_PERIPH_SAC ((uint32_t)0x00000800) 480 #define RCC_AHB_PERIPH_ADC1 ((uint32_t)0x00001000) 481 #define RCC_AHB_PERIPH_ADC2 ((uint32_t)0x00002000) 482 #define RCC_AHB_PERIPH_ADC3 ((uint32_t)0x00004000) 483 #define RCC_AHB_PERIPH_ADC4 ((uint32_t)0x00008000) 484 #define RCC_AHB_PERIPH_ETHMAC ((uint32_t)0x00010000) 485 #define RCC_AHB_PERIPH_QSPI ((uint32_t)0x00020000) 486 487 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH)&0xFFFC02A8) == 0x00) && ((PERIPH) != 0x00)) 488 489 /** 490 * @} 491 */ 492 493 /** @addtogroup APB2_peripheral 494 * @{ 495 */ 496 497 #define RCC_APB2_PERIPH_AFIO ((uint32_t)0x00000001) 498 #define RCC_APB2_PERIPH_GPIOA ((uint32_t)0x00000004) 499 #define RCC_APB2_PERIPH_GPIOB ((uint32_t)0x00000008) 500 #define RCC_APB2_PERIPH_GPIOC ((uint32_t)0x00000010) 501 #define RCC_APB2_PERIPH_GPIOD ((uint32_t)0x00000020) 502 #define RCC_APB2_PERIPH_GPIOE ((uint32_t)0x00000040) 503 #define RCC_APB2_PERIPH_TIM1 ((uint32_t)0x00000800) 504 #define RCC_APB2_PERIPH_SPI1 ((uint32_t)0x00001000) 505 #define RCC_APB2_PERIPH_TIM8 ((uint32_t)0x00002000) 506 #define RCC_APB2_PERIPH_USART1 ((uint32_t)0x00004000) 507 #define RCC_APB2_PERIPH_DVP ((uint32_t)0x00010000) 508 #define RCC_APB2_PERIPH_UART6 ((uint32_t)0x00020000) 509 #define RCC_APB2_PERIPH_UART7 ((uint32_t)0x00040000) 510 #define RCC_APB2_PERIPH_I2C3 ((uint32_t)0x00080000) 511 #define RCC_APB2_PERIPH_I2C4 ((uint32_t)0x00100000) 512 513 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH)&0xFFE08602) == 0x00) && ((PERIPH) != 0x00)) 514 /** 515 * @} 516 */ 517 518 /** @addtogroup APB1_peripheral 519 * @{ 520 */ 521 522 #define RCC_APB1_PERIPH_TIM2 ((uint32_t)0x00000001) 523 #define RCC_APB1_PERIPH_TIM3 ((uint32_t)0x00000002) 524 #define RCC_APB1_PERIPH_TIM4 ((uint32_t)0x00000004) 525 #define RCC_APB1_PERIPH_TIM5 ((uint32_t)0x00000008) 526 #define RCC_APB1_PERIPH_TIM6 ((uint32_t)0x00000010) 527 #define RCC_APB1_PERIPH_TIM7 ((uint32_t)0x00000020) 528 #define RCC_APB1_PERIPH_COMP ((uint32_t)0x00000040) 529 #define RCC_APB1_PERIPH_COMP_FILT ((uint32_t)0x00000080) 530 #define RCC_APB1_PERIPH_TSC ((uint32_t)0x00000400) 531 #define RCC_APB1_PERIPH_WWDG ((uint32_t)0x00000800) 532 #define RCC_APB1_PERIPH_SPI2 ((uint32_t)0x00004000) 533 #define RCC_APB1_PERIPH_SPI3 ((uint32_t)0x00008000) 534 #define RCC_APB1_PERIPH_USART2 ((uint32_t)0x00020000) 535 #define RCC_APB1_PERIPH_USART3 ((uint32_t)0x00040000) 536 #define RCC_APB1_PERIPH_UART4 ((uint32_t)0x00080000) 537 #define RCC_APB1_PERIPH_UART5 ((uint32_t)0x00100000) 538 #define RCC_APB1_PERIPH_I2C1 ((uint32_t)0x00200000) 539 #define RCC_APB1_PERIPH_I2C2 ((uint32_t)0x00400000) 540 #define RCC_APB1_PERIPH_USB ((uint32_t)0x00800000) 541 #define RCC_APB1_PERIPH_CAN1 ((uint32_t)0x02000000) 542 #define RCC_APB1_PERIPH_CAN2 ((uint32_t)0x04000000) 543 #define RCC_APB1_PERIPH_BKP ((uint32_t)0x08000000) 544 #define RCC_APB1_PERIPH_PWR ((uint32_t)0x10000000) 545 #define RCC_APB1_PERIPH_DAC ((uint32_t)0x20000000) 546 #define RCC_APB1_PERIPH_OPAMP ((uint32_t)0x80000000) 547 548 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH)&0x41013300) == 0x00) && ((PERIPH) != 0x00)) 549 550 /** 551 * @} 552 */ 553 554 #define RCC_MCO_PLLCLK_DIV2 ((uint32_t)0x20000000) 555 #define RCC_MCO_PLLCLK_DIV3 ((uint32_t)0x30000000) 556 #define RCC_MCO_PLLCLK_DIV4 ((uint32_t)0x40000000) 557 #define RCC_MCO_PLLCLK_DIV5 ((uint32_t)0x50000000) 558 #define RCC_MCO_PLLCLK_DIV6 ((uint32_t)0x60000000) 559 #define RCC_MCO_PLLCLK_DIV7 ((uint32_t)0x70000000) 560 #define RCC_MCO_PLLCLK_DIV8 ((uint32_t)0x80000000) 561 #define RCC_MCO_PLLCLK_DIV9 ((uint32_t)0x90000000) 562 #define RCC_MCO_PLLCLK_DIV10 ((uint32_t)0xA0000000) 563 #define RCC_MCO_PLLCLK_DIV11 ((uint32_t)0xB0000000) 564 #define RCC_MCO_PLLCLK_DIV12 ((uint32_t)0xC0000000) 565 #define RCC_MCO_PLLCLK_DIV13 ((uint32_t)0xD0000000) 566 #define RCC_MCO_PLLCLK_DIV14 ((uint32_t)0xE0000000) 567 #define RCC_MCO_PLLCLK_DIV15 ((uint32_t)0xF0000000) 568 #define IS_RCC_MCOPLLCLKPRE(DIV) \ 569 (((DIV) == RCC_MCO_PLLCLK_DIV2) || ((DIV) == RCC_MCO_PLLCLK_DIV3) || ((DIV) == RCC_MCO_PLLCLK_DIV4) \ 570 || ((DIV) == RCC_MCO_PLLCLK_DIV5) || ((DIV) == RCC_MCO_PLLCLK_DIV6) || ((DIV) == RCC_MCO_PLLCLK_DIV7) \ 571 || ((DIV) == RCC_MCO_PLLCLK_DIV8) || ((DIV) == RCC_MCO_PLLCLK_DIV9) || ((DIV) == RCC_MCO_PLLCLK_DIV10) \ 572 || ((DIV) == RCC_MCO_PLLCLK_DIV11) || ((DIV) == RCC_MCO_PLLCLK_DIV12) || ((DIV) == RCC_MCO_PLLCLK_DIV13) \ 573 || ((DIV) == RCC_MCO_PLLCLK_DIV14) || ((DIV) == RCC_MCO_PLLCLK_DIV15)) 574 575 /** @addtogroup Clock_source_to_output_on_MCO_pin 576 * @{ 577 */ 578 579 #define RCC_MCO_NOCLK ((uint8_t)0x00) 580 #define RCC_MCO_SYSCLK ((uint8_t)0x04) 581 #define RCC_MCO_HSI ((uint8_t)0x05) 582 #define RCC_MCO_HSE ((uint8_t)0x06) 583 #define RCC_MCO_PLLCLK ((uint8_t)0x07) 584 585 #define IS_RCC_MCO(MCO) \ 586 (((MCO) == RCC_MCO_NOCLK) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) \ 587 || ((MCO) == RCC_MCO_PLLCLK)) 588 589 /** 590 * @} 591 */ 592 593 /** @addtogroup RCC_Flag 594 * @{ 595 */ 596 #define RCC_FLAG_HSIRD ((uint8_t)0x21) 597 #define RCC_FLAG_HSERD ((uint8_t)0x31) 598 #define RCC_FLAG_PLLRD ((uint8_t)0x39) 599 #define RCC_FLAG_LSERD ((uint8_t)0x41) 600 #define RCC_FLAG_LSIRD ((uint8_t)0x61) 601 #define RCC_FLAG_BORRST ((uint8_t)0x73) 602 #define RCC_FLAG_RETEMC ((uint8_t)0x74) 603 #define RCC_FLAG_BKPEMC ((uint8_t)0x75) 604 #define RCC_FLAG_RAMRST ((uint8_t)0x77) 605 #define RCC_FLAG_MMURST ((uint8_t)0x79) 606 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 607 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 608 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 609 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 610 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 611 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 612 613 #define IS_RCC_FLAG(FLAG) \ 614 (((FLAG) == RCC_FLAG_HSIRD) || ((FLAG) == RCC_FLAG_HSERD) || ((FLAG) == RCC_FLAG_PLLRD) \ 615 || ((FLAG) == RCC_FLAG_LSERD) || ((FLAG) == RCC_FLAG_LSIRD) || ((FLAG) == RCC_FLAG_BORRST) \ 616 || ((FLAG) == RCC_FLAG_RETEMC) || ((FLAG) == RCC_FLAG_BKPEMC) || ((FLAG) == RCC_FLAG_RAMRST) \ 617 || ((FLAG) == RCC_FLAG_MMURST) || ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) \ 618 || ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST) || ((FLAG) == RCC_FLAG_WWDGRST) \ 619 || ((FLAG) == RCC_FLAG_LPWRRST)) 620 621 #define IS_RCC_CALIB_VALUE(VALUE) ((VALUE) <= 0x1F) 622 /** 623 * @} 624 */ 625 626 /** 627 * @} 628 */ 629 630 /** @addtogroup RCC_Exported_Macros 631 * @{ 632 */ 633 634 /** 635 * @} 636 */ 637 638 /** @addtogroup RCC_Exported_Functions 639 * @{ 640 */ 641 642 void RCC_DeInit(void); 643 void RCC_ConfigHse(uint32_t RCC_HSE); 644 ErrorStatus RCC_WaitHseStable(void); 645 void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue); 646 void RCC_EnableHsi(FunctionalState Cmd); 647 void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); 648 void RCC_EnablePll(FunctionalState Cmd); 649 650 void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource); 651 uint8_t RCC_GetSysclkSrc(void); 652 void RCC_ConfigHclk(uint32_t RCC_SYSCLK); 653 void RCC_ConfigPclk1(uint32_t RCC_HCLK); 654 void RCC_ConfigPclk2(uint32_t RCC_HCLK); 655 void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd); 656 657 void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource); 658 659 void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource); 660 void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler); 661 662 void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler); 663 void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd); 664 void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler); 665 666 void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler); 667 void RCC_EnableTrng1mClk(FunctionalState Cmd); 668 669 void RCC_ConfigLse(uint8_t RCC_LSE); 670 void RCC_EnableLsi(FunctionalState Cmd); 671 void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource); 672 void RCC_EnableRtcClk(FunctionalState Cmd); 673 void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks); 674 void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd); 675 void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd); 676 void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd); 677 678 void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd); 679 void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd); 680 void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd); 681 void RCC_EnableBORReset(FunctionalState Cmd); 682 void RCC_EnableBackupReset(FunctionalState Cmd); 683 void RCC_EnableClockSecuritySystem(FunctionalState Cmd); 684 void RCC_ConfigMcoPllClk(uint32_t RCC_MCOPLLCLKPrescaler); 685 void RCC_ConfigMco(uint8_t RCC_MCO); 686 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 687 void RCC_ClrFlag(void); 688 INTStatus RCC_GetIntStatus(uint8_t RccInt); 689 void RCC_ClrIntPendingBit(uint8_t RccInt); 690 691 #ifdef __cplusplus 692 } 693 #endif 694 695 #endif /* __N32G4FR_RCC_H__ */ 696 /** 697 * @} 698 */ 699 700 /** 701 * @} 702 */ 703 704 /** 705 * @} 706 */ 707