1 /***************************************************************************** 2 * Copyright (c) 2022, Nations Technologies Inc. 3 * 4 * All rights reserved. 5 * **************************************************************************** 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * - Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the disclaimer below. 12 * 13 * Nations' name may not be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 19 * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 22 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 23 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 24 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 25 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * ****************************************************************************/ 27 28 /** 29 * @file n32l40x_pwr.h 30 * @author Nations 31 * @version v1.2.0 32 * 33 * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. 34 */ 35 #ifndef __N32L40X_PWR_H__ 36 #define __N32L40X_PWR_H__ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include "n32l40x.h" 43 44 /** @addtogroup n32l40x_StdPeriph_Driver 45 * @{ 46 */ 47 48 /** @addtogroup PWR 49 * @{ 50 */ 51 52 /** @addtogroup PWR_Exported_Types 53 * @{ 54 */ 55 56 /** 57 * @} 58 */ 59 60 /** @addtogroup PWR_Exported_Constants 61 * @{ 62 */ 63 64 /** @addtogroup PVD_detection_level 65 * @{ 66 */ 67 68 #define PWR_PVDLEVEL_2V1 ((uint32_t)0x00000000) 69 #define PWR_PVDLEVEL_2V25 ((uint32_t)0x0000002) 70 #define PWR_PVDLEVEL_2V4 ((uint32_t)0x0000004) 71 #define PWR_PVDLEVEL_2V55 ((uint32_t)0x0000006) 72 #define PWR_PVDLEVEL_2V7 ((uint32_t)0x0000008) 73 #define PWR_PVDLEVEL_2V85 ((uint32_t)0x000000A) 74 #define PWR_PVDLEVEL_2V95 ((uint32_t)0x000000C) 75 #define PWR_PVDLEVEL_IN ((uint32_t)0x000000E) 76 77 78 #define IS_PWR_PVD_LEVEL(LEVEL) \ 79 (((LEVEL) == PWR_PVDLEVEL_2V1) || ((LEVEL) == PWR_PVDLEVEL_2V25) || ((LEVEL) == PWR_PVDLEVEL_2V4) \ 80 || ((LEVEL) == PWR_PVDLEVEL_2V55) || ((LEVEL) == PWR_PVDLEVEL_2V7) || ((LEVEL) == PWR_PVDLEVEL_2V85) \ 81 || ((LEVEL) == PWR_PVDLEVEL_2V95) || ((LEVEL) == PWR_PVDLEVEL_IN) ) 82 83 /** 84 * @} 85 */ 86 87 /** @addtogroup Regulator_state_is_STOP_mode 88 * @{ 89 */ 90 91 #define PWR_REGULATOR_ON ((uint32_t)0x00000000) 92 #define PWR_REGULATOR_LOWPOWER ((uint32_t)0x00000001) 93 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_REGULATOR_ON) || ((REGULATOR) == PWR_REGULATOR_LOWPOWER)) 94 /** 95 * @} 96 */ 97 98 /** @defgroup SLEEP_mode_entry 99 * @{ 100 */ 101 #define SLEEP_ON_EXIT (1) 102 #define SLEEP_OFF_EXIT (0) 103 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) 104 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) 105 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) 106 107 108 /** 109 * @} 110 */ 111 112 113 /** @defgroup STOP_mode_entry 114 * @{ 115 */ 116 117 #define PWR_STOPENTRY_WFI ((uint8_t)0x01) 118 #define PWR_STOPENTRY_WFE ((uint8_t)0x02) 119 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) 120 121 /** 122 * @} 123 */ 124 125 /** @addtogroup PWR_Flag 126 * @{ 127 */ 128 //STS1 129 #define PWR_WKUP0_FLAG ((uint32_t)0x00000001) 130 #define PWR_WKUP1_FLAG ((uint32_t)0x00000002) 131 #define PWR_WKUP2_FLAG ((uint32_t)0x00000004) 132 #define PWR_STBY_FLAG ((uint32_t)0x00000100) 133 //STS2 134 #define PWR_LPRUN_FLAG ((uint32_t)0x00000001) 135 #define PWR_MR_FLAG ((uint32_t)0x00000002) 136 #define PWR_PVDO_FLAG ((uint32_t)0x00000004) 137 138 #define IS_PWR_GET_FLAG(FLAG) \ 139 (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\ 140 || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG)) 141 142 #define IS_PWR_CLEAR_FLAG(FLAG) \ 143 (((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\ 144 || ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG)) 145 146 147 148 /** @addtogroup SRAM1 SRAM2 retention set 149 * @{ 150 */ 151 //#define SRAM1DIS_SRAM2DIS 0 152 //#define SRAM1EN_SRAM2DIS 1 153 154 //#define SRAM1DIS_SRAM2EN 2 155 //#define SRAM1EN_SRAM2EN 3 156 /** @addtogroup MR VOLTAGE 157 * @{ 158 */ 159 #define MR_1V0 2 160 #define MR_1V1 3 161 162 163 /** 164 * @} 165 */ 166 typedef enum 167 { 168 WAKEUP_PIN0 = 0x0001, 169 WAKEUP_PIN1 = 0x0002, 170 WAKEUP_PIN2 = 0x0004, 171 } WAKEUP_PINX; 172 /** @addtogroup PWR_Exported_Macros 173 * @{ 174 */ 175 176 /** 177 * @} 178 */ 179 #define LPRUN_SWITCH_ADDR (__IO unsigned*)(0x40007000) 180 #define LPRUN_SRAM_ADDR (__IO unsigned*)(0x40001800 + 0x20) 181 #define CLERR_BIT25 0xfdffffff //bit25 182 #define _SetLprunSramVoltage(vale) do{(*LPRUN_SRAM_ADDR) &= CLERR_BIT25;(*LPRUN_SRAM_ADDR) |= (uint32_t)(vale <<25);}while (0) //0:0.9V 1:1.1V 183 #define _SetBandGapMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_BGDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<8);}while (0) //0:always on 1:duty on 184 #define _SetPvdBorMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_PBDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<16);}while (0) //0:normal mode 1:standby mode 185 #define _SetLprunswitch(vale) do{(*LPRUN_SWITCH_ADDR) &= (~0x0600);(*LPRUN_SWITCH_ADDR) |= (uint32_t)(vale <<9);}while (0) 186 /** @addtogroup PWR_Exported_Functions 187 * @{ 188 */ 189 190 void PWR_DeInit(void); 191 void PWR_BackupAccessEnable(FunctionalState Cmd); 192 void PWR_PvdEnable(FunctionalState Cmd); 193 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); 194 void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd); 195 void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 196 void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry); 197 void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode); 198 void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret); 199 void PWR_EnterLowPowerRunMode(void); 200 void PWR_ExitLowPowerRunMode(void); 201 void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry); 202 203 FlagStatus PWR_GetFlagStatus(uint8_t STS, uint32_t PWR_FLAG); 204 void PWR_ClearFlag(uint32_t PWR_FLAG); 205 void PWR_WakeUpPinConfig(void); 206 void SetSysClock_MSI(void); 207 uint8_t GetMrVoltage(void); 208 void PWR_MRconfig(uint8_t voltage); 209 #ifdef __cplusplus 210 } 211 #endif 212 213 #endif /* __N32L40X_PWR_H__ */ 214 /** 215 * @} 216 */ 217 218 /** 219 * @} 220 */ 221 222 /** 223 * @} 224 */ 225