1 /***************************************************************************** 2 * Copyright (c) 2022, Nations Technologies Inc. 3 * 4 * All rights reserved. 5 * **************************************************************************** 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * - Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the disclaimer below. 12 * 13 * Nations' name may not be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 19 * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 22 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 23 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 24 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 25 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * ****************************************************************************/ 27 28 /** 29 * @file n32l40x_spi.h 30 * @author Nations 31 * @version v1.2.0 32 * 33 * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. 34 */ 35 #ifndef __N32L40X_SPI_H__ 36 #define __N32L40X_SPI_H__ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include "n32l40x.h" 43 44 /** @addtogroup n32l40x_StdPeriph_Driver 45 * @{ 46 */ 47 48 /** @addtogroup SPI 49 * @{ 50 */ 51 52 /** @addtogroup SPI_Exported_Types 53 * @{ 54 */ 55 56 /** 57 * @brief SPI Init structure definition 58 */ 59 60 typedef struct 61 { 62 uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. 63 This parameter can be a value of @ref SPI_data_direction */ 64 65 uint16_t SpiMode; /*!< Specifies the SPI operating mode. 66 This parameter can be a value of @ref SPI_mode */ 67 68 uint16_t DataLen; /*!< Specifies the SPI data size. 69 This parameter can be a value of @ref SPI_data_size */ 70 71 uint16_t CLKPOL; /*!< Specifies the serial clock steady state. 72 This parameter can be a value of @ref SPI_Clock_Polarity */ 73 74 uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture. 75 This parameter can be a value of @ref SPI_Clock_Phase */ 76 77 uint16_t NSS; /*!< Specifies whether the NSS signal is managed by 78 hardware (NSS pin) or by software using the SSI bit. 79 This parameter can be a value of @ref SPI_Slave_Select_management */ 80 81 uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be 82 used to configure the transmit and receive SCK clock. 83 This parameter can be a value of @ref SPI_BaudRate_Prescaler. 84 @note The communication clock is derived from the master 85 clock. The slave clock does not need to be set. */ 86 87 uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 88 This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 89 90 uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */ 91 } SPI_InitType; 92 93 /** 94 * @brief I2S Init structure definition 95 */ 96 97 typedef struct 98 { 99 uint16_t I2sMode; /*!< Specifies the I2S operating mode. 100 This parameter can be a value of @ref I2sMode */ 101 102 uint16_t Standard; /*!< Specifies the standard used for the I2S communication. 103 This parameter can be a value of @ref Standard */ 104 105 uint16_t DataFormat; /*!< Specifies the data format for the I2S communication. 106 This parameter can be a value of @ref I2S_Data_Format */ 107 108 uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not. 109 This parameter can be a value of @ref I2S_MCLK_Output */ 110 111 uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication. 112 This parameter can be a value of @ref I2S_Audio_Frequency */ 113 114 uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock. 115 This parameter can be a value of @ref I2S_Clock_Polarity */ 116 } I2S_InitType; 117 118 /** 119 * @} 120 */ 121 122 /** @addtogroup SPI_Exported_Constants 123 * @{ 124 */ 125 126 #define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2)) 127 128 129 /** @addtogroup SPI_data_direction 130 * @{ 131 */ 132 133 #define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000) 134 #define SPI_DIR_DOUBLELINE_RONLY ((uint16_t)0x0400) 135 #define SPI_DIR_SINGLELINE_RX ((uint16_t)0x8000) 136 #define SPI_DIR_SINGLELINE_TX ((uint16_t)0xC000) 137 #define IS_SPI_DIR_MODE(MODE) \ 138 (((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY) \ 139 || ((MODE) == SPI_DIR_SINGLELINE_RX) || ((MODE) == SPI_DIR_SINGLELINE_TX)) 140 /** 141 * @} 142 */ 143 144 /** @addtogroup SPI_mode 145 * @{ 146 */ 147 148 #define SPI_MODE_MASTER ((uint16_t)0x0104) 149 #define SPI_MODE_SLAVE ((uint16_t)0x0000) 150 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE)) 151 /** 152 * @} 153 */ 154 155 /** @addtogroup SPI_data_size 156 * @{ 157 */ 158 159 #define SPI_DATA_SIZE_16BITS ((uint16_t)0x0800) 160 #define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000) 161 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS)) 162 /** 163 * @} 164 */ 165 166 /** @addtogroup SPI_Clock_Polarity 167 * @{ 168 */ 169 170 #define SPI_CLKPOL_LOW ((uint16_t)0x0000) 171 #define SPI_CLKPOL_HIGH ((uint16_t)0x0002) 172 #define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH)) 173 /** 174 * @} 175 */ 176 177 /** @addtogroup SPI_Clock_Phase 178 * @{ 179 */ 180 181 #define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000) 182 #define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0001) 183 #define IS_SPI_CLKPHA(CPHA) (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE)) 184 /** 185 * @} 186 */ 187 188 /** @addtogroup SPI_Slave_Select_management 189 * @{ 190 */ 191 192 #define SPI_NSS_SOFT ((uint16_t)0x0200) 193 #define SPI_NSS_HARD ((uint16_t)0x0000) 194 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD)) 195 /** 196 * @} 197 */ 198 199 /** @addtogroup SPI_BaudRate_Prescaler 200 * @{ 201 */ 202 203 #define SPI_BR_PRESCALER_2 ((uint16_t)0x0000) 204 #define SPI_BR_PRESCALER_4 ((uint16_t)0x0008) 205 #define SPI_BR_PRESCALER_8 ((uint16_t)0x0010) 206 #define SPI_BR_PRESCALER_16 ((uint16_t)0x0018) 207 #define SPI_BR_PRESCALER_32 ((uint16_t)0x0020) 208 #define SPI_BR_PRESCALER_64 ((uint16_t)0x0028) 209 #define SPI_BR_PRESCALER_128 ((uint16_t)0x0030) 210 #define SPI_BR_PRESCALER_256 ((uint16_t)0x0038) 211 #define IS_SPI_BR_PRESCALER(PRESCALER) \ 212 (((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) || ((PRESCALER) == SPI_BR_PRESCALER_8) \ 213 || ((PRESCALER) == SPI_BR_PRESCALER_16) || ((PRESCALER) == SPI_BR_PRESCALER_32) \ 214 || ((PRESCALER) == SPI_BR_PRESCALER_64) || ((PRESCALER) == SPI_BR_PRESCALER_128) \ 215 || ((PRESCALER) == SPI_BR_PRESCALER_256)) 216 /** 217 * @} 218 */ 219 220 /** @addtogroup SPI_MSB_LSB_transmission 221 * @{ 222 */ 223 224 #define SPI_FB_MSB ((uint16_t)0x0000) 225 #define SPI_FB_LSB ((uint16_t)0x0080) 226 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB)) 227 /** 228 * @} 229 */ 230 231 /** @addtogroup I2sMode 232 * @{ 233 */ 234 235 #define I2S_MODE_SlAVE_TX ((uint16_t)0x0000) 236 #define I2S_MODE_SlAVE_RX ((uint16_t)0x0100) 237 #define I2S_MODE_MASTER_TX ((uint16_t)0x0200) 238 #define I2S_MODE_MASTER_RX ((uint16_t)0x0300) 239 #define IS_I2S_MODE(MODE) \ 240 (((MODE) == I2S_MODE_SlAVE_TX) || ((MODE) == I2S_MODE_SlAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX) \ 241 || ((MODE) == I2S_MODE_MASTER_RX)) 242 /** 243 * @} 244 */ 245 246 /** @addtogroup Standard 247 * @{ 248 */ 249 250 #define I2S_STD_PHILLIPS ((uint16_t)0x0000) 251 #define I2S_STD_MSB_ALIGN ((uint16_t)0x0010) 252 #define I2S_STD_LSB_ALIGN ((uint16_t)0x0020) 253 #define I2S_STD_PCM_SHORTFRAME ((uint16_t)0x0030) 254 #define I2S_STD_PCM_LONGFRAME ((uint16_t)0x00B0) 255 #define IS_I2S_STANDARD(STANDARD) \ 256 (((STANDARD) == I2S_STD_PHILLIPS) || ((STANDARD) == I2S_STD_MSB_ALIGN) || ((STANDARD) == I2S_STD_LSB_ALIGN) \ 257 || ((STANDARD) == I2S_STD_PCM_SHORTFRAME) || ((STANDARD) == I2S_STD_PCM_LONGFRAME)) 258 /** 259 * @} 260 */ 261 262 /** @addtogroup I2S_Data_Format 263 * @{ 264 */ 265 266 #define I2S_DATA_FMT_16BITS ((uint16_t)0x0000) 267 #define I2S_DATA_FMT_16BITS_EXTENDED ((uint16_t)0x0001) 268 #define I2S_DATA_FMT_24BITS ((uint16_t)0x0003) 269 #define I2S_DATA_FMT_32BITS ((uint16_t)0x0005) 270 #define IS_I2S_DATA_FMT(FORMAT) \ 271 (((FORMAT) == I2S_DATA_FMT_16BITS) || ((FORMAT) == I2S_DATA_FMT_16BITS_EXTENDED) \ 272 || ((FORMAT) == I2S_DATA_FMT_24BITS) || ((FORMAT) == I2S_DATA_FMT_32BITS)) 273 /** 274 * @} 275 */ 276 277 /** @addtogroup I2S_MCLK_Output 278 * @{ 279 */ 280 281 #define I2S_MCLK_ENABLE ((uint16_t)0x0200) 282 #define I2S_MCLK_DISABLE ((uint16_t)0x0000) 283 #define IS_I2S_MCLK_ENABLE(OUTPUT) (((OUTPUT) == I2S_MCLK_ENABLE) || ((OUTPUT) == I2S_MCLK_DISABLE)) 284 /** 285 * @} 286 */ 287 288 /** @addtogroup I2S_Audio_Frequency 289 * @{ 290 */ 291 292 #define I2S_AUDIO_FREQ_192K ((uint32_t)192000) 293 #define I2S_AUDIO_FREQ_96K ((uint32_t)96000) 294 #define I2S_AUDIO_FREQ_48K ((uint32_t)48000) 295 #define I2S_AUDIO_FREQ_44K ((uint32_t)44100) 296 #define I2S_AUDIO_FREQ_32K ((uint32_t)32000) 297 #define I2S_AUDIO_FREQ_22K ((uint32_t)22050) 298 #define I2S_AUDIO_FREQ_16K ((uint32_t)16000) 299 #define I2S_AUDIO_FREQ_11K ((uint32_t)11025) 300 #define I2S_AUDIO_FREQ_8K ((uint32_t)8000) 301 #define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2) 302 303 #define IS_I2S_AUDIO_FREQ(FREQ) \ 304 ((((FREQ) >= I2S_AUDIO_FREQ_8K) && ((FREQ) <= I2S_AUDIO_FREQ_192K)) || ((FREQ) == I2S_AUDIO_FREQ_DEFAULT)) 305 /** 306 * @} 307 */ 308 309 /** @addtogroup I2S_Clock_Polarity 310 * @{ 311 */ 312 313 #define I2S_CLKPOL_LOW ((uint16_t)0x0000) 314 #define I2S_CLKPOL_HIGH ((uint16_t)0x0008) 315 #define IS_I2S_CLKPOL(CPOL) (((CPOL) == I2S_CLKPOL_LOW) || ((CPOL) == I2S_CLKPOL_HIGH)) 316 /** 317 * @} 318 */ 319 320 /** @addtogroup SPI_I2S_DMA_transfer_requests 321 * @{ 322 */ 323 324 #define SPI_I2S_DMA_TX ((uint16_t)0x0002) 325 #define SPI_I2S_DMA_RX ((uint16_t)0x0001) 326 #define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) 327 /** 328 * @} 329 */ 330 331 /** @addtogroup SPI_NSS_internal_software_management 332 * @{ 333 */ 334 335 #define SPI_NSS_HIGH ((uint16_t)0x0100) 336 #define SPI_NSS_LOW ((uint16_t)0xFEFF) 337 #define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW)) 338 /** 339 * @} 340 */ 341 342 /** @addtogroup SPI_CRC_Transmit_Receive 343 * @{ 344 */ 345 346 #define SPI_CRC_TX ((uint8_t)0x00) 347 #define SPI_CRC_RX ((uint8_t)0x01) 348 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX)) 349 /** 350 * @} 351 */ 352 353 /** @addtogroup SPI_direction_transmit_receive 354 * @{ 355 */ 356 357 #define SPI_BIDIRECTION_RX ((uint16_t)0xBFFF) 358 #define SPI_BIDIRECTION_TX ((uint16_t)0x4000) 359 #define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX)) 360 /** 361 * @} 362 */ 363 364 /** @addtogroup SPI_I2S_interrupts_definition 365 * @{ 366 */ 367 368 #define SPI_I2S_INT_TE ((uint8_t)0x71) 369 #define SPI_I2S_INT_RNE ((uint8_t)0x60) 370 #define SPI_I2S_INT_ERR ((uint8_t)0x50) 371 #define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_ERR)) 372 #define SPI_I2S_INT_OVER ((uint8_t)0x56) 373 #define SPI_INT_MODERR ((uint8_t)0x55) 374 #define SPI_INT_CRCERR ((uint8_t)0x54) 375 #define I2S_INT_UNDER ((uint8_t)0x53) 376 #define IS_SPI_I2S_CLR_INT(IT) (((IT) == SPI_INT_CRCERR)) 377 #define IS_SPI_I2S_GET_INT(IT) \ 378 (((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || ((IT) == I2S_INT_UNDER) || ((IT) == SPI_INT_CRCERR) \ 379 || ((IT) == SPI_INT_MODERR) || ((IT) == SPI_I2S_INT_OVER)) 380 /** 381 * @} 382 */ 383 384 /** @addtogroup SPI_I2S_flags_definition 385 * @{ 386 */ 387 388 #define SPI_I2S_RNE_FLAG ((uint16_t)0x0001) 389 #define SPI_I2S_TE_FLAG ((uint16_t)0x0002) 390 #define I2S_CHSIDE_FLAG ((uint16_t)0x0004) 391 #define I2S_UNDER_FLAG ((uint16_t)0x0008) 392 #define SPI_CRCERR_FLAG ((uint16_t)0x0010) 393 #define SPI_MODERR_FLAG ((uint16_t)0x0020) 394 #define SPI_I2S_OVER_FLAG ((uint16_t)0x0040) 395 #define SPI_I2S_BUSY_FLAG ((uint16_t)0x0080) 396 #define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG)) 397 #define IS_SPI_I2S_GET_FLAG(FLAG) \ 398 (((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || ((FLAG) == SPI_MODERR_FLAG) \ 399 || ((FLAG) == SPI_CRCERR_FLAG) || ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG) \ 400 || ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG)) 401 /** 402 * @} 403 */ 404 405 /** @addtogroup SPI_CRC_polynomial 406 * @{ 407 */ 408 409 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) 410 /** 411 * @} 412 */ 413 414 /** 415 * @} 416 */ 417 418 /** @addtogroup SPI_Exported_Macros 419 * @{ 420 */ 421 422 /** 423 * @} 424 */ 425 426 /** @addtogroup SPI_Exported_Functions 427 * @{ 428 */ 429 430 void SPI_I2S_DeInit(SPI_Module* SPIx); 431 void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct); 432 void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct); 433 void SPI_InitStruct(SPI_InitType* SPI_InitStruct); 434 void I2S_InitStruct(I2S_InitType* I2S_InitStruct); 435 void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd); 436 void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd); 437 void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd); 438 void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd); 439 void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data); 440 uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx); 441 void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft); 442 void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd); 443 void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen); 444 void SPI_TransmitCrcNext(SPI_Module* SPIx); 445 void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd); 446 uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC); 447 uint16_t SPI_GetCRCPoly(SPI_Module* SPIx); 448 void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection); 449 FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG); 450 void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG); 451 INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT); 452 void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT); 453 454 #ifdef __cplusplus 455 } 456 #endif 457 458 #endif /*__N32L40X_SPI_H__ */ 459 460 /** 461 * @} 462 */ 463 464 /** 465 * @} 466 */ 467 468 /** 469 * @} 470 */ 471