1 /***************************************************************************** 2 * Copyright (c) 2022, Nations Technologies Inc. 3 * 4 * All rights reserved. 5 * **************************************************************************** 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * - Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the disclaimer below. 12 * 13 * Nations' name may not be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 19 * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 22 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 23 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 24 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 25 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * ****************************************************************************/ 27 28 /** 29 * @file n32l43x_adc.h 30 * @author Nations 31 * @version v1.2.0 32 * 33 * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. 34 */ 35 #ifndef __N32L43X_ADC_H__ 36 #define __N32L43X_ADC_H__ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include "n32l43x.h" 43 #include <stdbool.h> 44 45 /** @addtogroup n32l43x_StdPeriph_Driver 46 * @{ 47 */ 48 #define VREF1P2_CTRL (*(uint32_t*)(0x40001800+0x24)) 49 #define _EnVref1p2() do{VREF1P2_CTRL|=(0x1<<13);}while (0); 50 #define _DisVref1p2() do{VREF1P2_CTRL&=~(0x1<<13);}while (0); 51 52 #define VREF2P0_CTRL (*(uint32_t*)(0x40001800+0x24)) 53 #define _EnVref2p0() do{VREF2P0_CTRL|=(0x1<<20);}while (0); 54 #define _DisVref2p0() do{VREF2P0_CTRL&=~(0x1<<20);}while (0); 55 56 /** @addtogroup ADC 57 * @{ 58 */ 59 60 /** @addtogroup ADC_Exported_Types 61 * @{ 62 */ 63 64 /** 65 * @brief ADC Init structure definition 66 */ 67 typedef struct 68 { 69 70 FunctionalState MultiChEn; /*!< Specifies whether the conversion is performed in 71 Scan (multichannels) or Single (one channel) mode. 72 This parameter can be set to ENABLE or DISABLE */ 73 74 FunctionalState ContinueConvEn; /*!< Specifies whether the conversion is performed in 75 Continuous or Single mode. 76 This parameter can be set to ENABLE or DISABLE. */ 77 78 uint32_t ExtTrigSelect; /*!< Defines the external trigger used to start the analog 79 to digital conversion of regular channels. This parameter 80 can be a value of @ref 81 ADC_external_trigger_sources_for_regular_channels_conversion */ 82 83 uint32_t DatAlign; /*!< Specifies whether the ADC data alignment is left or right. 84 This parameter can be a value of @ref ADC_data_align */ 85 86 uint8_t ChsNumber; /*!< Specifies the number of ADC channels that will be converted 87 using the sequencer for regular channel group. 88 This parameter must range from 1 to 16. */ 89 } ADC_InitType; 90 /** 91 * @} 92 */ 93 94 /** @addtogroup ADC_Exported_Constants 95 * @{ 96 */ 97 98 #define IsAdcModule(PERIPH) (((PERIPH) == ADC)) 99 100 #define IsAdcDmaModule(PERIPH) (((PERIPH) == ADC)) 101 102 103 104 /** @addtogroup ADC_external_trigger_sources_for_regular_channels_conversion 105 * @{ 106 */ 107 108 #define ADC_EXT_TRIGCONV_T1_CC1 ((uint32_t)0x00000000) 109 #define ADC_EXT_TRIGCONV_T1_CC2 ((uint32_t)0x00020000) 110 #define ADC_EXT_TRIGCONV_T1_CC3 ((uint32_t)0x00040000) 111 #define ADC_EXT_TRIGCONV_T2_CC2 ((uint32_t)0x00060000) 112 #define ADC_EXT_TRIGCONV_T3_TRGO ((uint32_t)0x00080000) 113 #define ADC_EXT_TRIGCONV_T4_CC4 ((uint32_t)0x000A0000) 114 #define ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO ((uint32_t)0x000C0000) 115 #define ADC_EXT_TRIGCONV_NONE ((uint32_t)0x000E0000) 116 117 118 #define IsAdcExtTrig(REGTRIG) \ 119 (((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC2) \ 120 || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC3) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC2) \ 121 || ((REGTRIG) == ADC_EXT_TRIGCONV_T3_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_T4_CC4) \ 122 || ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_NONE)) 123 /** 124 * @} 125 */ 126 127 /** @addtogroup ADC_data_align 128 * @{ 129 */ 130 131 #define ADC_DAT_ALIGN_R ((uint32_t)0x00000000) 132 #define ADC_DAT_ALIGN_L ((uint32_t)0x00000800) 133 #define IsAdcDatAlign(ALIGN) (((ALIGN) == ADC_DAT_ALIGN_R) || ((ALIGN) == ADC_DAT_ALIGN_L)) 134 /** 135 * @} 136 */ 137 138 /** @addtogroup ADC_channels 139 * @{ 140 */ 141 142 #define ADC_CH_0 ((uint8_t)0x00) 143 #define ADC_CH_1 ((uint8_t)0x01) 144 #define ADC_CH_2 ((uint8_t)0x02) 145 #define ADC_CH_3 ((uint8_t)0x03) 146 #define ADC_CH_4 ((uint8_t)0x04) 147 #define ADC_CH_5 ((uint8_t)0x05) 148 #define ADC_CH_6 ((uint8_t)0x06) 149 #define ADC_CH_7 ((uint8_t)0x07) 150 #define ADC_CH_8 ((uint8_t)0x08) 151 #define ADC_CH_9 ((uint8_t)0x09) 152 #define ADC_CH_10 ((uint8_t)0x0A) 153 #define ADC_CH_11 ((uint8_t)0x0B) 154 #define ADC_CH_12 ((uint8_t)0x0C) 155 #define ADC_CH_13 ((uint8_t)0x0D) 156 #define ADC_CH_14 ((uint8_t)0x0E) 157 #define ADC_CH_15 ((uint8_t)0x0F) 158 #define ADC_CH_16 ((uint8_t)0x10) 159 #define ADC_CH_17 ((uint8_t)0x11) 160 #define ADC_CH_18 ((uint8_t)0x12) 161 162 #define ADC_CH_VREFINT ((uint8_t)ADC_CH_0) 163 #define ADC_CH_TEMP_SENSOR ((uint8_t)ADC_CH_17) 164 #define ADC_CH_VREFBUF ((uint8_t)ADC_CH_18) 165 166 #define IsAdcChannel(CHANNEL) \ 167 (((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) \ 168 || ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) \ 169 || ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) \ 170 || ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15) \ 171 || ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18)) 172 /** 173 * @} 174 */ 175 176 /** @addtogroup ADC_sampling_time 177 * @{ 178 */ 179 180 #define ADC_SAMP_TIME_1CYCLES5 ((uint8_t)0x00) 181 #define ADC_SAMP_TIME_7CYCLES5 ((uint8_t)0x01) 182 #define ADC_SAMP_TIME_13CYCLES5 ((uint8_t)0x02) 183 #define ADC_SAMP_TIME_28CYCLES5 ((uint8_t)0x03) 184 #define ADC_SAMP_TIME_41CYCLES5 ((uint8_t)0x04) 185 #define ADC_SAMP_TIME_55CYCLES5 ((uint8_t)0x05) 186 #define ADC_SAMP_TIME_71CYCLES5 ((uint8_t)0x06) 187 #define ADC_SAMP_TIME_239CYCLES5 ((uint8_t)0x07) 188 #define IsAdcSampleTime(TIME) \ 189 (((TIME) == ADC_SAMP_TIME_1CYCLES5) || ((TIME) == ADC_SAMP_TIME_7CYCLES5) || ((TIME) == ADC_SAMP_TIME_13CYCLES5) \ 190 || ((TIME) == ADC_SAMP_TIME_28CYCLES5) || ((TIME) == ADC_SAMP_TIME_41CYCLES5) \ 191 || ((TIME) == ADC_SAMP_TIME_55CYCLES5) || ((TIME) == ADC_SAMP_TIME_71CYCLES5) \ 192 || ((TIME) == ADC_SAMP_TIME_239CYCLES5)) 193 /** 194 * @} 195 */ 196 197 /** @addtogroup ADC_external_trigger_sources_for_injected_channels_conversion 198 * @{ 199 */ 200 201 #define ADC_EXT_TRIG_INJ_CONV_T1_TRGO ((uint32_t)0x00000000) 202 #define ADC_EXT_TRIG_INJ_CONV_T1_CC4 ((uint32_t)0x00001000) 203 #define ADC_EXT_TRIG_INJ_CONV_T2_TRGO ((uint32_t)0x00002000) 204 #define ADC_EXT_TRIG_INJ_CONV_T2_CC1 ((uint32_t)0x00003000) 205 #define ADC_EXT_TRIG_INJ_CONV_T3_CC4 ((uint32_t)0x00004000) 206 #define ADC_EXT_TRIG_INJ_CONV_T4_TRGO ((uint32_t)0x00005000) 207 #define ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 ((uint32_t)0x00006000) 208 #define ADC_EXT_TRIG_INJ_CONV_NONE ((uint32_t)0x00007000) 209 210 211 #define IsAdcExtInjTrig(INJTRIG) \ 212 (((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_CC4) \ 213 || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_CC1) \ 214 || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T3_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_TRGO) \ 215 || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_NONE)) 216 /** 217 * @} 218 */ 219 220 /** @addtogroup ADC_injected_channel_selection 221 * @{ 222 */ 223 224 #define ADC_INJ_CH_1 ((uint8_t)0x14) 225 #define ADC_INJ_CH_2 ((uint8_t)0x18) 226 #define ADC_INJ_CH_3 ((uint8_t)0x1C) 227 #define ADC_INJ_CH_4 ((uint8_t)0x20) 228 #define IsAdcInjCh(CHANNEL) \ 229 (((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) \ 230 || ((CHANNEL) == ADC_INJ_CH_4)) 231 /** 232 * @} 233 */ 234 235 /** @addtogroup ADC_analog_watchdog_selection 236 * @{ 237 */ 238 239 #define ADC_ANALOG_WTDG_SINGLEREG_ENABLE ((uint32_t)0x00800200) 240 #define ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE ((uint32_t)0x00400200) 241 #define ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE ((uint32_t)0x00C00200) 242 #define ADC_ANALOG_WTDG_ALLREG_ENABLE ((uint32_t)0x00800000) 243 #define ADC_ANALOG_WTDG_ALLINJEC_ENABLE ((uint32_t)0x00400000) 244 #define ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE ((uint32_t)0x00C00000) 245 #define ADC_ANALOG_WTDG_NONE ((uint32_t)0x00000000) 246 247 #define IsAdcAnalogWatchdog(WATCHDOG) \ 248 (((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE) \ 249 || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ENABLE) \ 250 || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLINJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE) \ 251 || ((WATCHDOG) == ADC_ANALOG_WTDG_NONE)) 252 /** 253 * @} 254 */ 255 256 /** @addtogroup ADC_interrupts_definition 257 * @{ 258 */ 259 260 #define ADC_INT_ENDC ((uint16_t)0x0220) 261 #define ADC_INT_AWD ((uint16_t)0x0140) 262 #define ADC_INT_JENDC ((uint16_t)0x0480) 263 264 #define IsAdcInt(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) 265 266 #define IsAdcGetInt(IT) (((IT) == ADC_INT_ENDC) || ((IT) == ADC_INT_AWD) || ((IT) == ADC_INT_JENDC)) 267 /** 268 * @} 269 */ 270 271 /** @addtogroup ADC_flags_definition 272 * @{ 273 */ 274 275 #define ADC_FLAG_AWDG ((uint8_t)0x01) 276 #define ADC_FLAG_ENDC ((uint8_t)0x02) 277 #define ADC_FLAG_JENDC ((uint8_t)0x04) 278 #define ADC_FLAG_JSTR ((uint8_t)0x08) 279 #define ADC_FLAG_STR ((uint8_t)0x10) 280 #define ADC_FLAG_EOC_ANY ((uint8_t)0x20) 281 #define ADC_FLAG_JEOC_ANY ((uint8_t)0x40) 282 #define IsAdcClrFlag(FLAG) ((((FLAG) & (uint8_t)0x80) == 0x00) && ((FLAG) != 0x00)) 283 #define IsAdcGetFlag(FLAG) \ 284 (((FLAG) == ADC_FLAG_AWDG) || ((FLAG) == ADC_FLAG_ENDC) || ((FLAG) == ADC_FLAG_JENDC) || ((FLAG) == ADC_FLAG_JSTR) \ 285 || ((FLAG) == ADC_FLAG_STR) || ((FLAG) == ADC_FLAG_EOC_ANY) || ((FLAG) == ADC_FLAG_JEOC_ANY)) 286 /** 287 * @} 288 */ 289 290 /** @addtogroup ADC_thresholds 291 * @{ 292 */ 293 #define IsAdcValid(THRESHOLD) ((THRESHOLD) <= 0xFFF) 294 /** 295 * @} 296 */ 297 298 /** @addtogroup ADC_injected_offset 299 * @{ 300 */ 301 302 #define IsAdcOffsetValid(OFFSET) ((OFFSET) <= 0xFFF) 303 304 /** 305 * @} 306 */ 307 308 /** @addtogroup ADC_injected_length 309 * @{ 310 */ 311 312 #define IsAdcInjLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) 313 314 /** 315 * @} 316 */ 317 318 /** @addtogroup ADC_injected_rank 319 * @{ 320 */ 321 322 #define IsAdcInjRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) 323 324 /** 325 * @} 326 */ 327 328 /** @addtogroup ADC_regular_length 329 * @{ 330 */ 331 332 #define IsAdcSeqLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) 333 /** 334 * @} 335 */ 336 337 /** @addtogroup ADC_regular_rank 338 * @{ 339 */ 340 341 #define IsAdcReqRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) 342 343 /** 344 * @} 345 */ 346 347 /** @addtogroup ADC_regular_discontinuous_mode_number 348 * @{ 349 */ 350 351 #define IsAdcSeqDiscNumberValid(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) 352 353 /** 354 * @} 355 */ 356 357 /************************** fllowing bit seg in ex register **********************/ 358 /**@addtogroup ADC_channels_ex_style 359 * @{ 360 */ 361 362 363 #define ADC_CH_0 ((uint8_t)0x00) 364 #define ADC_CH_1_PA0 ((uint8_t)0x01) 365 #define ADC_CH_2_PA1 ((uint8_t)0x02) 366 #define ADC_CH_3_PA2 ((uint8_t)0x03) 367 #define ADC_CH_4_PA3 ((uint8_t)0x04) 368 #define ADC_CH_5_PA4 ((uint8_t)0x05) 369 #define ADC_CH_6_PA5 ((uint8_t)0x06) 370 #define ADC_CH_7_PA6 ((uint8_t)0x07) 371 #define ADC_CH_8_PA7 ((uint8_t)0x08) 372 #define ADC_CH_9_PB0 ((uint8_t)0x09) 373 #define ADC_CH_10_PB1 ((uint8_t)0x0A) 374 #define ADC_CH_11_PC0 ((uint8_t)0x0B) 375 #define ADC_CH_12_PC1 ((uint8_t)0x0C) 376 #define ADC_CH_13_PC2 ((uint8_t)0x0D) 377 #define ADC_CH_14_PC3 ((uint8_t)0x0E) 378 #define ADC_CH_15_PC4 ((uint8_t)0x0F) 379 #define ADC_CH_16_PC5 ((uint8_t)0x10) 380 #define ADC_CH_17 ((uint8_t)0x11) 381 #define ADC_CH_18 ((uint8_t)0x12) 382 /** 383 * @} 384 */ 385 386 /**@addtogroup ADC_dif_sel_ch_definition 387 * @{ 388 */ 389 #define aDC_DIFSEL_CHS_MASK ((uint32_t)0x0007FFFF) 390 #define ADC_DIFSEL_CHS_0 ((uint32_t)0x00000001) 391 #define ADC_DIFSEL_CHS_1 ((uint32_t)0x00000002) 392 #define ADC_DIFSEL_CHS_2 ((uint32_t)0x00000004) 393 #define ADC_DIFSEL_CHS_3 ((uint32_t)0x00000008) 394 #define ADC_DIFSEL_CHS_4 ((uint32_t)0x00000010) 395 #define ADC_DIFSEL_CHS_5 ((uint32_t)0x00000020) 396 #define ADC_DIFSEL_CHS_6 ((uint32_t)0x00000040) 397 #define ADC_DIFSEL_CHS_7 ((uint32_t)0x00000080) 398 #define ADC_DIFSEL_CHS_8 ((uint32_t)0x00000100) 399 #define ADC_DIFSEL_CHS_9 ((uint32_t)0x00000200) 400 #define ADC_DIFSEL_CHS_10 ((uint32_t)0x00000400) 401 #define ADC_DIFSEL_CHS_11 ((uint32_t)0x00000800) 402 #define ADC_DIFSEL_CHS_12 ((uint32_t)0x00001000) 403 #define ADC_DIFSEL_CHS_13 ((uint32_t)0x00002000) 404 #define ADC_DIFSEL_CHS_14 ((uint32_t)0x00004000) 405 #define ADC_DIFSEL_CHS_15 ((uint32_t)0x00008000) 406 #define ADC_DIFSEL_CHS_16 ((uint32_t)0x00010000) 407 #define ADC_DIFSEL_CHS_17 ((uint32_t)0x00020000) 408 #define ADC_DIFSEL_CHS_18 ((uint32_t)0x00040000) 409 /** 410 * @} 411 */ 412 413 /**@addtogroup ADC_calfact_definition 414 * @{ 415 */ 416 #define ADC_CALFACT_CALFACTD_MSK ((uint32_t)0x3FL << 16) 417 #define ADC_CALFACT_CALFACTS_MSK ((uint32_t)0x3FL << 0) 418 /** 419 * @} 420 */ 421 422 /**@addtogroup ADC_ctrl3_definition 423 * @{ 424 */ 425 #define ADC_CTRL3_DPWMOD_MSK ((uint32_t)0x01L << 10) 426 #define ADC_CTRL3_JENDCAIEN_MSK ((uint32_t)0x01L << 9) 427 #define ADC_CTRL3_ENDCAIEN_MSK ((uint32_t)0x01L << 8) 428 #define ADC_CTRL3_BPCAL_MSK ((uint32_t)0x01L << 7) 429 #define ADC_CTRL3_CKMOD_MSK ((uint32_t)0x01L << 4) 430 #define ADC_CTRL3_CALALD_MSK ((uint32_t)0x01L << 3) 431 #define ADC_CTRL3_CALDIF_MSK ((uint32_t)0x01L << 2) 432 #define ADC_CTRL3_RES_MSK ((uint32_t)0x03L << 0) 433 #define ADC_SAMPT3_SAMPSEL_MSK ((uint32_t)0x01L << 3) 434 435 #define ADC_CLOCK_PLL ((uint32_t)ADC_CTRL3_CKMOD_MSK) 436 #define ADC_CLOCK_AHB ((uint32_t)(~ADC_CTRL3_CKMOD_MSK)) 437 typedef enum 438 { 439 ADC_CTRL3_CKMOD_AHB = 0, 440 ADC_CTRL3_CKMOD_PLL = 1, 441 } ADC_CTRL3_CKMOD; 442 typedef enum 443 { 444 ADC_CTRL3_RES_12BIT = 3, 445 ADC_CTRL3_RES_10BIT = 2, 446 ADC_CTRL3_RES_8BIT = 1, 447 ADC_CTRL3_RES_6BIT = 0, 448 } ADC_CTRL3_RES; 449 typedef struct 450 { 451 FunctionalState DeepPowerModEn; 452 FunctionalState JendcIntEn; 453 FunctionalState EndcIntEn; 454 ADC_CTRL3_CKMOD ClkMode; 455 FunctionalState CalAtuoLoadEn; 456 bool DifModCal; 457 ADC_CTRL3_RES ResBit; 458 bool Samp303Style; 459 } ADC_InitTypeEx; 460 /** 461 * @} 462 */ 463 464 /**@addtogroup ADC_bit_num_definition 465 * @{ 466 */ 467 #define ADC_RST_BIT_12 ((uint32_t)0x03) 468 #define ADC_RST_BIT_10 ((uint32_t)0x02) 469 #define ADC_RST_BIT_8 ((uint32_t)0x01) 470 #define ADC_RESULT_BIT_6 ((uint32_t)0x00) 471 /** 472 * @} 473 */ 474 475 /** @addtogroup ADC_flags_ex_definition 476 * @{ 477 */ 478 #define ADC_FLAG_RDY ((uint8_t)0x20) 479 #define ADC_FLAG_PD_RDY ((uint8_t)0x40) 480 #define IS_ADC_GET_READY(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_PD_RDY)) 481 /** 482 * @} 483 */ 484 485 /** 486 * @} 487 */ 488 489 /** @addtogroup ADC_Exported_Functions 490 * @{ 491 */ 492 493 void ADC_DeInit(ADC_Module* ADCx); 494 void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct); 495 void ADC_InitStruct(ADC_InitType* ADC_InitStruct); 496 void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd); 497 void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd); 498 void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd); 499 void ADC_StartCalibration(ADC_Module* ADCx); 500 FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx); 501 void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd); 502 FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx); 503 void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number); 504 void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd); 505 void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); 506 void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd); 507 uint16_t ADC_GetDat(ADC_Module* ADCx); 508 void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); 509 void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd); 510 void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv); 511 void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); 512 void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd); 513 FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx); 514 void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); 515 void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length); 516 void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); 517 uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel); 518 void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog); 519 void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); 520 void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel); 521 void ADC_EnableTempSensorVrefint(FunctionalState Cmd); 522 FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG); 523 void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG); 524 INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT); 525 void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT); 526 527 void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx); 528 FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW); 529 void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en); 530 void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum); 531 532 void ADC_ConfigClk(ADC_CTRL3_CKMOD ADC_ClkMode, uint32_t RCC_ADCHCLKPrescaler); 533 /** 534 * @} 535 */ 536 537 #ifdef __cplusplus 538 } 539 #endif 540 541 #endif /*__N32L43X_ADC_H__ */ 542 543 /** 544 * @} 545 */ 546 /** 547 * @} 548 */ 549