1 /***************************************************************************** 2 * Copyright (c) 2022, Nations Technologies Inc. 3 * 4 * All rights reserved. 5 * **************************************************************************** 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * - Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the disclaimer below. 12 * 13 * Nations' name may not be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 19 * DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 22 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 23 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 24 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 25 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * ****************************************************************************/ 27 28 /** 29 * @file n32l43x_tsc.h 30 * @author Nations 31 * @version v1.2.0 32 * 33 * @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. 34 */ 35 #ifndef __N32L43X_TSC_H__ 36 #define __N32L43X_TSC_H__ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include "n32l43x.h" 43 44 /** @addtogroup n32l43x_StdPeriph_Driver 45 * @{ 46 */ 47 48 /** @addtogroup TSC 49 * @{ 50 */ 51 52 /** 53 * @brief TSC error code 54 */ 55 typedef enum { 56 TSC_ERROR_OK = 0x00U, /*!< No error */ 57 TSC_ERROR_CLOCK = 0x01U, /*!< clock config error */ 58 TSC_ERROR_PARAMETER = 0x02U, /*!< parameter error */ 59 TSC_ERROR_HW_MODE = 0x03U, /*!< Exit hw mode timeout */ 60 61 }TSC_ErrorTypeDef; 62 /** 63 * @ 64 */ 65 66 /** 67 * @brief TSC clock source 68 */ 69 #define TSC_CLK_SRC_LSI (RCC_LSXCLK_SRC_LSI) /*!< LSI*/ 70 #define TSC_CLK_SRC_LSE (RCC_LSE_ENABLE|RCC_LSXCLK_SRC_LSE) /*!< LSE */ 71 #define TSC_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS|RCC_LSXCLK_SRC_LSE) /*!< LSE bypass */ 72 /** 73 * @ 74 */ 75 76 77 /** 78 * @defgroup Detect_Period 79 */ 80 #define TSC_DET_PERIOD_8 (0x00000000U) /*!< DET_PERIOD[3:0] = 8/TSC_CLOCK */ 81 #define TSC_DET_PERIOD_16 (0x01UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000001U DET_PERIOD[3:0] = 16/TSC_CLOCK */ 82 #define TSC_DET_PERIOD_24 (0x02UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000002U DET_PERIOD[3:0] = 24/TSC_CLOCK */ 83 #define TSC_DET_PERIOD_32 (0x03UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000003U DET_PERIOD[3:0] = 32/TSC_CLOCK(default) */ 84 #define TSC_DET_PERIOD_40 (0x04UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000004U DET_PERIOD[3:0] = 40/TSC_CLOCK */ 85 #define TSC_DET_PERIOD_48 (0x05UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000005U DET_PERIOD[3:0] = 48/TSC_CLOCK */ 86 #define TSC_DET_PERIOD_56 (0x06UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000006U DET_PERIOD[3:0] = 56/TSC_CLOCK */ 87 #define TSC_DET_PERIOD_64 (0x07UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000007U DET_PERIOD[3:0] = 64/TSC_CLOCK */ 88 #define TSC_DET_PERIOD_72 (0x08UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000008U DET_PERIOD[3:0] = 72/TSC_CLOCK */ 89 #define TSC_DET_PERIOD_80 (0x09UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000009U DET_PERIOD[3:0] = 80/TSC_CLOCK */ 90 #define TSC_DET_PERIOD_88 (0x0AUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000AU DET_PERIOD[3:0] = 88/TSC_CLOCK */ 91 #define TSC_DET_PERIOD_96 (0x0BUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000BU DET_PERIOD[3:0] = 96/TSC_CLOCK */ 92 #define TSC_DET_PERIOD_104 (0x0CUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000CU DET_PERIOD[3:0] = 104/TSC_CLOCK */ 93 /** 94 * @ 95 */ 96 97 /** 98 * @defgroup Detect_Filter 99 */ 100 #define TSC_DET_FILTER_1 (0x00000000U) /*!< DET_FILTER[3:0] = 1 sample */ 101 #define TSC_DET_FILTER_2 (0x01UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000010U DET_FILTER[3:0] = 2 samples */ 102 #define TSC_DET_FILTER_3 (0x02UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000020U DET_FILTER[3:0] = 3 samples */ 103 #define TSC_DET_FILTER_4 (0x03UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000030U DET_FILTER[3:0] = 4 samples */ 104 /** 105 * @ 106 */ 107 108 /** 109 * @defgroup HW_Detect_Mode 110 */ 111 #define TSC_HW_DET_MODE_DISABLE (0x00000000U) /*!< Hardware detect mode disable */ 112 #define TSC_HW_DET_MODE_ENABLE (0x01UL << TSC_CTRL_HW_DET_MODE_Pos) /*!< 0x00000040U Hardware detect mode enable */ 113 /** 114 * @ 115 */ 116 117 /** 118 * @defgroup Detect_Type 119 */ 120 #define TSC_DET_TYPE_Msk (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk) 121 #define TSC_DET_TYPE_Pos (TSC_CTRL_LESS_DET_SEL_Pos) 122 123 #define TSC_DET_TYPE_NONE (0UL) /*!< 0x00000000U Disable detect */ 124 #define TSC_DET_TYPE_LESS (0x01UL << TSC_DET_TYPE_Pos) /*!< 0x00000100U Less detect enable */ 125 #define TSC_DET_TYPE_GREAT (0x02UL << TSC_DET_TYPE_Pos) /*!< 0x00000200U Great detect enable */ 126 #define TSC_DET_TYPE_PERIOD (0x03UL << TSC_DET_TYPE_Pos) /*!< 0x00000300U Both great and less detct enable */ 127 /** 128 * @ 129 */ 130 131 /** 132 * @defgroup TSC_Interrupt 133 */ 134 #define TSC_IT_DET_ENABLE (TSC_CTRL_DET_INTEN) /*!< Enable TSC detect interrupt */ 135 #define TSC_IT_DET_DISABLE (0UL) /*!< Disable TSC detect interrupt */ 136 /** 137 * @ 138 */ 139 140 /** 141 * @defgroup TSC_Out 142 */ 143 #define TSC_OUT_PIN (0x00000000U) /*!< TSC output to TSC_OUT pin */ 144 #define TSC_OUT_TIM4_ETR (0x1UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM4 ETR */ 145 #define TSC_OUT_TIM2_ETR (0x2UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM2 ETR and TIM2 CH1*/ 146 /** 147 * @ 148 */ 149 150 /** 151 * @defgroup TSC_Flag 152 */ 153 #define TSC_FLAG_HW (0x1UL << TSC_CTRL_HW_DET_ST_Pos) /*!< Flag of hardware detect mode */ 154 155 #define TSC_FLAG_GREAT_DET (0x1UL << TSC_STS_GREAT_DET_Pos) /*!< Flag of great detect type */ 156 #define TSC_FLAG_LESS_DET (0x1UL << TSC_STS_LESS_DET_Pos) /*!< Flag of less detect type */ 157 #define TSC_FLAG_PERIOD_DET (TSC_FLAG_GREAT_DET|TSC_FLAG_LESS_DET) /*!< Flag of period detect type */ 158 /** 159 * @ 160 */ 161 162 /** 163 * @defgroup TSC_SW_Detect 164 */ 165 #define TSC_SW_MODE_DISABLE (0x00000000U) /*!< Disable software detect mode */ 166 #define TSC_SW_MODE_ENABLE (0x1UL << TSC_ANA_CTRL_SW_TSC_EN_Pos) /*!< Enable software detect mode */ 167 /** 168 * @ 169 */ 170 171 /** 172 * @defgroup TSC_PadOption 173 */ 174 #define TSC_PAD_INTERNAL_RES (0x00000000U) /*!< Use internal resistor */ 175 #define TSC_PAD_EXTERNAL_RES (0x1UL << TSC_ANA_SEL_PAD_OPT_Pos) /*!< Use external resistor */ 176 /** 177 * @ 178 */ 179 180 /** 181 * @defgroup TSC_PadSpeed 182 */ 183 #define TSC_PAD_SPEED_0 (0x00000000U) /*!< Low speed,about 100K */ 184 #define TSC_PAD_SPEED_1 (0x1UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */ 185 #define TSC_PAD_SPEED_2 (0x2UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */ 186 #define TSC_PAD_SPEED_3 (0x3UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */ 187 /** 188 * @ 189 */ 190 191 /** 192 * @defgroup TSC_Constant 193 */ 194 #define TSC_CHN_SEL_ALL (TSC_CHNEN_CHN_SELx_Msk) 195 #define MAX_TSC_HW_CHN (24) /*Maximum number of tsc pin*/ 196 #define MAX_TSC_THRESHOLD_BASE (2047) /*Maximum detect base value of threshold*/ 197 #define MAX_TSC_THRESHOLD_DELTA (255) /*Maximum detect delta value of threshold*/ 198 #define TSC_TIMEOUT (0x01000000) /*TSC normal timeout */ 199 /** 200 * @ 201 */ 202 203 /** 204 * @defgroup TSC_DetectMode 205 */ 206 #define TSC_HW_DETECT_MODE (0x00000001U) /*TSC hardware detect mode*/ 207 #define TSC_SW_DETECT_MODE (0x00000000U) /*TSC software detect mode*/ 208 /** 209 * @ 210 */ 211 212 /* TSC Exported macros -----------------------------------------------------------*/ 213 /** @defgroup TSC_Exported_Macros 214 * @{ 215 */ 216 217 /** @brief Enable the TSC HW detect mode 218 * @param None 219 * @retval None 220 */ 221 #define __TSC_HW_ENABLE() SET_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE) 222 223 /** @brief Disable the TSC HW detect mode 224 * @param None 225 * @retval None 226 */ 227 #define __TSC_HW_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE) 228 229 /** @brief Config TSC detect period for HW detect mode 230 * @param __PERIOD__ specifies the TSC detect period during HW detect mode 231 * @arg TSC_DET_PERIOD_8: Detect period = 8/TSC_CLK 232 * @arg TSC_DET_PERIOD_16: Detect Period = 1/TSC_CLK 233 * @arg TSC_DET_PERIOD_24: Detect Period = 2/TSC_CLK 234 * @arg TSC_DET_PERIOD_32: Detect Period = 3/TSC_CLK 235 * @arg TSC_DET_PERIOD_40: Detect Period = 4/TSC_CLK 236 * @arg TSC_DET_PERIOD_48: Detect Period = 5/TSC_CLK 237 * @arg TSC_DET_PERIOD_56: Detect Period = 6/TSC_CLK 238 * @arg TSC_DET_PERIOD_64: Detect Period = 7/TSC_CLK 239 * @arg TSC_DET_PERIOD_72: Detect Period = 7/TSC_CLK 240 * @arg TSC_DET_PERIOD_80: Detect Period = 7/TSC_CLK 241 * @arg TSC_DET_PERIOD_88: Detect Period = 7/TSC_CLK 242 * @arg TSC_DET_PERIOD_96: Detect Period = 7/TSC_CLK 243 * @arg TSC_DET_PERIOD_104:Detect Period = 7/TSC_CLK 244 * @retval None 245 */ 246 #define __TSC_PERIOD_CONFIG(__PERIOD__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_PERIOD_Msk,__PERIOD__) 247 248 /** @brief Config TSC detect filter for HW detect mode 249 * @param __FILTER__ specifies the least usefull continuous samples during HW detect mode 250 * @arg TSC_DET_FILTER_1: Detect filter = 1 pulse 251 * @arg TSC_DET_FILTER_2: Detect filter = 2 pulse 252 * @arg TSC_DET_FILTER_3: Detect filter = 3 pulse 253 * @arg TSC_DET_FILTER_4: Detect filter = 4 pulse 254 * @retval None 255 */ 256 #define __TSC_FILTER_CONFIG(__FILTER__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_FILTER_Msk,__FILTER__) 257 258 /** @brief Config TSC detect type for HW detect mode,less great or both 259 * @param __TYPE__ specifies the detect type of a sample during HW detect mode 260 * @arg TSC_DET_TYPE_NONE: Detect disable 261 * @arg TSC_DET_TYPE_LESS: Pulse number must be greater than the threshold(basee-delta) during a sample time 262 * @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time 263 * @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta) 264 and also be less than (basee+delta) during a sample time 265 * @retval None 266 */ 267 #define __TSC_LESS_GREAT_CONFIG(__TYPE__) MODIFY_REG(TSC->CTRL, \ 268 (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk), \ 269 __TYPE__) 270 271 /** @brief Enable TSC interrupt 272 * @param None 273 * @retval None 274 */ 275 #define __TSC_INT_ENABLE() SET_BIT(TSC->CTRL, TSC_IT_DET_ENABLE) 276 277 /** @brief Disable TSC interrupt 278 * @param None 279 * @retval None 280 */ 281 #define __TSC_INT_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_IT_DET_ENABLE) 282 283 /** @brief Config the TSC output 284 * @param __OUT__ specifies where the TSC output should go 285 * @arg TSC_OUT_PIN: TSC output to the TSC_OUT pin 286 * @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR 287 * @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR 288 * @retval None 289 */ 290 #define __TSC_OUT_CONFIG(__OUT__) MODIFY_REG( TSC->CTRL, \ 291 (TSC_CTRL_TM4_ETR_Msk|TSC_CTRL_TM2_ETR_CH1_Msk),\ 292 __OUT__) 293 294 /** @brief Config the TSC channel 295 * @param __CHN__ specifies the pin of channels used for detect 296 * This parameter:bit[0:23] used,bit[24:31] must be 0 297 * bitx: TSC channel x 298 * @retval None 299 */ 300 #define __TSC_CHN_CONFIG(__CHN__) WRITE_REG(TSC->CHNEN, __CHN__) 301 302 /** @brief Enable the TSC SW detect mode 303 * @param None 304 * @retval None 305 */ 306 #define __TSC_SW_ENABLE() SET_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN) 307 308 /** @brief Disable the TSC SW detect mode 309 * @param None 310 * @retval None 311 */ 312 #define __TSC_SW_DISABLE() CLEAR_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN) 313 314 /** @brief Config the detect channel number during SW detect mode 315 * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN 316 * @retval None 317 */ 318 #define __TSC_SW_CHN_NUM_CONFIG(__NUM__) MODIFY_REG(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_PAD_MUX_Msk,__NUM__) 319 320 /** @brief Config the pad charge type 321 * @param __OPT__ specifies which resistor is used for charge 322 * @arg TSC_PAD_INTERNAL_RES: Internal resistor is used 323 * @arg TSC_PAD_EXTERNAL_RES: External resistor is used 324 * @retval None 325 */ 326 #define __TSC_PAD_OPT_CONFIG(__OPT__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_PAD_OPT_Msk,__OPT__) 327 328 /** @brief Config TSC speed 329 * @param __SPEED__ specifies the TSC speed range 330 * @arg TSC_PAD_SPEED_0: Low speed 331 * @arg TSC_PAD_SPEED_1: Middle speed 332 * @arg TSC_PAD_SPEED_2: Middle speed 333 * @arg TSC_PAD_SPEED_3: High speed 334 * @retval None 335 */ 336 #define __TSC_PAD_SPEED_CONFIG(__SPEED__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_SP_OPT_Msk,__SPEED__) 337 338 339 /** @brief Check if the HW detect mode is enable 340 * @param None 341 * @retval Current state of HW detect mode 342 */ 343 #define __TSC_GET_HW_MODE() (((TSC->CTRL) & TSC_FLAG_HW) == (TSC_FLAG_HW)) 344 345 /** @brief Check the detect type during HW detect mode 346 * @param __FLAG__ specifies the flag of detect type 347 * @arg TSC_FLAG_LESS_DET: Flag of less detect type 348 * @arg TSC_FLAG_GREAT_DET: Flag of great detect type 349 * @arg TSC_FLAG_PERIOD_DET: Flag of priod detect type 350 * @retval Current state of flag 351 */ 352 #define __TSC_GET_HW_DET_TYPE(__FLAG__) (((TSC->STS) & (__FLAG__))==(__FLAG__)) 353 354 /** @brief Get the number of channel which is detected now 355 * @param None 356 * @retval Current channel number 357 */ 358 #define __TSC_GET_CHN_NUMBER() (((TSC->STS) & TSC_STS_CHN_NUM_Msk) >> TSC_STS_CHN_NUM_Pos ) 359 360 /** @brief Get the count value of pulse 361 * @param None 362 * @retval Pulse count of current channel 363 */ 364 #define __TSC_GET_CHN_CNT() (((TSC->STS) & TSC_STS_CNT_VAL_Msk ) >> TSC_STS_CNT_VAL_Pos ) 365 366 /** @brief Get the base value of one channel 367 * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN 368 * @retval base value of the channel 369 */ 370 #define __TSC_GET_CHN_BASE(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_BASE_Msk ) >> TSC_THRHDx_BASE_Pos) 371 372 /** @brief Get the delta value of one channel 373 * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN 374 * @retval delta value of the channel 375 */ 376 #define __TSC_GET_CHN_DELTA(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_DELTA_Msk ) >> TSC_THRHDx_DELTA_Pos ) 377 378 /** @brief Get the internal resist value of one channel 379 * @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN 380 * @retval resist value of the channel 381 */ 382 #define __TSC_GET_CHN_RESIST(__NUM__) ((TSC->RESR[(__NUM__)>>3] >>(((__NUM__) & 0x7UL)*4)) & TSC_RESRx_CHN_RESIST_Msk) 383 384 /* Private macros ------------------------------------------------------------*/ 385 /** @defgroup TSC_Private_Macros 386 * @{ 387 */ 388 #define IS_TSC_DET_PERIOD(_PERIOD_) \ 389 (((_PERIOD_)==TSC_DET_PERIOD_8) ||((_PERIOD_)==TSC_DET_PERIOD_16)||((_PERIOD_)==TSC_DET_PERIOD_24) \ 390 ||((_PERIOD_)==TSC_DET_PERIOD_32)||((_PERIOD_)==TSC_DET_PERIOD_40)||((_PERIOD_)==TSC_DET_PERIOD_48) \ 391 ||((_PERIOD_)==TSC_DET_PERIOD_56)||((_PERIOD_)==TSC_DET_PERIOD_64)||((_PERIOD_)==TSC_DET_PERIOD_72) \ 392 ||((_PERIOD_)==TSC_DET_PERIOD_80)||((_PERIOD_)==TSC_DET_PERIOD_88)||((_PERIOD_)==TSC_DET_PERIOD_96) \ 393 ||((_PERIOD_)==TSC_DET_PERIOD_104) ) 394 395 #define IS_TSC_FILTER(_FILTER_) \ 396 ( ((_FILTER_)==TSC_DET_FILTER_1) ||((_FILTER_)==TSC_DET_FILTER_2)\ 397 ||((_FILTER_)==TSC_DET_FILTER_3) ||((_FILTER_)==TSC_DET_FILTER_4) ) 398 399 #define IS_TSC_DET_MODE(_MODE_) \ 400 ( ((_MODE_)==TSC_HW_DETECT_MODE) ||((_MODE_)==TSC_SW_DETECT_MODE) ) 401 402 #define IS_TSC_DET_TYPE(_TYPE_) \ 403 ( ((_TYPE_)==TSC_DET_TYPE_GREAT) ||((_TYPE_)==TSC_DET_TYPE_LESS) \ 404 ||((_TYPE_)==TSC_DET_TYPE_PERIOD)|| ((_TYPE_)==TSC_DET_TYPE_NONE) ) 405 406 #define IS_TSC_INT(_INT_) (((_INT_)==TSC_IT_DET_ENABLE)||((_INT_)==TSC_IT_DET_DISABLE)) 407 408 #define IS_TSC_OUT(_ETR_) (((_ETR_)==TSC_OUT_PIN)||((_ETR_)==TSC_OUT_TIM2_ETR)||((_ETR_)==TSC_OUT_TIM4_ETR)) 409 410 #define IS_TSC_CHN(_CHN_) (0==((_CHN_)&(~TSC_CHNEN_CHN_SELx_Msk))) 411 412 #define IS_TSC_CHN_NUMBER(_NUM_) ((uint32_t)(_NUM_)<MAX_TSC_HW_CHN) 413 414 #define IS_TSC_PAD_OPTION(_OPT_) (((_OPT_)==TSC_PAD_INTERNAL_RES)||((_OPT_)==TSC_PAD_EXTERNAL_RES)) 415 416 #define IS_TSC_PAD_SPEED(_SPEED_) \ 417 ( ((_SPEED_)==TSC_PAD_SPEED_0)||((_SPEED_)==TSC_PAD_SPEED_1) \ 418 ||((_SPEED_)==TSC_PAD_SPEED_2)||((_SPEED_)==TSC_PAD_SPEED_3) ) 419 420 #define IS_TSC_RESISTOR_VALUE(_RES_) \ 421 ( ((_RES_)==TSC_RESRx_CHN_RESIST_0)||((_RES_)==TSC_RESRx_CHN_RESIST_1) \ 422 ||((_RES_)==TSC_RESRx_CHN_RESIST_2)||((_RES_)==TSC_RESRx_CHN_RESIST_3) \ 423 ||((_RES_)==TSC_RESRx_CHN_RESIST_4)||((_RES_)==TSC_RESRx_CHN_RESIST_5) \ 424 ||((_RES_)==TSC_RESRx_CHN_RESIST_6)||((_RES_)==TSC_RESRx_CHN_RESIST_7) ) 425 426 #define IS_TSC_THRESHOLD_BASE(_BASE_) ( (_BASE_)<=MAX_TSC_THRESHOLD_BASE) 427 428 429 #define IS_TSC_THRESHOLD_DELTA(_DELTA_) ( (_DELTA_)<=MAX_TSC_THRESHOLD_DELTA) 430 431 /** 432 * @brief TSC Init structure definition 433 */ 434 435 typedef struct 436 { 437 uint32_t Mode; /*!< Configures the TSC work mode. 438 This parameter can be one value of @ref TSC_DetectMode */ 439 uint32_t Period; /*!< Configures the TSC check period for a sample. 440 This parameter can be one value of @ref Detect_Period */ 441 uint32_t Filter; /*!< Configures the TSC filter. 442 This parameter can be one value of @ref Detect_Filter */ 443 uint32_t Type; /*!< Configures the TSC check type 444 This parameter can be one value of @ref Detect_Type */ 445 uint32_t Chn; /*!< Selects the TSC chnnel used 446 This parameter can be one value of @ref TSC_CHNEN_CHN_SELx_Msk */ 447 uint32_t Out; /*!< Configures the TSC_OUT etr 448 This parameter can be one value of @ref TSC_Out */ 449 uint32_t Int; /*!< Configures the TSC interrupt 450 This parameter can be one value of @ref TSC_Interrupt */ 451 uint32_t PadOpt; /*!< Configures the TSC charge resistor 452 This parameter can be one value of @ref TSC_PadOption */ 453 uint32_t Speed; /*!< Configures the TSC detect speed 454 This parameter can be one value of @ref TSC_PadSpeed */ 455 }TSC_InitType; 456 457 typedef struct 458 { 459 uint16_t TSC_Base; /*!< base value */ 460 uint8_t TSC_Delta; /*!< offset value */ 461 uint8_t TSC_Resistor; /*!< resistance value configuration*/ 462 } TSC_ChnCfg; 463 464 TSC_ErrorTypeDef TSC_Init(TSC_InitType* InitParam); 465 TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource); 466 TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res ); 467 TSC_ErrorTypeDef TSC_ConfigThreshold( uint32_t Channels, uint32_t base, uint32_t delta); 468 TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum); 469 470 471 #ifdef __cplusplus 472 } 473 #endif 474 475 #endif /* __N32L43X_TSC_H__ */ 476 477 /** 478 * @} 479 */ 480 481 /** 482 * @} 483 */ 484