1 #ifndef __CE_PLATFORM_H
2 #define __CE_PLARFORM_H
3 
4 
5 #ifdef __cplusplus
6 extern "C"
7 {
8 #endif
9 
10 /*define CE version*/
11 #define CE_SUPPORT_CE_V3_1
12 
13 #define CE_NS_BASE_REG          (0x40004000)
14 #define CE_S_BASE_REG           (0x40004800)
15 
16 #define SUNXI_IRQ_CE            79
17 #define SUNXI_IRQ_CE_NS         80
18 
19 #define SUNXI_CLK_CE CLK_BUS_SS
20 #define SUNXI_CLK_MBUS_CE CLK_MBUS_CE
21 #define SUNXI_RST_CE RST_SS
22 
23 #define SUNXI_CCM_BASE          (0x03001000)
24 #define CCMU_CE_CLK_REG         (SUNXI_CCM_BASE + 0x680)
25 #define CCMU_CE_BGR_REG         (SUNXI_CCM_BASE + 0x68C)
26 #define MBUS_MAT_CLK_GATING_REG     (SUNXI_CCM_BASE + 0x804)
27 
28 #define CE_CLK_SRC_MASK         (0x1)
29 #define CE_CLK_SRC_SEL_BIT      (24)
30 #define CE_CLK_SRC          (0x01)
31 #define CE_CLK_DIV_RATION_N_BIT     (8)
32 #define CE_CLK_DIV_RATION_N_MASK    (0x3)
33 #define CE_CLK_DIV_RATION_N     (0)
34 
35 #define CE_CLK_DIV_RATION_M_BIT     (0)
36 #define CE_CLK_DIV_RATION_M_MASK    (0xF)
37 #define CE_CLK_DIV_RATION_M     (3)
38 
39 #define CE_SCLK_ONOFF_BIT       (31)
40 #define CE_SCLK_ON          (1)
41 
42 #define CE_GATING_PASS          (1)
43 #define CE_GATING_BIT           (0)
44 #define CE_RST_BIT          (16)
45 #define CE_DEASSERT         (1)
46 
47 #endif
48