1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the People's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY¡¯S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS¡¯SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY¡¯S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef __SPI_SUN8IW19_H__ 34 #define __SPI_SUN8IW19_H__ 35 36 #define SUNXI_SPI0_PBASE 0X05010000 /* 4K */ 37 #define SUNXI_SPI1_PBASE 0X05011000 /* 4K */ 38 #define SUNXI_SPI2_PBASE 0X05012000 /* 4K */ 39 #define SUNXI_IRQ_SPI0 86 40 #define SUNXI_IRQ_SPI1 87 41 #define SUNXI_IRQ_SPI2 88 42 43 #define SPI_MAX_NUM 3 44 #define SPI0_PARAMS \ 45 {.reg_base = SUNXI_SPI0_PBASE, .irq_num = SUNXI_IRQ_SPI0, .gpio_num = 6, \ 46 .gpio_clk = GPIO_PC0, .gpio_mosi = GPIO_PC2, .gpio_miso = GPIO_PC3, \ 47 .gpio_cs0 = GPIO_PC1, .gpio_wp = GPIO_PC4, .gpio_hold = GPIO_PC5, \ 48 .mux = 4, .driv_level = GPIO_DRIVING_LEVEL2} 49 #define SPI1_PARAMS \ 50 {.reg_base = SUNXI_SPI1_PBASE, .irq_num = SUNXI_IRQ_SPI1, .gpio_num = 4, \ 51 .gpio_clk = GPIO_PH0, .gpio_mosi = GPIO_PH1, .gpio_miso = GPIO_PH2, \ 52 .gpio_cs0 = GPIO_PH3, .gpio_wp = 0, .gpio_hold = 0, \ 53 .mux = 4, .driv_level = GPIO_DRIVING_LEVEL2} 54 #define SPI2_PARAMS \ 55 {.reg_base = SUNXI_SPI2_PBASE, .irq_num = SUNXI_IRQ_SPI2, .gpio_num = 4, \ 56 .gpio_clk = GPIO_PE18, .gpio_mosi = GPIO_PE19, .gpio_miso = GPIO_PE20, \ 57 .gpio_cs0 = GPIO_PE21, .gpio_wp = 0, .gpio_hold = 0, \ 58 .mux = 4, .driv_level = GPIO_DRIVING_LEVEL2} 59 60 #define SUNXI_CLK_SPI(x) HAL_CLK_PERIPH_SPI##x 61 #define SUNXI_CLK_BUS_SPI(x) 0 62 #define SUNXI_CLK_RST_SPI(x) 0 63 #define SUNXI_CLK_PLL_SPI HAL_CLK_PLL_PERI0 64 65 66 #endif /*__SPI_SUN8IW19_H__ */ 67