1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the people's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 #ifndef __SUN8IW19_DAUDIO_H_ 33 #define __SUN8IW19_DAUDIO_H_ 34 35 #define SUNXI_DAUDIO_BASE (0x05090000) 36 37 #define DAUDIO_NUM_MAX 2 38 39 /*------------------------ CLK CONFIG FOR NORMAL ---------------------------*/ 40 #define SUNXI_DAUDIO_CLK_PLL_AUDIO HAL_CLK_PLL_AUDIO 41 #define SUNXI_DAUDIO_CLK_PLL_AUDIO1 HAL_CLK_PLL_AUDIOX4 42 #define SUNXI_DAUDIO_CLK_I2S_ASRC 0 43 44 #define SUNXI_DAUDIO_CLK_I2S0 HAL_CLK_PERIPH_I2S0 45 #define SUNXI_DAUDIO_CLK_BUS_I2S0 0 46 #define SUNXI_DAUDIO_CLK_RST_I2S0 0 47 48 #define SUNXI_DAUDIO_CLK_I2S1 HAL_CLK_PERIPH_I2S1 49 #define SUNXI_DAUDIO_CLK_BUS_I2S1 0 50 #define SUNXI_DAUDIO_CLK_RST_I2S1 0 51 52 #define SUNXI_DAUDIO_CLK_I2S2 HAL_CLK_PERIPH_I2S2 53 #define SUNXI_DAUDIO_CLK_BUS_I2S2 0 54 #define SUNXI_DAUDIO_CLK_RST_I2S2 0 55 56 #define SUNXI_DAUDIO_CLK_I2S3 0 57 #define SUNXI_DAUDIO_CLK_BUS_I2S3 0 58 #define SUNXI_DAUDIO_CLK_RST_I2S3 0 59 60 /*------------------------ PIN CONFIG FOR NORMAL ---------------------------*/ 61 /* GPIO define */ 62 #define DAUDIO0_PIN_MCLK \ 63 {.gpio_pin = GPIOH(0), .mux = 3, .driv_level = GPIO_DRIVING_LEVEL1} 64 #define DAUDIO0_PIN_BCLK \ 65 {.gpio_pin = GPIOH(1), .mux = 3, .driv_level = GPIO_DRIVING_LEVEL1} 66 #define DAUDIO0_PIN_LRCK \ 67 {.gpio_pin = GPIOH(2), .mux = 3, .driv_level = GPIO_DRIVING_LEVEL1} 68 #define DAUDIO0_PIN_DOUT \ 69 {.gpio_pin = GPIOH(3), .mux = 3, .driv_level = GPIO_DRIVING_LEVEL1} 70 #define DAUDIO0_PIN_DIN \ 71 {.gpio_pin = GPIOH(4), .mux = 3, .driv_level = GPIO_DRIVING_LEVEL1} 72 73 #define DAUDIO1_PIN_MCLK \ 74 {.gpio_pin = GPIOD(10), .mux = 3, .driv_level = GPIO_DRIVING_LEVEL1} 75 #define DAUDIO1_PIN_BCLK \ 76 {.gpio_pin = GPIOD(11), .mux = 3, .driv_level = GPIO_DRIVING_LEVEL1} 77 #define DAUDIO1_PIN_LRCK \ 78 {.gpio_pin = GPIOD(12), .mux = 3, .driv_level = GPIO_DRIVING_LEVEL1} 79 #define DAUDIO1_PIN_DOUT \ 80 {.gpio_pin = GPIOD(13), .mux = 3, .driv_level = GPIO_DRIVING_LEVEL1} 81 #define DAUDIO1_PIN_DIN \ 82 {.gpio_pin = GPIOD(16), .mux = 3, .driv_level = GPIO_DRIVING_LEVEL1} 83 84 /* 85 * Daudio Params 86 * 87 *daudio_master: 88 * 1: SND_SOC_DAIFMT_CBM_CFM(codec clk & FRM master) use 89 * 2: SND_SOC_DAIFMT_CBS_CFM(codec clk slave & FRM master) not use 90 * 3: SND_SOC_DAIFMT_CBM_CFS(codec clk master & frame slave) not use 91 * 4: SND_SOC_DAIFMT_CBS_CFS(codec clk & FRM slave) use 92 *tdm_config: 93 * 0 is pcm; 1 is i2s 94 *audio_format: 95 * 1:SND_SOC_DAIFMT_I2S(standard i2s format). use 96 * 2:SND_SOC_DAIFMT_RIGHT_J(right justfied format). 97 * 3:SND_SOC_DAIFMT_LEFT_J(left justfied format) 98 * 4:SND_SOC_DAIFMT_DSP_A(pcm. MSB is available on 2nd BCLK rising edge after LRC rising edge). use 99 * 5:SND_SOC_DAIFMT_DSP_B(pcm. MSB is available on 1nd BCLK rising edge after LRC rising edge) 100 *signal_inversion: 101 * 1:SND_SOC_DAIFMT_NB_NF(normal bit clock + frame) use 102 * 2:SND_SOC_DAIFMT_NB_IF(normal BCLK + inv FRM) 103 * 3:SND_SOC_DAIFMT_IB_NF(invert BCLK + nor FRM) use 104 * 4:SND_SOC_DAIFMT_IB_IF(invert BCLK + FRM) 105 *pcm_lrck_period :16/32/64/128/256 106 *msb_lsb_first :0: msb first; 1: lsb first 107 *sign_extend :0: zero pending; 1: sign extend 108 *slot_width_select :8 bit width / 16 bit width / 32 bit width 109 *frametype :0: short frame = 1 clock width; 1: long frame = 2 clock width 110 *mclk_div :0: not output(normal setting this); 111 * :1/2/4/6/8/12/16/24/32/48/64/96/128/176/192: 112 * setting mclk as input clock to external codec, 113 * freq is pll_audio/mclk_div 114 *tx_data_mode :0: 16bit linear PCM; (use) 1: reserved; 115 * :2: 8bit u-law; (no use) 3: 8bit a-law (no use) 116 *rx_data_mode :0: 16bit linear PCM; (use) 1: reserved; 117 * :2: 8bit u-law; (no use) 3: 8bit a-law (no use) 118 */ 119 120 #define DAUDIO0_PARAMS \ 121 {.tdm_num = 0, \ 122 .daudio_master = 4, .audio_format = 1, .signal_inversion = 1, \ 123 .pcm_lrck_period = 128, .slot_width_select = 32, \ 124 .msb_lsb_first = 0, .frametype = 0, \ 125 .tx_data_mode = 0, .rx_data_mode = 0, \ 126 .tdm_config = 1, .mclk_div = 1,\ 127 } 128 129 #define DAUDIO1_PARAMS \ 130 {.tdm_num = 1, \ 131 .daudio_master = 4, .audio_format = 1, .signal_inversion = 1, \ 132 .pcm_lrck_period = 128, .slot_width_select = 32, \ 133 .msb_lsb_first = 1, .frametype = 1, \ 134 .tx_data_mode = 0, .rx_data_mode = 0, \ 135 .tdm_config = 0, .mclk_div = 1,\ 136 } 137 138 struct daudio_pinctrl daudio0_pinctrl[] = { 139 DAUDIO0_PIN_MCLK, 140 DAUDIO0_PIN_BCLK, 141 DAUDIO0_PIN_LRCK, 142 DAUDIO0_PIN_DOUT, 143 DAUDIO0_PIN_DIN, 144 }; 145 146 struct daudio_pinctrl daudio1_pinctrl[] = { 147 DAUDIO1_PIN_MCLK, 148 DAUDIO1_PIN_BCLK, 149 DAUDIO1_PIN_LRCK, 150 DAUDIO1_PIN_DOUT, 151 DAUDIO1_PIN_DIN, 152 }; 153 154 struct sunxi_daudio_param daudio_param[] = { 155 DAUDIO0_PARAMS, 156 DAUDIO1_PARAMS, 157 }; 158 159 160 /* SUNXI_ADC_DAUDIO_SYNC: Whether to enable ADC AEC Drive adaptation */ 161 /* #define SUNXI_ADC_DAUDIO_SYNC */ 162 163 enum sunxi_pcm_adc_i2s_mode { 164 ADC_CODEC_SYNC = 0, 165 ADC_I2S_SYNC = 1, 166 ADC_I2S_RUNNING = 2, 167 }; 168 169 void sunxi_daudio_rx_drq_enable(bool enable); 170 171 #endif /* __SUN8IW19_DAUDIO_H_ */ 172