1 /* 2 * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved. 3 * 4 * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in 5 * the the people's Republic of China and other countries. 6 * All Allwinner Technology Co.,Ltd. trademarks are used with permission. 7 * 8 * DISCLAIMER 9 * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. 10 * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.) 11 * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN 12 * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. 13 * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS 14 * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE. 15 * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY. 16 * 17 * 18 * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT 19 * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND, 20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING 21 * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE 22 * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 23 * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 30 * OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 #ifndef __SUN8IW20_SPDIF_H_ 33 #define __SUN8IW20_SPDIF_H_ 34 35 #define SUNXI_SPDIF_MEMBASE (0x02036000) 36 37 /*add this to surport the spdif receive IEC-61937 data */ 38 #define CONFIG_SND_SUNXI_SPDIF_RX_IEC61937 39 40 /*------------------------ CLK CONFIG FOR NORMAL ---------------------------*/ 41 #define SUNXI_SPDIF_CLK_PLL_AUDIO CLK_PLL_AUDIO0 42 #define SUNXI_SPDIF_CLK_SPDIF CLK_SPDIF_TX 43 #define SUNXI_SPDIF_CLK_BUS CLK_BUS_SPDIF 44 #define SUNXI_SPDIF_CLK_RST RST_BUS_SPDIF 45 #define SUNXI_SPDIF_CLK_PLL_AUDIO1 CLK_PLL_AUDIO1 46 #define SUNXI_SPDIF_CLK_PLL_AUDIO1_DIV CLK_PLL_AUDIO1_DIV5 47 #define SUNXI_SPDIF_CLK_SPDIF_RX CLK_SPDIF_RX 48 49 /*------------------SPDIF EXP register definition--------------------*/ 50 #define SUNXI_SPDIF_EXP_CTL 0x40 51 #define SUNXI_SPDIF_EXP_ISTA 0x44 52 #define SUNXI_SPDIF_EXP_INFO0 0x48 53 #define SUNXI_SPDIF_EXP_INFO1 0x4C 54 #define SUNXI_SPDIF_EXP_DBG0 0x50 55 #define SUNXI_SPDIF_EXP_DBG1 0x54 56 #define SUNXI_SPDIF_EXP_VER 0x58 57 58 /* SUNXI_SPDIF_EXP_CTL register */ 59 #define INSET_DET_NUM 0 60 #define INSET_DET_EN 8 61 #define SYNCW_BIT_EN 9 62 #define DATA_TYPE_BIT_EN 10 63 #define DATA_LEG_BIT_EN 11 64 #define AUDIO_DATA_BIT_EN 12 65 #define RX_MODE 13 66 #define RX_MODE_MAN 14 67 #define UNIT_SEL 15 68 #define RPOTBF_NUM 16 69 #define BURST_DATA_OUT_SEL 30 70 71 /* SUNXI_SPDIF_EXP_ISTA register */ 72 #define INSET_INT 0 73 #define PAPB_CAP_INT 1 74 #define PCPD_CAP_INT 2 75 #define RPDB_ERR_INT 3 76 #define PC_DTYOE_CH_INT 4 77 #define PC_ERR_FLAG_INT 5 78 #define PC_BIT_CH_INT 6 79 #define PC_PAUSE_STOP_INT 7 80 #define PD_CHAN_INT 8 81 #define INSET_INT_EN 16 82 #define PAPB_CAP_INT_EN 17 83 #define PCPD_CAP_INT_EN 18 84 #define RPDB_ERR_INT_EN 19 85 #define PC_DTYOE_CH_INT_EN 20 86 #define PC_ERR_FLAG_INT_EN 21 87 #define PC_BIT_CH_INT_EN 22 88 #define PC_PAUSE_STOP_INT_EN 23 89 #define PD_CHAN_INT_EN 24 90 91 /* SUNXI_SPDIF_EXP_INFO0 register */ 92 #define PD_DATA_INFO 0 93 #define PC_DATA_INFO 16 94 95 /* SUNXI_SPDIF_EXP_INFO1 register */ 96 #define SAMPLE_RATE_VAL 0 97 #define RPOTBF_VAL 16 98 99 /* SUNXI_SPDIF_EXP_DBG0 register */ 100 #define RE_DATA_COUNT_VAL 0 101 #define DATA_CAP_STA_MACHE 16 102 103 /* SUNXI_SPDIF_EXP_DBG1 register */ 104 #define SAMPLE_RATE_COUNT 0 105 #define RPOTBF_COUNT 16 106 107 /* SUNXI_SPDIF_EXP_VER register */ 108 #define MOD_VER 0 109 110 /*------------------------ PIN CONFIG FOR NORMAL ---------------------------*/ 111 112 113 114 /*------------------------ PIN CONFIG FOR FPGA VERIFY -----------------------*/ 115 spdif_gpio_t g_spdif_gpio = { 116 // .clk = {GPIOB(12), 3}, 117 .out = {GPIOB(6), 2}, 118 .in = {GPIOB(7), 2}, 119 }; 120 121 #endif /* __SUN8IW20_SPDIF_H_ */ 122