1 /*
2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include "sdkconfig.h"
7 #include "esp_idf_version.h"
8 #include "esp_intr_alloc.h"
9 #include "esp_private/usb_phy.h"
10 #include "soc/periph_defs.h"
11 #include "freertos/FreeRTOS.h"
12 #include "freertos/task.h"
13 #include "usbd_core.h"
14 #include "usbh_core.h"
15 #include "usb_dwc2_param.h"
16
17 #define GET_USB_INDEX(reg_base) 0
18 #define GET_USB_INTR_SOURCE(reg_base) ETS_USB_INTR_SOURCE
19 #define GET_USB_PHY_TARGET(reg_base) USB_PHY_TARGET_INT
20 #define GET_USB_PHY_SPEED(reg_base) USB_PHY_SPEED_UNDEFINED
21 #ifdef CONFIG_IDF_TARGET_ESP32S2
22 #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ
23 #define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE
24 #elif CONFIG_IDF_TARGET_ESP32S3
25 #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
26 #define DEFAULT_USB_INTR_SOURCE ETS_USB_INTR_SOURCE
27 #elif CONFIG_IDF_TARGET_ESP32P4
28 #undef GET_USB_INDEX
29 #define GET_USB_INDEX(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? 0 : 1)
30 #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ
31 #define DEFAULT_USB_INTR_SOURCE ETS_USB_OTG_INTR_SOURCE
32 #define USB_FS_INTR_SOURCE ETS_USB_OTG11_CH0_INTR_SOURCE
33 #undef GET_USB_INTR_SOURCE
34 #define GET_USB_INTR_SOURCE(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? DEFAULT_USB_INTR_SOURCE : USB_FS_INTR_SOURCE)
35 #undef GET_USB_PHY_TARGET
36 #define GET_USB_PHY_TARGET(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? USB_PHY_TARGET_UTMI : USB_PHY_TARGET_INT)
37 #undef GET_USB_PHY_SPEED
38 #define GET_USB_PHY_SPEED(reg_base) ((reg_base) == (void*)ESP_USB_HS0_BASE ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL)
39 #else
40 #define DEFAULT_CPU_FREQ_MHZ 160
41 #endif
42
43 uint32_t SystemCoreClock = (DEFAULT_CPU_FREQ_MHZ * 1000 * 1000);
44 static usb_phy_handle_t s_phy_handle[SOC_USB_OTG_PERIPH_NUM] = {NULL};
45 static intr_handle_t s_interrupt_handle[SOC_USB_OTG_PERIPH_NUM] = {NULL};
46
47 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
48 const struct dwc2_user_params param_fs = {
49 .phy_type = DWC2_PHY_TYPE_PARAM_FS,
50 .device_dma_enable = true,
51 .device_dma_desc_enable = false,
52 .device_rx_fifo_size = (200 - 16 * 7),
53 .device_tx_fifo_size = {
54 [0] = 16, // 64 byte
55 [1] = 16, // 64 byte
56 [2] = 16, // 64 byte
57 [3] = 16, // 64 byte
58 [4] = 16, // 64 byte
59 [5] = 16, // 64 byte
60 [6] = 16, // 64 byte
61 [7] = 0,
62 [8] = 0,
63 [9] = 0,
64 [10] = 0,
65 [11] = 0,
66 [12] = 0,
67 [13] = 0,
68 [14] = 0,
69 [15] = 0 },
70
71 .host_dma_desc_enable = false,
72 .host_rx_fifo_size = 80,
73 .host_nperio_tx_fifo_size = 60, // 240 byte
74 .host_perio_tx_fifo_size = 60, // 240 byte
75 };
76 #elif CONFIG_IDF_TARGET_ESP32P4
77 const struct dwc2_user_params param_fs = {
78 .phy_type = DWC2_PHY_TYPE_PARAM_FS,
79 .device_dma_enable = true,
80 .device_dma_desc_enable = false,
81 .device_rx_fifo_size = (200 - 16 * 7),
82 .device_tx_fifo_size = {
83 [0] = 16, // 64 byte
84 [1] = 16, // 64 byte
85 [2] = 16, // 64 byte
86 [3] = 16, // 64 byte
87 [4] = 16, // 64 byte
88 [5] = 16, // 64 byte
89 [6] = 16, // 64 byte
90 [7] = 0,
91 [8] = 0,
92 [9] = 0,
93 [10] = 0,
94 [11] = 0,
95 [12] = 0,
96 [13] = 0,
97 [14] = 0,
98 [15] = 0 },
99
100 .host_dma_desc_enable = false,
101 .host_rx_fifo_size = (200 - 60 - 60),
102 .host_nperio_tx_fifo_size = 60, // 240 byte
103 .host_perio_tx_fifo_size = 60, // 240 byte
104 };
105
106 const struct dwc2_user_params param_hs = {
107 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
108 .device_dma_enable = true,
109 .device_dma_desc_enable = false,
110 .device_rx_fifo_size = (896 - 16 - 128 - 128 - 128 - 128 - 16 - 16),
111 .device_tx_fifo_size = {
112 [0] = 16, // 64 byte
113 [1] = 128, // 512 byte
114 [2] = 128, // 512 byte
115 [3] = 128, // 512 byte
116 [4] = 128, // 512 byte
117 [5] = 16, // 64 byte
118 [6] = 16, // 64 byte
119 [7] = 0,
120 [8] = 0,
121 [9] = 0,
122 [10] = 0,
123 [11] = 0,
124 [12] = 0,
125 [13] = 0,
126 [14] = 0,
127 [15] = 0 },
128
129 .host_dma_desc_enable = false,
130 .host_rx_fifo_size = (896 - 128 - 128),
131 .host_nperio_tx_fifo_size = 128, // 512 byte
132 .host_perio_tx_fifo_size = 128, // 512 byte
133 };
134 #endif
135
usb_dc_interrupt_cb(void * arg_pv)136 static void usb_dc_interrupt_cb(void *arg_pv)
137 {
138 extern void USBD_IRQHandler(uint8_t busid);
139 uint8_t busid = (uintptr_t)arg_pv;
140 USBD_IRQHandler(busid);
141 }
142
usb_dc_low_level_init(uint8_t busid)143 void usb_dc_low_level_init(uint8_t busid)
144 {
145 esp_err_t ret;
146 void *reg_base = (void*)g_usbdev_bus[busid].reg_base;
147 (void)reg_base;
148 usb_phy_config_t phy_config = {
149 .controller = USB_PHY_CTRL_OTG,
150 .otg_mode = USB_OTG_MODE_DEVICE,
151 };
152 phy_config.target = GET_USB_PHY_TARGET(reg_base);
153 phy_config.otg_speed = GET_USB_PHY_SPEED(reg_base);
154
155 ret = usb_new_phy(&phy_config, &s_phy_handle[GET_USB_INDEX(reg_base)]);
156 if (ret != ESP_OK) {
157 USB_LOG_ERR("USB Phy Init Failed!\r\n");
158 return;
159 }
160
161 uintptr_t arg = busid;
162 // TODO: Check when to enable interrupt
163 ret = esp_intr_alloc(GET_USB_INTR_SOURCE(reg_base), ESP_INTR_FLAG_LOWMED, usb_dc_interrupt_cb, (void *)arg, &s_interrupt_handle[GET_USB_INDEX(reg_base)]);
164 if (ret != ESP_OK) {
165 USB_LOG_ERR("USB Interrupt Init Failed!\r\n");
166 return;
167 }
168 USB_LOG_INFO("cherryusb, version: " CHERRYUSB_VERSION_STR "\r\n");
169 }
170
usb_dc_low_level_deinit(uint8_t busid)171 void usb_dc_low_level_deinit(uint8_t busid)
172 {
173 void *reg_base = (void*)g_usbdev_bus[busid].reg_base;
174 (void)reg_base;
175 if (s_interrupt_handle[GET_USB_INDEX(reg_base)]) {
176 esp_intr_free(s_interrupt_handle[GET_USB_INDEX(reg_base)]);
177 s_interrupt_handle[GET_USB_INDEX(reg_base)] = NULL;
178 }
179 if (s_phy_handle[GET_USB_INDEX(reg_base)]) {
180 usb_del_phy(s_phy_handle[GET_USB_INDEX(reg_base)]);
181 s_phy_handle[GET_USB_INDEX(reg_base)] = NULL;
182 }
183 }
184
usb_hc_interrupt_cb(void * arg_pv)185 static void usb_hc_interrupt_cb(void *arg_pv)
186 {
187 extern void USBH_IRQHandler(uint8_t busid);
188 uint8_t busid = (uintptr_t)arg_pv;
189 USBH_IRQHandler(busid);
190 }
191
usb_hc_low_level_init(struct usbh_bus * bus)192 void usb_hc_low_level_init(struct usbh_bus *bus)
193 {
194 void *reg_base = (void*)bus->hcd.reg_base;
195 (void)reg_base;
196 // Host Library defaults to internal PHY
197 usb_phy_config_t phy_config = {
198 .controller = USB_PHY_CTRL_OTG,
199 .otg_mode = USB_OTG_MODE_HOST,
200 .otg_speed = USB_PHY_SPEED_UNDEFINED, // In Host mode, the speed is determined by the connected device
201 .ext_io_conf = NULL,
202 .otg_io_conf = NULL,
203 };
204 phy_config.target = GET_USB_PHY_TARGET(reg_base);
205
206 esp_err_t ret = usb_new_phy(&phy_config, &s_phy_handle[GET_USB_INDEX(reg_base)]);
207 if (ret != ESP_OK) {
208 USB_LOG_ERR("USB Phy Init Failed!\r\n");
209 return;
210 }
211
212 uintptr_t arg = bus->busid;
213 // TODO: Check when to enable interrupt
214 ret = esp_intr_alloc(GET_USB_INTR_SOURCE(reg_base), ESP_INTR_FLAG_LOWMED, usb_hc_interrupt_cb, (void*)(arg), &s_interrupt_handle[GET_USB_INDEX(reg_base)]);
215 if (ret != ESP_OK) {
216 USB_LOG_ERR("USB Interrupt Init Failed!\r\n");
217 return;
218 }
219 USB_LOG_INFO("cherryusb, version: " CHERRYUSB_VERSION_STR "\r\n");
220 }
221
usb_hc_low_level_deinit(struct usbh_bus * bus)222 void usb_hc_low_level_deinit(struct usbh_bus *bus)
223 {
224 void *reg_base = (void*)bus->hcd.reg_base;
225 (void)reg_base;
226 if (s_interrupt_handle[GET_USB_INDEX(reg_base)]) {
227 esp_intr_free(s_interrupt_handle[GET_USB_INDEX(reg_base)]);
228 s_interrupt_handle[GET_USB_INDEX(reg_base)] = NULL;
229 }
230 if (s_phy_handle[GET_USB_INDEX(reg_base)]) {
231 usb_del_phy(s_phy_handle[GET_USB_INDEX(reg_base)]);
232 s_phy_handle[GET_USB_INDEX(reg_base)] = NULL;
233 }
234 }
235
dwc2_get_user_params(uint32_t reg_base,struct dwc2_user_params * params)236 void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params)
237 {
238 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
239 memcpy(params, ¶m_fs, sizeof(struct dwc2_user_params));
240 #elif CONFIG_IDF_TARGET_ESP32P4
241 if (reg_base == ESP_USB_HS0_BASE) {
242 memcpy(params, ¶m_hs, sizeof(struct dwc2_user_params));
243 } else {
244 memcpy(params, ¶m_fs, sizeof(struct dwc2_user_params));
245 }
246 #endif
247 #ifdef CONFIG_USB_DWC2_CUSTOM_FIFO
248 struct usb_dwc2_user_fifo_config s_dwc2_fifo_config;
249
250 dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config);
251
252 params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size;
253 for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++)
254 {
255 params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i];
256 }
257 #endif
258 }
259
usbd_dwc2_delay_ms(uint8_t ms)260 void usbd_dwc2_delay_ms(uint8_t ms)
261 {
262 vTaskDelay(pdMS_TO_TICKS(ms));
263 }
264
265 #ifdef CONFIG_USB_DCACHE_ENABLE
266 #include "esp_cache.h"
267
usb_dcache_clean(uintptr_t addr,size_t size)268 void usb_dcache_clean(uintptr_t addr, size_t size)
269 {
270 if (size == 0)
271 return;
272
273 esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M);
274 }
275
usb_dcache_invalidate(uintptr_t addr,size_t size)276 void usb_dcache_invalidate(uintptr_t addr, size_t size)
277 {
278 if (size == 0)
279 return;
280
281 esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C);
282 }
283
usb_dcache_flush(uintptr_t addr,size_t size)284 void usb_dcache_flush(uintptr_t addr, size_t size)
285 {
286 if (size == 0)
287 return;
288
289 esp_cache_msync((void *)addr, size, ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C);
290 }
291 #endif