1 /* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are met:
5 * 1. Redistributions of source code must retain the above copyright
6 * notice, this list of conditions and the following disclaimer.
7 * 2. Redistributions in binary form must reproduce the above copyright
8 * notice, this list of conditions and the following disclaimer in the
9 * documentation and/or other materials provided with the distribution.
10 *
11 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
12 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
13 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
15 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
16 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
17 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
22 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
23 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 #include <rtthread.h>
27 #include <rthw.h>
28 #include "usbd_core.h"
29 #include "usbh_core.h"
30 #include "usb_dwc2_param.h"
31
32 #include <riscv_io.h>
33 #include "sysctl_rst.h"
34 #include "ioremap.h"
35 #include "mmu.h"
36 #include "cache.h"
37
38 extern rt_mmu_info mmu_info;
39
40 #if defined(ENABLE_CHERRY_USB) || defined(PKG_USING_CHERRYUSB) || defined(RT_USING_CHERRYUSB)
41 #define DEFAULT_USB_HCLK_FREQ_MHZ 200
42
43 uint32_t SystemCoreClock = (DEFAULT_USB_HCLK_FREQ_MHZ * 1000 * 1000);
44
45 const uintptr_t usb_dev_addr[2] = { 0x91500000UL, 0x91540000UL };
46
47 #define USB_IDPULLUP0 (1 << 4)
48 #define USB_DMPULLDOWN0 (1 << 8)
49 #define USB_DPPULLDOWN0 (1 << 9)
50
51 const struct dwc2_user_params param_common = {
52 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
53 #ifdef CONFIG_USB_DWC2_DMA_ENABLE
54 .device_dma_enable = true,
55 #else
56 .device_dma_enable = false,
57 #endif
58 .device_dma_desc_enable = false,
59 .device_rx_fifo_size = (3016 - 16 - 256 * 8),
60 .device_tx_fifo_size = {
61 [0] = 16, // 64 byte
62 [1] = 512, // 1024 byte, double buffer
63 [2] = 256, // 1024 byte
64 [3] = 512, // 1024 byte, double buffer
65 [4] = 256, // 1024 byte
66 [5] = 256, // 1024 byte
67 [6] = 256, // 1024 byte
68 [7] = 0,
69 [8] = 0,
70 [9] = 0,
71 [10] = 0,
72 [11] = 0,
73 [12] = 0,
74 [13] = 0,
75 [14] = 0,
76 [15] = 0 },
77
78 .host_dma_desc_enable = false,
79 .host_rx_fifo_size = 3016 - 128 * 2 - 256 * 2,
80 .host_nperio_tx_fifo_size = 128 * 2, // 512 byte, double buffer
81 .host_perio_tx_fifo_size = 256 * 2, // 1024 byte, double buffer
82
83 .device_gccfg = 0,
84 .host_gccfg = 0
85 };
86
87 #ifndef CONFIG_USB_DWC2_CUSTOM_PARAM
dwc2_get_user_params(uint32_t reg_base,struct dwc2_user_params * params)88 void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params)
89 {
90 memcpy(params, ¶m_common, sizeof(struct dwc2_user_params));
91 #ifdef CONFIG_USB_DWC2_CUSTOM_FIFO
92 struct usb_dwc2_user_fifo_config s_dwc2_fifo_config;
93
94 dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config);
95
96 params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size;
97 for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++) {
98 params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i];
99 }
100 #endif
101 }
102 #endif
103
104 // USB Host
105 #if defined(ENABLE_CHERRY_USB_HOST) || defined(PKG_CHERRYUSB_HOST) || defined(RT_CHERRYUSB_HOST)
usb_hc_interrupt_cb(int irq,void * arg_pv)106 static void usb_hc_interrupt_cb(int irq, void *arg_pv)
107 {
108 USBH_IRQHandler((uint8_t)(uintptr_t)arg_pv);
109 }
110
usb_hc_low_level_init(struct usbh_bus * bus)111 void usb_hc_low_level_init(struct usbh_bus *bus)
112 {
113 uint32_t *hs_reg;
114 uint32_t usb_ctl3;
115
116 if ((uintptr_t)rt_hw_mmu_v2p(&mmu_info, (void *)bus->hcd.reg_base) == usb_dev_addr[0]) {
117 if (!sysctl_reset(SYSCTL_RESET_USB0)) {
118 USB_LOG_ERR("reset usb0 fail\n");
119 }
120
121 hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x7C), 0x1000);
122 usb_ctl3 = *hs_reg | USB_IDPULLUP0;
123
124 *hs_reg = usb_ctl3 | (USB_DMPULLDOWN0 | USB_DPPULLDOWN0);
125
126 rt_iounmap(hs_reg);
127
128 rt_hw_interrupt_install(173, usb_hc_interrupt_cb, (void *)(uintptr_t)bus->hcd.hcd_id, "usbh0");
129 rt_hw_interrupt_umask(173);
130
131 } else {
132 if (!sysctl_reset(SYSCTL_RESET_USB1)) {
133 USB_LOG_ERR("reset usb1 fail\n");
134 }
135
136 hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x9C), 0x1000);
137 usb_ctl3 = *hs_reg | USB_IDPULLUP0;
138
139 *hs_reg = usb_ctl3 | (USB_DMPULLDOWN0 | USB_DPPULLDOWN0);
140
141 rt_iounmap(hs_reg);
142
143 rt_hw_interrupt_install(174, usb_hc_interrupt_cb, (void *)(uintptr_t)bus->hcd.hcd_id, "usbh1");
144 rt_hw_interrupt_umask(174);
145 }
146 }
147
usb_hc_low_level_deinit(struct usbh_bus * bus)148 void usb_hc_low_level_deinit(struct usbh_bus *bus)
149 {
150 if ((uintptr_t)rt_hw_mmu_v2p(&mmu_info, (void *)bus->hcd.reg_base) == usb_dev_addr[0]) {
151 rt_hw_interrupt_mask(173);
152 } else {
153 rt_hw_interrupt_mask(174);
154 }
155 }
156 #endif // ENABLE_CHERRY_USB_HOST
157
158 // USB Device
159 #if defined(ENABLE_CHERRY_USB_DEVICE) || defined(PKG_CHERRYUSB_DEVICE) || defined(RT_CHERRYUSB_DEVICE)
usb_dc_interrupt_cb(int irq,void * arg_pv)160 static void usb_dc_interrupt_cb(int irq, void *arg_pv)
161 {
162 USBD_IRQHandler((uint8_t)(uintptr_t)arg_pv);
163 }
164
usb_dc_low_level_init(uint8_t busid)165 void usb_dc_low_level_init(uint8_t busid)
166 {
167 if ((uintptr_t)rt_hw_mmu_v2p(&mmu_info, (void *)g_usbdev_bus[busid].reg_base) == usb_dev_addr[0]) {
168 if (!sysctl_reset(SYSCTL_RESET_USB0)) {
169 USB_LOG_ERR("reset usb0 fail\n");
170 }
171
172 uint32_t *hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x7C), 0x1000);
173 *hs_reg = 0x37;
174 rt_iounmap(hs_reg);
175
176 rt_hw_interrupt_install(173, usb_dc_interrupt_cb, (void *)(uintptr_t)busid, "usbd0");
177 rt_hw_interrupt_umask(173);
178 } else {
179 if (!sysctl_reset(SYSCTL_RESET_USB1)) {
180 USB_LOG_ERR("reset usb1 fail\n");
181 }
182
183 uint32_t *hs_reg = (uint32_t *)rt_ioremap((void *)(0x91585000 + 0x9C), 0x1000);
184 *hs_reg = 0x37;
185 rt_iounmap(hs_reg);
186
187 rt_hw_interrupt_install(174, usb_dc_interrupt_cb, (void *)(uintptr_t)busid, "usbd1");
188 rt_hw_interrupt_umask(174);
189 }
190 }
191
usb_dc_low_level_deinit(uint8_t busid)192 void usb_dc_low_level_deinit(uint8_t busid)
193 {
194 if ((uintptr_t)rt_hw_mmu_v2p(&mmu_info, (void *)g_usbdev_bus[busid].reg_base) == usb_dev_addr[0]) {
195 rt_hw_interrupt_mask(173);
196 } else {
197 rt_hw_interrupt_mask(174);
198 }
199 }
200 #endif // ENABLE_CHERRY_USB_DEVICE
201
usbd_dwc2_delay_ms(uint8_t ms)202 void usbd_dwc2_delay_ms(uint8_t ms)
203 {
204 rt_thread_mdelay(ms);
205 }
206
207 #ifdef CONFIG_USB_DCACHE_ENABLE
usb_dcache_clean(uintptr_t addr,size_t size)208 void usb_dcache_clean(uintptr_t addr, size_t size)
209 {
210 rt_hw_cpu_dcache_clean((void *)addr, size);
211 }
212
usb_dcache_invalidate(uintptr_t addr,size_t size)213 void usb_dcache_invalidate(uintptr_t addr, size_t size)
214 {
215 rt_hw_cpu_dcache_invalidate((void *)addr, size);
216 }
217
usb_dcache_flush(uintptr_t addr,size_t size)218 void usb_dcache_flush(uintptr_t addr, size_t size)
219 {
220 rt_hw_cpu_dcache_clean_flush((void *)addr, size);
221 }
222 #endif
223
224 #endif // ENABLE_CHERRY_USB
225