1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: pwm3_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for pwm3 module.
pwm3_iomux_config(void)34 void pwm3_iomux_config(void)
35 {
36 // Config pwm3.PWM3_OUT to pad SD4_DATA1(B19)
37 // HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_WR(0x00000002);
38 // HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR(0x0001B0B0);
39 // Mux Register:
40 // IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1(0x020E0344)
41 // SION [4] - Software Input On Field Reset: DISABLED
42 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
43 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
44 // ENABLED (1) - Force input path of pad.
45 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
46 // Select iomux modes to be used for pad.
47 // ALT1 (1) - Select instance: usdhc4 signal: SD4_DATA1
48 // ALT2 (2) - Select instance: pwm3 signal: PWM3_OUT
49 // ALT5 (5) - Select instance: gpio2 signal: GPIO2_IO09
50 HW_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_WR(
51 BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_SION_V(DISABLED) |
52 BF_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_MUX_MODE_V(ALT2));
53 // Pad Control Register:
54 // IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1(0x020E072C)
55 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
56 // DISABLED (0) - CMOS input
57 // ENABLED (1) - Schmitt trigger input
58 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
59 // 100K_OHM_PD (0) - 100K Ohm Pull Down
60 // 47K_OHM_PU (1) - 47K Ohm Pull Up
61 // 100K_OHM_PU (2) - 100K Ohm Pull Up
62 // 22K_OHM_PU (3) - 22K Ohm Pull Up
63 // PUE [13] - Pull / Keep Select Field Reset: PULL
64 // KEEP (0) - Keeper Enabled
65 // PULL (1) - Pull Enabled
66 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
67 // DISABLED (0) - Pull/Keeper Disabled
68 // ENABLED (1) - Pull/Keeper Enabled
69 // ODE [11] - Open Drain Enable Field Reset: DISABLED
70 // Enables open drain of the pin.
71 // DISABLED (0) - Output is CMOS.
72 // ENABLED (1) - Output is Open Drain.
73 // SPEED [7:6] - Speed Field Reset: 100MHZ
74 // RESERVED0 (0) - Reserved
75 // 50MHZ (1) - Low (50 MHz)
76 // 100MHZ (2) - Medium (100 MHz)
77 // 200MHZ (3) - Maximum (200 MHz)
78 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
79 // HIZ (0) - HI-Z
80 // 240_OHM (1) - 240 Ohm
81 // 120_OHM (2) - 120 Ohm
82 // 80_OHM (3) - 80 Ohm
83 // 60_OHM (4) - 60 Ohm
84 // 48_OHM (5) - 48 Ohm
85 // 40_OHM (6) - 40 Ohm
86 // 34_OHM (7) - 34 Ohm
87 // SRE [0] - Slew Rate Field Reset: SLOW
88 // Slew rate control.
89 // SLOW (0) - Slow Slew Rate
90 // FAST (1) - Fast Slew Rate
91 HW_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_WR(
92 BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_HYS_V(ENABLED) |
93 BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUS_V(100K_OHM_PU) |
94 BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PUE_V(PULL) |
95 BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_PKE_V(ENABLED) |
96 BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_ODE_V(DISABLED) |
97 BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SPEED_V(100MHZ) |
98 BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_DSE_V(40_OHM) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_SRE_V(SLOW));
100 }
101