1 /** 2 * @file pwrseq_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 4 */ 5 6 /* **************************************************************************** 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included 17 * in all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Except as contained in this notice, the name of Maxim Integrated 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated 29 * Products, Inc. Branding Policy. 30 * 31 * The mere transfer of this software does not imply any licenses 32 * of trade secrets, proprietary technology, copyrights, patents, 33 * trademarks, maskwork rights, or any other form of intellectual 34 * property whatsoever. Maxim Integrated Products, Inc. retains all 35 * ownership rights. 36 * 37 * 38 *************************************************************************** */ 39 40 #ifndef _PWRSEQ_REGS_H_ 41 #define _PWRSEQ_REGS_H_ 42 43 /* **** Includes **** */ 44 #include <stdint.h> 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 #if defined (__ICCARM__) 51 #pragma system_include 52 #endif 53 54 #if defined (__CC_ARM) 55 #pragma anon_unions 56 #endif 57 /// @cond 58 /* 59 If types are not defined elsewhere (CMSIS) define them here 60 */ 61 #ifndef __IO 62 #define __IO volatile 63 #endif 64 #ifndef __I 65 #define __I volatile const 66 #endif 67 #ifndef __O 68 #define __O volatile 69 #endif 70 #ifndef __R 71 #define __R volatile const 72 #endif 73 /// @endcond 74 75 /* **** Definitions **** */ 76 77 /** 78 * @ingroup pwrseq 79 * @defgroup pwrseq_registers PWRSEQ_Registers 80 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 81 * @details Power Sequencer / Low Power Control Register. 82 */ 83 84 /** 85 * @ingroup pwrseq_registers 86 * Structure type to access the PWRSEQ Registers. 87 */ 88 typedef struct { 89 __IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */ 90 __IO uint32_t lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */ 91 __IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */ 92 __R uint32_t rsv_0xc_0x3f[13]; 93 __IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */ 94 } mxc_pwrseq_regs_t; 95 96 /* Register offsets for module PWRSEQ */ 97 /** 98 * @ingroup pwrseq_registers 99 * @defgroup PWRSEQ_Register_Offsets Register Offsets 100 * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. 101 * @{ 102 */ 103 #define MXC_R_PWRSEQ_LP_CTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */ 104 #define MXC_R_PWRSEQ_LP_WAKEFL ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */ 105 #define MXC_R_PWRSEQ_LPWK_EN ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */ 106 #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */ 107 /**@} end of group pwrseq_registers */ 108 109 /** 110 * @ingroup pwrseq_registers 111 * @defgroup PWRSEQ_LP_CTRL PWRSEQ_LP_CTRL 112 * @brief Low Power Control Register. 113 * @{ 114 */ 115 #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS 0 /**< LP_CTRL_RAMRET_SEL0 Position */ 116 #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< LP_CTRL_RAMRET_SEL0 Mask */ 117 #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */ 118 #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS Setting */ 119 #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */ 120 #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN Setting */ 121 122 #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS 1 /**< LP_CTRL_RAMRET_SEL1 Position */ 123 #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< LP_CTRL_RAMRET_SEL1 Mask */ 124 #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */ 125 #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS Setting */ 126 #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */ 127 #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN Setting */ 128 129 #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS 2 /**< LP_CTRL_RAMRET_SEL2 Position */ 130 #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< LP_CTRL_RAMRET_SEL2 Mask */ 131 #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */ 132 #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS Setting */ 133 #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */ 134 #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN Setting */ 135 136 #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS 3 /**< LP_CTRL_RAMRET_SEL3 Position */ 137 #define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< LP_CTRL_RAMRET_SEL3 Mask */ 138 #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */ 139 #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS Setting */ 140 #define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */ 141 #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN Setting */ 142 143 #define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */ 144 #define MXC_F_PWRSEQ_LP_CTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */ 145 #define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */ 146 #define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */ 147 #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */ 148 #define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */ 149 #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */ 150 #define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */ 151 152 #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */ 153 #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< LP_CTRL_VCORE_DET_BYPASS Mask */ 154 #define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */ 155 #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Setting */ 156 #define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */ 157 #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Setting */ 158 159 #define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS 8 /**< LP_CTRL_RETREG_EN Position */ 160 #define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN Mask */ 161 #define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS ((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */ 162 #define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS Setting */ 163 #define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN ((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */ 164 #define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN Setting */ 165 166 #define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS 10 /**< LP_CTRL_FAST_WK_EN Position */ 167 #define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< LP_CTRL_FAST_WK_EN Mask */ 168 #define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS ((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */ 169 #define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS Setting */ 170 #define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN ((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */ 171 #define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN Setting */ 172 173 #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */ 174 #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF Mask */ 175 #define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON ((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */ 176 #define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */ 177 #define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF ((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */ 178 #define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting */ 179 180 #define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS 12 /**< LP_CTRL_VCORE_POR_DIS Position */ 181 #define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< LP_CTRL_VCORE_POR_DIS Mask */ 182 #define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */ 183 #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< LP_CTRL_VCORE_POR_DIS_DIS Setting */ 184 #define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */ 185 #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< LP_CTRL_VCORE_POR_DIS_EN Setting */ 186 187 #define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS 16 /**< LP_CTRL_LDO_DIS Position */ 188 #define MXC_F_PWRSEQ_LP_CTRL_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS Mask */ 189 #define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */ 190 #define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting */ 191 #define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */ 192 #define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting */ 193 194 #define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS 20 /**< LP_CTRL_VCORE_SVM_DIS Position */ 195 #define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< LP_CTRL_VCORE_SVM_DIS Mask */ 196 #define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */ 197 #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< LP_CTRL_VCORE_SVM_DIS_EN Setting */ 198 #define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */ 199 #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< LP_CTRL_VCORE_SVM_DIS_DIS Setting */ 200 201 #define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS 25 /**< LP_CTRL_VDDIO_POR_DIS Position */ 202 #define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< LP_CTRL_VDDIO_POR_DIS Mask */ 203 #define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN ((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */ 204 #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< LP_CTRL_VDDIO_POR_DIS_EN Setting */ 205 #define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS ((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */ 206 #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< LP_CTRL_VDDIO_POR_DIS_DIS Setting */ 207 208 /**@} end of group PWRSEQ_LP_CTRL_Register */ 209 210 /** 211 * @ingroup pwrseq_registers 212 * @defgroup PWRSEQ_LP_WAKEFL PWRSEQ_LP_WAKEFL 213 * @brief Low Power Mode Wakeup Flags for GPIO0 214 * @{ 215 */ 216 #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */ 217 #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST Mask */ 218 219 /**@} end of group PWRSEQ_LP_WAKEFL_Register */ 220 221 /** 222 * @ingroup pwrseq_registers 223 * @defgroup PWRSEQ_LPWK_EN PWRSEQ_LPWK_EN 224 * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup 225 * functionality for GPIO0. 226 * @{ 227 */ 228 #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */ 229 #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN Mask */ 230 231 /**@} end of group PWRSEQ_LPWK_EN_Register */ 232 233 /** 234 * @ingroup pwrseq_registers 235 * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD 236 * @brief Low Power Memory Shutdown Control. 237 * @{ 238 */ 239 #define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS 0 /**< LPMEMSD_SRAM0_OFF Position */ 240 #define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF Mask */ 241 #define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */ 242 #define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL Setting */ 243 #define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */ 244 #define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Setting */ 245 246 #define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS 1 /**< LPMEMSD_SRAM1_OFF Position */ 247 #define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF Mask */ 248 #define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */ 249 #define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL Setting */ 250 #define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */ 251 #define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Setting */ 252 253 #define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS 2 /**< LPMEMSD_SRAM2_OFF Position */ 254 #define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF Mask */ 255 #define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */ 256 #define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL Setting */ 257 #define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */ 258 #define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Setting */ 259 260 #define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS 3 /**< LPMEMSD_SRAM3_OFF Position */ 261 #define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF Mask */ 262 #define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL ((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */ 263 #define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL Setting */ 264 #define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN ((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */ 265 #define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Setting */ 266 267 /**@} end of group PWRSEQ_LPMEMSD_Register */ 268 269 #ifdef __cplusplus 270 } 271 #endif 272 273 #endif /* _PWRSEQ_REGS_H_ */ 274