1 /*""FILE COMMENT""******************************************************* 2 * System Name : POE API for RX62Nxx 3 * File Name : r_pdl_poe.h 4 * Version : 1.02 5 * Contents : POE API header 6 * Customer : 7 * Model : 8 * Order : 9 * CPU : RX 10 * Compiler : RXC 11 * OS : Nothing 12 * Programmer : 13 * Note : 14 ************************************************************************ 15 * Copyright, 2011. Renesas Electronics Corporation 16 * and Renesas Solutions Corporation 17 ************************************************************************ 18 * History : 2011.04.08 19 * : Ver 1.02 20 * : CS-5 release. 21 *""FILE COMMENT END""**************************************************/ 22 23 #ifndef R_PDL_POE_H 24 #define R_PDL_POE_H 25 26 #include "r_pdl_common_defs_RX62Nxx.h" 27 28 /* Function prototypes */ 29 bool R_POE_Set( 30 uint32_t, 31 uint8_t, 32 uint32_t 33 ); 34 bool R_POE_Create( 35 uint16_t, 36 void *, 37 void *, 38 void *, 39 void *, 40 uint8_t 41 ); 42 bool POE_Control( 43 uint8_t, 44 uint16_t, 45 uint16_t 46 ); 47 bool R_POE_GetStatus( 48 uint16_t * 49 ); 50 51 /* Pin selection */ 52 #define PDL_POE_PINS_0_TO_3 0x01u 53 #define PDL_POE_PINS_4_TO_7 0x02u 54 #define PDL_POE_PIN_8 0x04u 55 #define PDL_POE_PIN_9 0x08u 56 57 /* Input pin detection */ 58 #define PDL_POE_0_MODE_EDGE 0x00000001ul 59 #define PDL_POE_0_MODE_LOW_8 0x00000002ul 60 #define PDL_POE_0_MODE_LOW_16 0x00000004ul 61 #define PDL_POE_0_MODE_LOW_128 0x00000008ul 62 63 #define PDL_POE_1_MODE_EDGE 0x00000010ul 64 #define PDL_POE_1_MODE_LOW_8 0x00000020ul 65 #define PDL_POE_1_MODE_LOW_16 0x00000040ul 66 #define PDL_POE_1_MODE_LOW_128 0x00000080ul 67 68 #define PDL_POE_2_MODE_EDGE 0x00000100ul 69 #define PDL_POE_2_MODE_LOW_8 0x00000200ul 70 #define PDL_POE_2_MODE_LOW_16 0x00000400ul 71 #define PDL_POE_2_MODE_LOW_128 0x00000800ul 72 73 #define PDL_POE_3_MODE_EDGE 0x00001000ul 74 #define PDL_POE_3_MODE_LOW_8 0x00002000ul 75 #define PDL_POE_3_MODE_LOW_16 0x00004000ul 76 #define PDL_POE_3_MODE_LOW_128 0x00008000ul 77 78 #define PDL_POE_4_MODE_EDGE 0x00010000ul 79 #define PDL_POE_4_MODE_LOW_8 0x00020000ul 80 #define PDL_POE_4_MODE_LOW_16 0x00040000ul 81 #define PDL_POE_4_MODE_LOW_128 0x00080000ul 82 83 #define PDL_POE_5_MODE_EDGE 0x00100000ul 84 #define PDL_POE_5_MODE_LOW_8 0x00200000ul 85 #define PDL_POE_5_MODE_LOW_16 0x00400000ul 86 #define PDL_POE_5_MODE_LOW_128 0x00800000ul 87 88 #define PDL_POE_6_MODE_EDGE 0x01000000ul 89 #define PDL_POE_6_MODE_LOW_8 0x02000000ul 90 #define PDL_POE_6_MODE_LOW_16 0x04000000ul 91 #define PDL_POE_6_MODE_LOW_128 0x08000000ul 92 93 #define PDL_POE_7_MODE_EDGE 0x10000000ul 94 #define PDL_POE_7_MODE_LOW_8 0x20000000ul 95 #define PDL_POE_7_MODE_LOW_16 0x40000000ul 96 #define PDL_POE_7_MODE_LOW_128 0x80000000ul 97 98 #define PDL_POE_8_MODE_EDGE 0x01u 99 #define PDL_POE_8_MODE_LOW_8 0x02u 100 #define PDL_POE_8_MODE_LOW_16 0x04u 101 #define PDL_POE_8_MODE_LOW_128 0x08u 102 103 #define PDL_POE_9_MODE_EDGE 0x10u 104 #define PDL_POE_9_MODE_LOW_8 0x20u 105 #define PDL_POE_9_MODE_LOW_16 0x40u 106 #define PDL_POE_9_MODE_LOW_128 0x80u 107 108 /* Pin output control */ 109 110 /* High impedance request detection */ 111 #define PDL_POE_HI_Z_REQ_8_ENABLE 0x00000001ul 112 #define PDL_POE_HI_Z_REQ_MTIOC0A 0x00000002ul 113 #define PDL_POE_HI_Z_REQ_MTIOC0B 0x00000004ul 114 #define PDL_POE_HI_Z_REQ_MTIOC0C 0x00000008ul 115 #define PDL_POE_HI_Z_REQ_MTIOC0D 0x00000010ul 116 117 #define PDL_POE_HI_Z_REQ_9_ENABLE 0x00000020ul 118 #define PDL_POE_HI_Z_REQ_MTIOC6A 0x00000040ul 119 #define PDL_POE_HI_Z_REQ_MTIOC6B 0x00000080ul 120 #define PDL_POE_HI_Z_REQ_MTIOC6C 0x00000100ul 121 #define PDL_POE_HI_Z_REQ_MTIOC6D 0x00000200ul 122 123 /* Output short detection */ 124 #define PDL_POE_SHORT_3_4_HI_Z 0x00000400ul 125 #define PDL_POE_SHORT_MTIOC4BD_B 0x00000800ul 126 #define PDL_POE_SHORT_MTIOC4AC_B 0x00001000ul 127 #define PDL_POE_SHORT_MTIOC3BD_B 0x00002000ul 128 #define PDL_POE_SHORT_MTIOC4BD_A 0x00004000ul 129 #define PDL_POE_SHORT_MTIOC4AC_A 0x00008000ul 130 #define PDL_POE_SHORT_MTIOC3BD_A 0x00010000ul 131 132 #define PDL_POE_SHORT_9_10_HI_Z 0x00020000ul 133 #define PDL_POE_SHORT_MTIOC10BD 0x00040000ul 134 #define PDL_POE_SHORT_MTIOC10AC 0x00080000ul 135 #define PDL_POE_SHORT_MTIOC9BD 0x00100000ul 136 137 /* High impedance request response */ 138 #define PDL_POE_IRQ_HI_Z_0_3_DISABLE 0x0001u 139 #define PDL_POE_IRQ_HI_Z_0_3_ENABLE 0x0002u 140 #define PDL_POE_IRQ_HI_Z_4_7_DISABLE 0x0004u 141 #define PDL_POE_IRQ_HI_Z_4_7_ENABLE 0x0008u 142 #define PDL_POE_IRQ_HI_Z_8_DISABLE 0x0010u 143 #define PDL_POE_IRQ_HI_Z_8_ENABLE 0x0020u 144 #define PDL_POE_IRQ_HI_Z_9_DISABLE 0x0040u 145 #define PDL_POE_IRQ_HI_Z_9_ENABLE 0x0080u 146 147 /* Output short detection response */ 148 #define PDL_POE_IRQ_SHORT_3_4_ENABLE 0x0100u 149 #define PDL_POE_IRQ_SHORT_3_4_DISABLE 0x0200u 150 #define PDL_POE_IRQ_SHORT_9_10_ENABLE 0x0400u 151 #define PDL_POE_IRQ_SHORT_9_10_DISABLE 0x0800u 152 153 /* MTU channel high impedance control */ 154 #define PDL_POE_MTU3_MTU4_HI_Z_ON 0x01u 155 #define PDL_POE_MTU3_MTU4_HI_Z_OFF 0x02u 156 #define PDL_POE_MTU0_HI_Z_ON 0x04u 157 #define PDL_POE_MTU0_HI_Z_OFF 0x08u 158 #define PDL_POE_MTU9_MTU10_HI_Z_ON 0x10u 159 #define PDL_POE_MTU9_MTU10_HI_Z_OFF 0x20u 160 #define PDL_POE_MTU6_HI_Z_ON 0x40u 161 #define PDL_POE_MTU6_HI_Z_OFF 0x80u 162 163 /* Event flag control */ 164 #define PDL_POE_FLAG_POE0_CLEAR 0x0001u 165 #define PDL_POE_FLAG_POE1_CLEAR 0x0002u 166 #define PDL_POE_FLAG_POE2_CLEAR 0x0004u 167 #define PDL_POE_FLAG_POE3_CLEAR 0x0008u 168 #define PDL_POE_FLAG_POE4_CLEAR 0x0010u 169 #define PDL_POE_FLAG_POE5_CLEAR 0x0020u 170 #define PDL_POE_FLAG_POE6_CLEAR 0x0040u 171 #define PDL_POE_FLAG_POE7_CLEAR 0x0080u 172 #define PDL_POE_FLAG_POE8_CLEAR 0x0100u 173 #define PDL_POE_FLAG_POE9_CLEAR 0x0200u 174 #define PDL_POE_FLAG_SHORT_3_4_CLEAR 0x0400u 175 #define PDL_POE_FLAG_SHORT_9_10_CLEAR 0x0800u 176 177 #endif 178 /* End of file */ 179