1 /*""FILE COMMENT""******************************************************* 2 * System Name : Serial Peripheral Interface API for RX62Nxx 3 * File Name : r_pdl_spi.h 4 * Version : 1.02 5 * Contents : SPI API header 6 * Customer : 7 * Model : 8 * Order : 9 * CPU : RX 10 * Compiler : RXC 11 * OS : Nothing 12 * Programmer : 13 * Note : 14 ************************************************************************ 15 * Copyright, 2011. Renesas Electronics Corporation 16 * and Renesas Solutions Corporation 17 ************************************************************************ 18 * History : 2011.04.08 19 * : Ver 1.02 20 * : CS-5 release. 21 *""FILE COMMENT END""**************************************************/ 22 23 #ifndef R_PDL_SPI_H 24 #define R_PDL_SPI_H 25 26 #include "r_pdl_common_defs_RX62Nxx.h" 27 28 /* Function prototypes */ 29 bool R_SPI_Create( 30 uint8_t, 31 uint32_t, 32 uint32_t, 33 uint32_t, 34 uint32_t 35 ); 36 bool R_SPI_Destroy( 37 uint8_t 38 ); 39 bool R_SPI_Command( 40 uint8_t, 41 uint8_t, 42 uint32_t, 43 uint8_t 44 ); 45 bool R_SPI_Transfer( 46 uint8_t, 47 uint8_t, 48 uint32_t *, 49 uint32_t *, 50 uint16_t, 51 void *, 52 uint8_t 53 ); 54 bool R_SPI_Control( 55 uint8_t, 56 uint8_t, 57 uint32_t 58 ); 59 bool R_SPI_GetStatus( 60 uint8_t, 61 uint16_t *, 62 uint16_t * 63 ); 64 65 /* Connection mode */ 66 #define PDL_SPI_MODE_SPI_MASTER 0x00000001ul 67 #define PDL_SPI_MODE_SPI_MULTI_MASTER 0x00000002ul 68 #define PDL_SPI_MODE_SPI_SLAVE 0x00000004ul 69 #define PDL_SCI_MODE_SYNC_MASTER 0x00000008ul 70 #define PDL_SCI_MODE_SYNC_SLAVE 0x00000010ul 71 72 /* Reception control */ 73 #define PDL_SPI_FULL_DUPLEX 0x00000020ul 74 #define PDL_SPI_TRANSMIT_ONLY 0x00000040ul 75 76 /* Pin selection and control */ 77 #define PDL_SPI_PIN_CMOS 0x00000080ul 78 #define PDL_SPI_PIN_OPEN_DRAIN 0x00000100ul 79 #define PDL_SPI_PIN_A 0x00000200ul 80 #define PDL_SPI_PIN_B 0x00000400ul 81 #define PDL_SPI_PIN_RSPCK_ENABLE 0x00000800ul 82 #define PDL_SPI_PIN_RSPCK_DISABLE 0x00001000ul 83 #define PDL_SPI_PIN_MOSI_ENABLE 0x00002000ul 84 #define PDL_SPI_PIN_MOSI_DISABLE 0x00004000ul 85 #define PDL_SPI_PIN_MISO_ENABLE 0x00008000ul 86 #define PDL_SPI_PIN_MISO_DISABLE 0x00010000ul 87 #define PDL_SPI_PIN_SSL0_LOW 0x00020000ul 88 #define PDL_SPI_PIN_SSL0_HIGH 0x00040000ul 89 #define PDL_SPI_PIN_SSL0_DISABLE 0x00080000ul 90 #define PDL_SPI_PIN_SSL1_LOW 0x00100000ul 91 #define PDL_SPI_PIN_SSL1_HIGH 0x00200000ul 92 #define PDL_SPI_PIN_SSL1_DISABLE 0x00400000ul 93 #define PDL_SPI_PIN_SSL2_LOW 0x00800000ul 94 #define PDL_SPI_PIN_SSL2_HIGH 0x01000000ul 95 #define PDL_SPI_PIN_SSL2_DISABLE 0x02000000ul 96 #define PDL_SPI_PIN_SSL3_LOW 0x04000000ul 97 #define PDL_SPI_PIN_SSL3_HIGH 0x08000000ul 98 #define PDL_SPI_PIN_SSL3_DISABLE 0x10000000ul 99 #define PDL_SPI_PIN_MOSI_IDLE_LAST 0x20000000ul 100 #define PDL_SPI_PIN_MOSI_IDLE_LOW 0x40000000ul 101 #define PDL_SPI_PIN_MOSI_IDLE_HIGH 0x80000000ul 102 103 /* Buffer size */ 104 #define PDL_SPI_BUFFER_64 0x00000001ul 105 #define PDL_SPI_BUFFER_128 0x00000002ul 106 107 /* Frame configuration selection */ 108 #define PDL_SPI_FRAME_1_1 0x00000004ul 109 #define PDL_SPI_FRAME_1_2 0x00000008ul 110 #define PDL_SPI_FRAME_1_3 0x00000010ul 111 #define PDL_SPI_FRAME_1_4 0x00000020ul 112 #define PDL_SPI_FRAME_2_1 0x00000040ul 113 #define PDL_SPI_FRAME_2_2 0x00000080ul 114 #define PDL_SPI_FRAME_3 0x00000100ul 115 #define PDL_SPI_FRAME_4 0x00000200ul 116 #define PDL_SPI_FRAME_5 0x00000400ul 117 #define PDL_SPI_FRAME_6 0x00000800ul 118 #define PDL_SPI_FRAME_7 0x00001000ul 119 #define PDL_SPI_FRAME_8 0x00002000ul 120 121 /* Parity bit control */ 122 #define PDL_SPI_PARITY_NONE 0x00004000ul 123 #define PDL_SPI_PARITY_EVEN 0x00008000ul 124 #define PDL_SPI_PARITY_ODD 0x00010000ul 125 126 /* Extended clock delay */ 127 #define PDL_SPI_CLOCK_DELAY_1 0x00000001ul 128 #define PDL_SPI_CLOCK_DELAY_2 0x00000002ul 129 #define PDL_SPI_CLOCK_DELAY_3 0x00000004ul 130 #define PDL_SPI_CLOCK_DELAY_4 0x00000008ul 131 #define PDL_SPI_CLOCK_DELAY_5 0x00000010ul 132 #define PDL_SPI_CLOCK_DELAY_6 0x00000020ul 133 #define PDL_SPI_CLOCK_DELAY_7 0x00000040ul 134 #define PDL_SPI_CLOCK_DELAY_8 0x00000080ul 135 136 /* Extended SSL negation delay */ 137 #define PDL_SPI_SSL_DELAY_1 0x00000100ul 138 #define PDL_SPI_SSL_DELAY_2 0x00000200ul 139 #define PDL_SPI_SSL_DELAY_3 0x00000400ul 140 #define PDL_SPI_SSL_DELAY_4 0x00000800ul 141 #define PDL_SPI_SSL_DELAY_5 0x00001000ul 142 #define PDL_SPI_SSL_DELAY_6 0x00002000ul 143 #define PDL_SPI_SSL_DELAY_7 0x00004000ul 144 #define PDL_SPI_SSL_DELAY_8 0x00008000ul 145 146 /* Extended next-access delay */ 147 #define PDL_SPI_NEXT_DELAY_1 0x00010000ul 148 #define PDL_SPI_NEXT_DELAY_2 0x00020000ul 149 #define PDL_SPI_NEXT_DELAY_3 0x00040000ul 150 #define PDL_SPI_NEXT_DELAY_4 0x00080000ul 151 #define PDL_SPI_NEXT_DELAY_5 0x00100000ul 152 #define PDL_SPI_NEXT_DELAY_6 0x00200000ul 153 #define PDL_SPI_NEXT_DELAY_7 0x00400000ul 154 #define PDL_SPI_NEXT_DELAY_8 0x00800000ul 155 156 /* Channel control */ 157 #define PDL_SPI_DISABLE 0x01u 158 159 /* Loopback control */ 160 #define PDL_SPI_LOOPBACK_DISABLE 0x02u 161 #define PDL_SPI_LOOPBACK_DIRECT 0x04u 162 #define PDL_SPI_LOOPBACK_REVERSED 0x08u 163 164 /* Clock phase and polarity */ 165 #define PDL_SPI_CLOCK_MODE_0 0x00000001ul 166 #define PDL_SPI_CLOCK_MODE_1 0x00000002ul 167 #define PDL_SPI_CLOCK_MODE_2 0x00000004ul 168 #define PDL_SPI_CLOCK_MODE_3 0x00000008ul 169 170 /* Clock division */ 171 #define PDL_SPI_DIV_1 0x00000010ul 172 #define PDL_SPI_DIV_2 0x00000020ul 173 #define PDL_SPI_DIV_4 0x00000040ul 174 #define PDL_SPI_DIV_8 0x00000080ul 175 176 /* SSL assertion */ 177 #define PDL_SPI_ASSERT_SSL0 0x00000100ul 178 #define PDL_SPI_ASSERT_SSL1 0x00000200ul 179 #define PDL_SPI_ASSERT_SSL2 0x00000400ul 180 #define PDL_SPI_ASSERT_SSL3 0x00000800ul 181 182 /* SSL negation */ 183 #define PDL_SPI_SSL_NEGATE 0x00001000ul 184 #define PDL_SPI_SSL_KEEP 0x00002000ul 185 186 /* Frame data length */ 187 #define PDL_SPI_LENGTH_8 0x00004000ul 188 #define PDL_SPI_LENGTH_9 0x00008000ul 189 #define PDL_SPI_LENGTH_10 0x00010000ul 190 #define PDL_SPI_LENGTH_11 0x00020000ul 191 #define PDL_SPI_LENGTH_12 0x00040000ul 192 #define PDL_SPI_LENGTH_13 0x00080000ul 193 #define PDL_SPI_LENGTH_14 0x00100000ul 194 #define PDL_SPI_LENGTH_15 0x00200000ul 195 #define PDL_SPI_LENGTH_16 0x00400000ul 196 #define PDL_SPI_LENGTH_20 0x00800000ul 197 #define PDL_SPI_LENGTH_24 0x01000000ul 198 #define PDL_SPI_LENGTH_32 0x02000000ul 199 200 /* Data transfer format */ 201 #define PDL_SPI_MSB_FIRST 0x04000000ul 202 #define PDL_SPI_LSB_FIRST 0x08000000ul 203 204 /* Extended timing selection */ 205 #define PDL_SPI_CLOCK_DELAY_MINIMUM 0x01u 206 #define PDL_SPI_CLOCK_DELAY_EXTENDED 0x02u 207 208 /* Extended timing selection */ 209 #define PDL_SPI_SSL_DELAY_MINIMUM 0x04u 210 #define PDL_SPI_SSL_DELAY_EXTENDED 0x08u 211 212 /* Next-access delay */ 213 #define PDL_SPI_NEXT_DELAY_MINIMUM 0x10u 214 #define PDL_SPI_NEXT_DELAY_EXTENDED 0x20u 215 216 /* DMAC / DTC trigger control */ 217 #define PDL_SPI_DMAC_DTC_TRIGGER_DISABLE 0x01u 218 #define PDL_SPI_DMAC_TRIGGER_ENABLE 0x02u 219 #define PDL_SPI_DTC_TRIGGER_ENABLE 0x04u 220 221 #endif 222 /* End of file */ 223