1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2020/12/31 Bernard Add license info 9 */ 10 #ifndef __REALVIEW_H__ 11 #define __REALVIEW_H__ 12 13 #define __REG32(x) (*((volatile unsigned int *)(x))) 14 #define __REG16(x) (*((volatile unsigned short *)(x))) 15 16 /* 17 * Peripheral addresses 18 */ 19 #define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */ 20 #define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */ 21 #define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */ 22 #define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */ 23 #define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */ 24 #define REALVIEW_WATCHDOG0_BASE 0x1000F000 /* Watchdog 0 */ 25 #define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */ 26 #define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */ 27 #define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */ 28 #define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */ 29 #define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */ 30 #define REALVIEW_TIMER4_5_BASE 0x10018000 /* Timer 4/5 */ 31 #define REALVIEW_TIMER6_7_BASE 0x10019000 /* Timer 6/7 */ 32 #define REALVIEW_SCTL_BASE 0x10001000 /* System Controller */ 33 #define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ 34 #define REALVIEW_ONB_SRAM_BASE 0x10060000 /* On-board SRAM */ 35 #define REALVIEW_DMC_BASE 0x100E0000 /* DMC configuration */ 36 #define REALVIEW_SMC_BASE 0x100E1000 /* SMC configuration */ 37 #define REALVIEW_CAN_BASE 0x100E2000 /* CAN bus */ 38 #define REALVIEW_GIC_CPU_BASE 0x1E000100 /* Generic interrupt controller CPU interface */ 39 #define REALVIEW_FLASH0_BASE 0x40000000 40 #define REALVIEW_FLASH0_SIZE SZ_64M 41 #define REALVIEW_FLASH1_BASE 0x44000000 42 #define REALVIEW_FLASH1_SIZE SZ_64M 43 44 #define VEXPRESS_SRAM_BASE 0x48000000 45 46 #define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */ 47 #define VEXPRESS_ETH_BASE 0x4E000000 /* Ethernet */ 48 49 #define REALVIEW_USB_BASE 0x4F000000 /* USB */ 50 #define REALVIEW_GIC_DIST_BASE 0x1E001000 /* Generic interrupt controller distributor */ 51 #define REALVIEW_LT_BASE 0xC0000000 /* Logic Tile expansion */ 52 #define REALVIEW_SDRAM6_BASE 0x70000000 /* SDRAM bank 6 256MB */ 53 #define REALVIEW_SDRAM7_BASE 0x80000000 /* SDRAM bank 7 256MB */ 54 55 #define REALVIEW_SYS_PLD_CTRL1 0x74 56 57 /* 58 * PCI regions 59 */ 60 #define REALVIEW_PCI_BASE 0x90040000 /* PCI-X Unit base */ 61 #define REALVIEW_PCI_IO_BASE 0x90050000 /* IO Region on AHB */ 62 #define REALVIEW_PCI_MEM_BASE 0xA0000000 /* MEM Region on AHB */ 63 64 #define REALVIEW_PCI_BASE_SIZE 0x10000 /* 16 Kb */ 65 #define REALVIEW_PCI_IO_SIZE 0x1000 /* 4 Kb */ 66 #define REALVIEW_PCI_MEM_SIZE 0x20000000 /* 512 MB */ 67 68 /* 69 * Memory definitions 70 */ 71 #define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)... */ 72 #define REALVIEW_BOOT_ROM_HI 0x30000000 73 #define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */ 74 #define REALVIEW_BOOT_ROM_SIZE SZ_64M 75 76 #define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */ 77 #define REALVIEW_SSRAM_SIZE SZ_2M 78 79 /* 80 * SDRAM 81 */ 82 #define REALVIEW_SDRAM_BASE 0x00000000 83 84 /* 85 * Logic expansion modules 86 * 87 */ 88 #define IRQ_PBA8_GIC_START 32 89 90 /* 91 * PB-A8 on-board gic irq sources 92 */ 93 #define IRQ_PBA8_WATCHDOG (IRQ_PBA8_GIC_START + 0) /* Watchdog timer */ 94 #define IRQ_PBA8_SOFT (IRQ_PBA8_GIC_START + 1) /* Software interrupt */ 95 #define IRQ_PBA8_TIMER0_1 (IRQ_PBA8_GIC_START + 2) /* Timer 0/1 (default timer) */ 96 #define IRQ_PBA8_TIMER2_3 (IRQ_PBA8_GIC_START + 3) /* Timer 2/3 */ 97 #define IRQ_PBA8_RTC (IRQ_PBA8_GIC_START + 4) /* Timer 2/3 */ 98 #define IRQ_VEXPRESS_A9_RTC (IRQ_PBA8_GIC_START + 4) 99 100 #define IRQ_PBA8_UART0 (IRQ_PBA8_GIC_START + 5) /* UART 0 on development chip */ 101 #define IRQ_PBA8_UART1 (IRQ_PBA8_GIC_START + 6) /* UART 1 on development chip */ 102 #define IRQ_PBA8_UART2 (IRQ_PBA8_GIC_START + 7) /* UART 2 on development chip */ 103 #define IRQ_PBA8_UART3 (IRQ_PBA8_GIC_START + 8) /* UART 3 on development chip */ 104 105 #define IRQ_VEXPRESS_A9_KBD (IRQ_PBA8_GIC_START + 12) 106 #define IRQ_VEXPRESS_A9_MOUSE (IRQ_PBA8_GIC_START + 13) 107 #define IRQ_VEXPRESS_A9_CLCD (IRQ_PBA8_GIC_START + 14) 108 #define IRQ_VEXPRESS_A9_ETH (IRQ_PBA8_GIC_START + 15) 109 110 /* 9 reserved */ 111 #define IRQ_PBA8_SSP (IRQ_PBA8_GIC_START + 11) /* Synchronous Serial Port */ 112 #define IRQ_PBA8_SCI (IRQ_PBA8_GIC_START + 16) /* Smart Card Interface */ 113 #define IRQ_PBA8_MMCI0A (IRQ_PBA8_GIC_START + 17) /* Multimedia Card 0A */ 114 #define IRQ_PBA8_MMCI0B (IRQ_PBA8_GIC_START + 18) /* Multimedia Card 0B */ 115 #define IRQ_PBA8_AACI (IRQ_PBA8_GIC_START + 19) /* Audio Codec */ 116 #define IRQ_PBA8_KMI0 (IRQ_PBA8_GIC_START + 20) /* Keyboard/Mouse port 0 */ 117 #define IRQ_PBA8_KMI1 (IRQ_PBA8_GIC_START + 21) /* Keyboard/Mouse port 1 */ 118 #define IRQ_PBA8_CHARLCD (IRQ_PBA8_GIC_START + 22) /* Character LCD */ 119 #define IRQ_PBA8_CLCD (IRQ_PBA8_GIC_START + 23) /* CLCD controller */ 120 #define IRQ_PBA8_DMAC (IRQ_PBA8_GIC_START + 24) /* DMA controller */ 121 #define IRQ_PBA8_PWRFAIL (IRQ_PBA8_GIC_START + 25) /* Power failure */ 122 #define IRQ_PBA8_PISMO (IRQ_PBA8_GIC_START + 26) /* PISMO interface */ 123 #define IRQ_PBA8_DoC (IRQ_PBA8_GIC_START + 27) /* Disk on Chip memory controller */ 124 #define IRQ_PBA8_ETH (IRQ_PBA8_GIC_START + 28) /* Ethernet controller */ 125 #define IRQ_PBA8_USB (IRQ_PBA8_GIC_START + 29) /* USB controller */ 126 #define IRQ_PBA8_TSPEN (IRQ_PBA8_GIC_START + 30) /* Touchscreen pen */ 127 #define IRQ_PBA8_TSKPAD (IRQ_PBA8_GIC_START + 31) /* Touchscreen keypad */ 128 129 #define IRQ_PBA8_PMU (IRQ_PBA8_GIC_START + 47) /* Cortex-A8 PMU */ 130 131 /* ... */ 132 #define IRQ_PBA8_PCI0 (IRQ_PBA8_GIC_START + 50) 133 #define IRQ_PBA8_PCI1 (IRQ_PBA8_GIC_START + 51) 134 #define IRQ_PBA8_PCI2 (IRQ_PBA8_GIC_START + 52) 135 #define IRQ_PBA8_PCI3 (IRQ_PBA8_GIC_START + 53) 136 137 #define IRQ_PBA8_SMC -1 138 #define IRQ_PBA8_SCTL -1 139 140 #define NR_GIC_PBA8 1 141 142 /* 143 * Only define NR_IRQS if less than NR_IRQS_PBA8 144 */ 145 #define NR_IRQS_PBA8 (IRQ_PBA8_GIC_START + 64) 146 147 /* ------------------------------------------------------------------------ 148 * RealView Registers 149 * ------------------------------------------------------------------------ 150 * 151 */ 152 #define REALVIEW_SYS_ID_OFFSET 0x00 153 #define REALVIEW_SYS_SW_OFFSET 0x04 154 #define REALVIEW_SYS_LED_OFFSET 0x08 155 #define REALVIEW_SYS_OSC0_OFFSET 0x0C 156 157 #define REALVIEW_SYS_OSC1_OFFSET 0x10 158 #define REALVIEW_SYS_OSC2_OFFSET 0x14 159 #define REALVIEW_SYS_OSC3_OFFSET 0x18 160 #define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */ 161 162 #define REALVIEW_SYS_LOCK_OFFSET 0x20 163 #define REALVIEW_SYS_100HZ_OFFSET 0x24 164 #define REALVIEW_SYS_CFGDATA1_OFFSET 0x28 165 #define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C 166 #define REALVIEW_SYS_FLAGS_OFFSET 0x30 167 #define REALVIEW_SYS_FLAGSSET_OFFSET 0x30 168 #define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34 169 #define REALVIEW_SYS_NVFLAGS_OFFSET 0x38 170 #define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38 171 #define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C 172 #define REALVIEW_SYS_RESETCTL_OFFSET 0x40 173 #define REALVIEW_SYS_PCICTL_OFFSET 0x44 174 #define REALVIEW_SYS_MCI_OFFSET 0x48 175 #define REALVIEW_SYS_FLASH_OFFSET 0x4C 176 #define REALVIEW_SYS_CLCD_OFFSET 0x50 177 #define REALVIEW_SYS_CLCDSER_OFFSET 0x54 178 #define REALVIEW_SYS_BOOTCS_OFFSET 0x58 179 #define REALVIEW_SYS_24MHz_OFFSET 0x5C 180 #define REALVIEW_SYS_MISC_OFFSET 0x60 181 #define REALVIEW_SYS_IOSEL_OFFSET 0x70 182 #define REALVIEW_SYS_PROCID_OFFSET 0x84 183 #define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0 184 #define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4 185 #define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8 186 #define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC 187 #define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0 188 189 #define REALVIEW_SYS_BASE 0x10000000 190 #define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) 191 #define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET) 192 #define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET) 193 #define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET) 194 #define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET) 195 196 #define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET) 197 #define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET) 198 #define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET) 199 #define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET) 200 #define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET) 201 #define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET) 202 #define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET) 203 #define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET) 204 #define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET) 205 #define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET) 206 #define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET) 207 #define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET) 208 #define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET) 209 #define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET) 210 #define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET) 211 #define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET) 212 #define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET) 213 #define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) 214 #define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) 215 #define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) 216 #define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET) 217 #define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) 218 #define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) 219 #define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) 220 #define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET) 221 #define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET) 222 223 #define REALVIEW_SYS_CTRL_LED (1 << 0) 224 225 /* ------------------------------------------------------------------------ 226 * RealView control registers 227 * ------------------------------------------------------------------------ 228 */ 229 230 /* 231 * REALVIEW_IDFIELD 232 * 233 * 31:24 = manufacturer (0x41 = ARM) 234 * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus) 235 * 15:12 = FPGA (0x3 = XVC600 or XVC600E) 236 * 11:4 = build value 237 * 3:0 = revision number (0x1 = rev B (AHB)) 238 */ 239 240 /* 241 * REALVIEW_SYS_LOCK 242 * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, 243 * SYS_CLD, SYS_BOOTCS 244 */ 245 #define REALVIEW_SYS_LOCK_LOCKED (1 << 16) 246 #define REALVIEW_SYS_LOCKVAL 0xA05F 247 #define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */ 248 249 /* 250 * REALVIEW_SYS_FLASH 251 */ 252 #define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ 253 254 /* 255 * REALVIEW_INTREG 256 * - used to acknowledge and control MMCI and UART interrupts 257 */ 258 #define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */ 259 #define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */ 260 #define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */ 261 /* write 1 to acknowledge and clear */ 262 #define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */ 263 #define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ 264 265 /* 266 * LED settings, bits [7:0] 267 */ 268 #define REALVIEW_SYS_LED0 (1 << 0) 269 #define REALVIEW_SYS_LED1 (1 << 1) 270 #define REALVIEW_SYS_LED2 (1 << 2) 271 #define REALVIEW_SYS_LED3 (1 << 3) 272 #define REALVIEW_SYS_LED4 (1 << 4) 273 #define REALVIEW_SYS_LED5 (1 << 5) 274 #define REALVIEW_SYS_LED6 (1 << 6) 275 #define REALVIEW_SYS_LED7 (1 << 7) 276 277 #define ALL_LEDS 0xFF 278 279 #define LED_BANK REALVIEW_SYS_LED 280 281 /* 282 * Control registers 283 */ 284 #define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */ 285 #define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */ 286 #define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ 287 #define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ 288 289 /* 290 * Clean base - dummy 291 * 292 */ 293 #define CLEAN_BASE REALVIEW_BOOT_ROM_HI 294 295 /* 296 * System controller bit assignment 297 */ 298 #define REALVIEW_REFCLK 0 299 #define REALVIEW_TIMCLK 1 300 301 #define REALVIEW_TIMER1_EnSel 15 302 #define REALVIEW_TIMER2_EnSel 17 303 #define REALVIEW_TIMER3_EnSel 19 304 #define REALVIEW_TIMER4_EnSel 21 305 306 struct rt_hw_register 307 { 308 unsigned long r0; 309 unsigned long r1; 310 unsigned long r2; 311 unsigned long r3; 312 unsigned long r4; 313 unsigned long r5; 314 unsigned long r6; 315 unsigned long r7; 316 unsigned long r8; 317 unsigned long r9; 318 unsigned long r10; 319 unsigned long fp; 320 unsigned long ip; 321 unsigned long sp; 322 unsigned long lr; 323 unsigned long pc; 324 unsigned long cpsr; 325 unsigned long ORIG_r0; 326 }; 327 328 #include <rtdef.h> 329 #include <cpuport.h> 330 331 /* Interrupt Control Interface */ 332 #define ARM_GIC_CPU_BASE 0x1E000000 333 334 /* number of interrupts on board */ 335 #define ARM_GIC_NR_IRQS 96 336 /* only one GIC available */ 337 #define ARM_GIC_MAX_NR 1 338 339 #endif 340 341