1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_bkp.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_BKP_H 22 #define __REG_BKP_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 //////////////////////////////////////////////////////////////////////////////// 44 /// @brief BKP Base Address Definition 45 //////////////////////////////////////////////////////////////////////////////// 46 47 48 #define BKP_BASE (APB1PERIPH_BASE + 0x2840) ///< Base Address: 0x40002840 49 50 51 52 53 //////////////////////////////////////////////////////////////////////////////// 54 /// @brief BKP Register Structure Definition 55 //////////////////////////////////////////////////////////////////////////////// 56 57 58 59 #define BKP_NUMBER 20 60 61 typedef struct { 62 __IO u32 RTCCR; ///< RTC clock calibration register, offset: 0x00 63 __IO u32 CR; ///< BKP control register, offset: 0x04 64 __IO u32 CSR; ///< BKP control/status register, offset: 0x08 65 __IO u32 RESERVED0; ///< Reserved, offset: 0x0C 66 __IO u32 DR1; ///< BKP data register 1, offset: 0x10 67 __IO u32 DR2; ///< BKP data register 2, offset: 0x14 68 __IO u32 DR3; ///< BKP data register 3, offset: 0x18 69 __IO u32 DR4; ///< BKP data register 4, offset: 0x1C 70 __IO u32 DR5; ///< BKP data register 5, offset: 0x20 71 __IO u32 DR6; ///< BKP data register 6, offset: 0x24 72 __IO u32 DR7; ///< BKP data register 7, offset: 0x28 73 __IO u32 DR8; ///< BKP data register 8, offset: 0x2C 74 __IO u32 DR9; ///< BKP data register 9, offset: 0x30 75 __IO u32 DR10; ///< BKP data register 10 offset: 0x34 76 __IO u32 DR11; ///< BKP data register 11, offset: 0x38 77 __IO u32 DR12; ///< BKP data register 12, offset: 0x3C 78 __IO u32 DR13; ///< BKP data register 13, offset: 0x40 79 __IO u32 DR14; ///< BKP data register 14, offset: 0x44 80 __IO u32 DR15; ///< BKP data register 15, offset: 0x48 81 __IO u32 DR16; ///< BKP data register 16, offset: 0x4C 82 __IO u32 DR17; ///< BKP data register 17, offset: 0x50 83 __IO u32 DR18; ///< BKP data register 18, offset: 0x54 84 __IO u32 DR19; ///< BKP data register 19, offset: 0x58 85 __IO u32 DR20; ///< BKP data register 20, offset: 0x5C 86 } BKP_TypeDef; 87 88 //////////////////////////////////////////////////////////////////////////////// 89 /// @brief BKP type pointer Definition 90 //////////////////////////////////////////////////////////////////////////////// 91 #define BKP ((BKP_TypeDef*) BKP_BASE) 92 93 94 95 //////////////////////////////////////////////////////////////////////////////// 96 /// @brief BKP_DRn Register Bit Definition 97 //////////////////////////////////////////////////////////////////////////////// 98 #define BKP_DR_DATA_Pos (0) 99 #define BKP_DR_DATA (0xFFFFU << BKP_DR_DATA) ///< Backup data 100 101 //////////////////////////////////////////////////////////////////////////////// 102 /// @brief BKP_RTCCR Register Bit Definition 103 //////////////////////////////////////////////////////////////////////////////// 104 #define BKP_RTCCR_CAL_Pos (0) 105 #define BKP_RTCCR_CAL (0x7FU << BKP_RTCCR_CAL_Pos) ///< Calibration value 106 #define BKP_RTCCR_CCO_Pos (7) 107 #define BKP_RTCCR_CCO (0x01U << BKP_RTCCR_CCO_Pos) ///< Calibration Clock Output 108 #define BKP_RTCCR_ASOE_Pos (8) 109 #define BKP_RTCCR_ASOE (0x01U << BKP_RTCCR_ASOE_Pos) ///< Alarm or Second Output Enable 110 #define BKP_RTCCR_ASOS_Pos (9) 111 #define BKP_RTCCR_ASOS (0x01U << BKP_RTCCR_ASOS_Pos) ///< Alarm or Second Output Selection 112 113 //////////////////////////////////////////////////////////////////////////////// 114 /// @brief BKP_CR Register Bit Definition 115 //////////////////////////////////////////////////////////////////////////////// 116 #define BKP_CR_TPE_Pos (0) 117 #define BKP_CR_TPE (0x01U << BKP_CR_TPE_Pos) ///< TAMPER pin enable 118 #define BKP_CR_TPAL_Pos (1) 119 #define BKP_CR_TPAL (0x01U << BKP_CR_TPAL_Pos) ///< TAMPER pin active level 120 121 //////////////////////////////////////////////////////////////////////////////// 122 /// @brief BKP_CSR Register Bit Definition 123 //////////////////////////////////////////////////////////////////////////////// 124 #define BKP_CSR_CTE_Pos (0) 125 #define BKP_CSR_CTE (0x01U << BKP_CSR_CTE_Pos) ///< Clear Tamper event 126 #define BKP_CSR_CTI_Pos (1) 127 #define BKP_CSR_CTI (0x01U << BKP_CSR_CTI_Pos) ///< Clear Tamper Interrupt 128 #define BKP_CSR_TPIE_Pos (2) 129 #define BKP_CSR_TPIE (0x01U << BKP_CSR_TPIE_Pos) ///< TAMPER Pin interrupt enable 130 #define BKP_CSR_TEF_Pos (8) 131 #define BKP_CSR_TEF (0x01U << BKP_CSR_TEF_Pos) ///< Tamper Event Flag 132 #define BKP_CSR_TIF_Pos (9) 133 #define BKP_CSR_TIF (0x01U << BKP_CSR_TIF_Pos) ///< Tamper Interrupt Flag 134 135 136 137 138 139 /// @} 140 141 /// @} 142 143 /// @} 144 145 //////////////////////////////////////////////////////////////////////////////// 146 #endif 147 //////////////////////////////////////////////////////////////////////////////// 148