1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_common.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_COMMON_H 22 #define __REG_COMMON_H 23 24 // Files includes 25 #include <stdint.h> 26 #include <stdbool.h> 27 #include "types.h" 28 29 30 #if defined ( __CC_ARM ) 31 #pragma anon_unions 32 #endif 33 34 #ifndef HSE_STARTUP_TIMEOUT 35 #define HSE_STARTUP_TIMEOUT (0x0500U) ///< Time out for HSE start up. 36 #endif 37 #ifdef CUSTOM_HSE_VAL 38 #ifndef HSE_VALUE 39 #define HSE_VALUE (12000000U) ///< Value of the External oscillator in Hz. 40 #endif 41 #else 42 #ifndef HSE_VALUE 43 #define HSE_VALUE (8000000U) ///< Value of the External oscillator in Hz. 44 #endif 45 #endif 46 47 48 49 #define HSI_VALUE_PLL_ON (8000000U) ///< Value of the Internal oscillator in Hz. 50 #define HSI_DIV6 (8000000U) ///< Value of the Internal oscillator in Hz. 51 // Value of the Internal oscillator in Hz. 52 53 54 #define LSI_VALUE (40000U) ///< Value of the Internal oscillator in Hz. 55 56 57 58 59 60 #ifndef HSI_VALUE 61 62 #define HSI_VALUE (8000000U) ///< Value of the Internal oscillator in Hz. 63 64 #endif 65 66 67 68 69 70 71 72 73 #define __MPU_PRESENT (0) ///< Cortex-M3 does not provide a MPU present or not 74 #ifndef __NVIC_PRIO_BITS 75 #define __NVIC_PRIO_BITS (4) ///< Cortex-M3 uses 4 Bits for the Priority Levels 76 //#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 77 #endif 78 79 #define __Vendor_SysTickConfig (0) ///< Set to 1 if different SysTick Config is used 80 81 82 //////////////////////////////////////////////////////////////////////////////// 83 /// @brief MM32 MCU Interrupt Handle 84 //////////////////////////////////////////////////////////////////////////////// 85 typedef enum IRQn { 86 NonMaskableInt_IRQn = -14, ///< 2 Non Maskable Interrupt 87 MemoryManagement_IRQn = -12, ///< 4 Cortex-M3 Memory Management Interrupt 88 BusFault_IRQn = -11, ///< 5 Cortex-M3 Bus Fault Interrupt 89 UsageFault_IRQn = -10, ///< 6 Cortex-M3 Usage Fault Interrupt 90 SVCall_IRQn = -5, ///< 11 Cortex-M3 SV Call Interrupt 91 DebugMonitor_IRQn = -4, ///< 12 Cortex-M3 Debug Monitor Interrupt 92 PendSV_IRQn = -2, ///< 14 Cortex-M3 Pend SV Interrupt 93 SysTick_IRQn = -1, ///< 15 Cortex-M3 System Tick Interrupt 94 95 WWDG_IWDG_IRQn = 0, ///< Watchdog interrupt 96 WWDG_IRQn = 0, ///< Watchdog interrupt 97 PVD_IRQn = 1, ///< (PVD) Interrupt 98 TAMPER_IRQn = 2, ///< Intrusion detection interrupted 99 RTC_IRQn = 3, ///< Real-time clock (RTC) global interrupt 100 FLASH_IRQn = 4, ///< Flash global interrupt 101 RCC_CRS_IRQn = 5, ///< RCC and CRS global interrupt 102 EXTI0_IRQn = 6, ///< EXTI line 0 interrupt 103 EXTI1_IRQn = 7, ///< EXTI line 1 interrupt 104 EXTI2_IRQn = 8, ///< EXTI line 2 interrupt 105 EXTI3_IRQn = 9, ///< EXTI line 3 interrupted 106 EXTI4_IRQn = 10, ///< EXTI line 4 interrupt 107 DMA1_Channel1_IRQn = 11, ///< DMA1 channel 1 global interrupt 108 DMA1_Channel2_IRQn = 12, ///< DMA1 channel 2 global interrupt 109 DMA1_Channel3_IRQn = 13, ///< DMA1 channel 3 global interrupt 110 DMA1_Channel4_IRQn = 14, ///< DMA1 channel 4 global interrupt 111 DMA1_Channel5_IRQn = 15, ///< DMA1 channel 5 global interrupt 112 DMA1_Channel6_IRQn = 16, ///< DMA1 channel 6 global interrupt 113 DMA1_Channel7_IRQn = 17, ///< DMA1 channel 7 global interrupt 114 ADC1_IRQn = 18, ///< ADC1 global interrupt 115 ADC1_2_IRQn = 18, ///< ADC1&ADC2 global interrupt 116 ADC2_IRQn = 18, ///< ADC2 global interrupt 117 FlashCache_IRQn = 19, ///< FlashCache outage 118 CAN1_RX_IRQn = 21, ///< CAN1 receive interrupt 119 CAN_IRQn = 21, ///< CAN interrupt 120 EXTI9_5_IRQn = 23, ///< EXTI line [9: 5] interrupted 121 TIM1_BRK_IRQn = 24, ///< TIM1 disconnect interrupt 122 TIM1_UP_IRQn = 25, ///< TIM1 update interrupt 123 IM1_TRG_COM_IRQn = 26, ///< TIM1 trigger and communication interrupt 124 TIM1_CC_IRQn = 27, ///< TIM1 capture compare interrupt 125 TIM2_IRQn = 28, ///< TIM2 global interrupt 126 TIM3_IRQn = 29, ///< TIM3 global interrupt 127 TIM4_IRQn = 30, ///< TIM4 global interrupt 128 I2C1_IRQn = 31, ///< I2C1 global interrupt 129 I2C2_IRQn = 33, ///< I2C2 global interrupt 130 SPI1_IRQn = 35, ///< SPI1 global interrupt 131 SPI2_IRQn = 36, ///< SPI2 global interrupt 132 UART1_IRQn = 37, ///< UART1 global interrupt 133 UART2_IRQn = 38, ///< UART2 global interrupt 134 UART3_IRQn = 39, ///< UART3 global interrupt 135 EXTI15_10_IRQn = 40, ///< EXTI line [15: 10] interrupted 136 RTCAlarm_IRQn = 41, ///< RTC alarm connected to EXTI interrupted 137 USB_WKUP_IRQn = 42, ///< Wake-up interrupt from USB connected to EXTI 138 TIM8_BRK_IRQn = 43, ///< TIM8 brake interruption 139 TIM8_UP_IRQn = 44, ///< TIM8 update interrupt 140 TIM8_TRG_COM_IRQn = 45, ///< TIM8 trigger, communication interrupt 141 TIM8_CC_IRQn = 46, ///< TIM8 capture compare interrupt 142 ADC3_IRQn = 47, ///< ADC3 global interrupt 143 SDIO_IRQn = 49, ///< SDIO global interrupt 144 TIM5_IRQn = 50, ///< TIM5 global interrupt 145 SPI3_IRQn = 51, ///< SPI3 global interrupt 146 UART4_IRQn = 52, ///< UART4 global interrupt 147 UART5_IRQn = 53, ///< UART5 global interrupt 148 TIM6_IRQn = 54, ///< TIM6 global interrupt 149 TIM7_IRQn = 55, ///< TIM7 global interrupt 150 DMA2_Channel1_IRQn = 56, ///< DMA2 channel 1 global interrupt 151 DMA2_Channel2_IRQn = 57, ///< DMA2 channel 2 global interrupt 152 DMA2_Channel3_IRQn = 58, ///< DMA2 channel 3 global interrupt 153 DMA2_Channel4_IRQn = 59, ///< DMA2 channel 4 global interrupt 154 DMA2_Channel5_IRQn = 60, ///< DMA2 channel 5 global interrupt 155 ETHERNET_MAC_IRQn = 61, ///< ETHERNET global interrupt 156 COMP1_2_IRQn = 64, ///< Comparator 1/2 interrupt connected to EXTI 157 USB_FS_IRQn = 67, ///< USB FS global interrupt 158 UART6_IRQn = 71, ///< UART6 global interrupt 159 UART7_IRQn = 82, ///< UART7 global interrupt 160 UART8_IRQn = 83, ///< UART8 global interrupt 161 } IRQn_Type; 162 163 164 165 166 #include <core_cm3.h> 167 168 169 170 #define PERIPH_BASE (0x40000000U) ///< Peripheral base address in the alias region 171 172 #define EEPROM_BASE (0x08100000U) ///< EEPROM base address in the alias region 173 174 175 #define SRAM_BITBAND_BASE (0x22000000U) ///< Peripheral base address in the bit-band region 176 #define PERIPH_BITBAND_BASE (0x42000000U) ///< SRAM base address in the bit-band region 177 178 #define APB1PERIPH_BASE (PERIPH_BASE + 0x00000000) 179 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) 180 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) 181 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) 182 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x20000000) 183 184 185 186 //////////////////////////////////////////////////////////////////////////////// 187 /// @brief UID type pointer Definition 188 //////////////////////////////////////////////////////////////////////////////// 189 #define UID_BASE (0x1FFFF7E0U) ///< Unique device ID register base address 190 191 192 193 194 195 196 197 198 /////////////////////////////////////////////////////////////////////////////// 199 /// @brief Nested Vectored Interrupt Controller 200 /////////////////////////////////////////////////////////////////////////////// 201 //////////////////////////////////////////////////////////////////////////////// 202 /// @brief NVIC_ISER Register Bit Definition 203 //////////////////////////////////////////////////////////////////////////////// 204 #define NVIC_ISER_SETENA (0xFFFFFFFFU) ///< Interrupt set enable bits 205 #define NVIC_ISER_SETENA_0 (0x00000001U) ///< bit 0 206 #define NVIC_ISER_SETENA_1 (0x00000002U) ///< bit 1 207 #define NVIC_ISER_SETENA_2 (0x00000004U) ///< bit 2 208 #define NVIC_ISER_SETENA_3 (0x00000008U) ///< bit 3 209 #define NVIC_ISER_SETENA_4 (0x00000010U) ///< bit 4 210 #define NVIC_ISER_SETENA_5 (0x00000020U) ///< bit 5 211 #define NVIC_ISER_SETENA_6 (0x00000040U) ///< bit 6 212 #define NVIC_ISER_SETENA_7 (0x00000080U) ///< bit 7 213 #define NVIC_ISER_SETENA_8 (0x00000100U) ///< bit 8 214 #define NVIC_ISER_SETENA_9 (0x00000200U) ///< bit 9 215 #define NVIC_ISER_SETENA_10 (0x00000400U) ///< bit 10 216 #define NVIC_ISER_SETENA_11 (0x00000800U) ///< bit 11 217 #define NVIC_ISER_SETENA_12 (0x00001000U) ///< bit 12 218 #define NVIC_ISER_SETENA_13 (0x00002000U) ///< bit 13 219 #define NVIC_ISER_SETENA_14 (0x00004000U) ///< bit 14 220 #define NVIC_ISER_SETENA_15 (0x00008000U) ///< bit 15 221 #define NVIC_ISER_SETENA_16 (0x00010000U) ///< bit 16 222 #define NVIC_ISER_SETENA_17 (0x00020000U) ///< bit 17 223 #define NVIC_ISER_SETENA_18 (0x00040000U) ///< bit 18 224 #define NVIC_ISER_SETENA_19 (0x00080000U) ///< bit 19 225 #define NVIC_ISER_SETENA_20 (0x00100000U) ///< bit 20 226 #define NVIC_ISER_SETENA_21 (0x00200000U) ///< bit 21 227 #define NVIC_ISER_SETENA_22 (0x00400000U) ///< bit 22 228 #define NVIC_ISER_SETENA_23 (0x00800000U) ///< bit 23 229 #define NVIC_ISER_SETENA_24 (0x01000000U) ///< bit 24 230 #define NVIC_ISER_SETENA_25 (0x02000000U) ///< bit 25 231 #define NVIC_ISER_SETENA_26 (0x04000000U) ///< bit 26 232 #define NVIC_ISER_SETENA_27 (0x08000000U) ///< bit 27 233 #define NVIC_ISER_SETENA_28 (0x10000000U) ///< bit 28 234 #define NVIC_ISER_SETENA_29 (0x20000000U) ///< bit 29 235 #define NVIC_ISER_SETENA_30 (0x40000000U) ///< bit 30 236 #define NVIC_ISER_SETENA_31 (0x80000000U) ///< bit 31 237 238 //////////////////////////////////////////////////////////////////////////////// 239 /// @brief NVIC_ICER Register Bit Definition 240 //////////////////////////////////////////////////////////////////////////////// 241 #define NVIC_ICER_CLRENA (0xFFFFFFFFU) ///< Interrupt clear-enable bits 242 #define NVIC_ICER_CLRENA_0 (0x00000001U) ///< bit 0 243 #define NVIC_ICER_CLRENA_1 (0x00000002U) ///< bit 1 244 #define NVIC_ICER_CLRENA_2 (0x00000004U) ///< bit 2 245 #define NVIC_ICER_CLRENA_3 (0x00000008U) ///< bit 3 246 #define NVIC_ICER_CLRENA_4 (0x00000010U) ///< bit 4 247 #define NVIC_ICER_CLRENA_5 (0x00000020U) ///< bit 5 248 #define NVIC_ICER_CLRENA_6 (0x00000040U) ///< bit 6 249 #define NVIC_ICER_CLRENA_7 (0x00000080U) ///< bit 7 250 #define NVIC_ICER_CLRENA_8 (0x00000100U) ///< bit 8 251 #define NVIC_ICER_CLRENA_9 (0x00000200U) ///< bit 9 252 #define NVIC_ICER_CLRENA_10 (0x00000400U) ///< bit 10 253 #define NVIC_ICER_CLRENA_11 (0x00000800U) ///< bit 11 254 #define NVIC_ICER_CLRENA_12 (0x00001000U) ///< bit 12 255 #define NVIC_ICER_CLRENA_13 (0x00002000U) ///< bit 13 256 #define NVIC_ICER_CLRENA_14 (0x00004000U) ///< bit 14 257 #define NVIC_ICER_CLRENA_15 (0x00008000U) ///< bit 15 258 #define NVIC_ICER_CLRENA_16 (0x00010000U) ///< bit 16 259 #define NVIC_ICER_CLRENA_17 (0x00020000U) ///< bit 17 260 #define NVIC_ICER_CLRENA_18 (0x00040000U) ///< bit 18 261 #define NVIC_ICER_CLRENA_19 (0x00080000U) ///< bit 19 262 #define NVIC_ICER_CLRENA_20 (0x00100000U) ///< bit 20 263 #define NVIC_ICER_CLRENA_21 (0x00200000U) ///< bit 21 264 #define NVIC_ICER_CLRENA_22 (0x00400000U) ///< bit 22 265 #define NVIC_ICER_CLRENA_23 (0x00800000U) ///< bit 23 266 #define NVIC_ICER_CLRENA_24 (0x01000000U) ///< bit 24 267 #define NVIC_ICER_CLRENA_25 (0x02000000U) ///< bit 25 268 #define NVIC_ICER_CLRENA_26 (0x04000000U) ///< bit 26 269 #define NVIC_ICER_CLRENA_27 (0x08000000U) ///< bit 27 270 #define NVIC_ICER_CLRENA_28 (0x10000000U) ///< bit 28 271 #define NVIC_ICER_CLRENA_29 (0x20000000U) ///< bit 29 272 #define NVIC_ICER_CLRENA_30 (0x40000000U) ///< bit 30 273 #define NVIC_ICER_CLRENA_31 (0x80000000U) ///< bit 31 274 275 //////////////////////////////////////////////////////////////////////////////// 276 /// @brief NVIC_ISPR Register Bit Definition 277 //////////////////////////////////////////////////////////////////////////////// 278 #define NVIC_ISPR_SETPEND (0xFFFFFFFFU) ///< Interrupt set-pending bits 279 #define NVIC_ISPR_SETPEND_0 (0x00000001U) ///< bit 0 280 #define NVIC_ISPR_SETPEND_1 (0x00000002U) ///< bit 1 281 #define NVIC_ISPR_SETPEND_2 (0x00000004U) ///< bit 2 282 #define NVIC_ISPR_SETPEND_3 (0x00000008U) ///< bit 3 283 #define NVIC_ISPR_SETPEND_4 (0x00000010U) ///< bit 4 284 #define NVIC_ISPR_SETPEND_5 (0x00000020U) ///< bit 5 285 #define NVIC_ISPR_SETPEND_6 (0x00000040U) ///< bit 6 286 #define NVIC_ISPR_SETPEND_7 (0x00000080U) ///< bit 7 287 #define NVIC_ISPR_SETPEND_8 (0x00000100U) ///< bit 8 288 #define NVIC_ISPR_SETPEND_9 (0x00000200U) ///< bit 9 289 #define NVIC_ISPR_SETPEND_10 (0x00000400U) ///< bit 10 290 #define NVIC_ISPR_SETPEND_11 (0x00000800U) ///< bit 11 291 #define NVIC_ISPR_SETPEND_12 (0x00001000U) ///< bit 12 292 #define NVIC_ISPR_SETPEND_13 (0x00002000U) ///< bit 13 293 #define NVIC_ISPR_SETPEND_14 (0x00004000U) ///< bit 14 294 #define NVIC_ISPR_SETPEND_15 (0x00008000U) ///< bit 15 295 #define NVIC_ISPR_SETPEND_16 (0x00010000U) ///< bit 16 296 #define NVIC_ISPR_SETPEND_17 (0x00020000U) ///< bit 17 297 #define NVIC_ISPR_SETPEND_18 (0x00040000U) ///< bit 18 298 #define NVIC_ISPR_SETPEND_19 (0x00080000U) ///< bit 19 299 #define NVIC_ISPR_SETPEND_20 (0x00100000U) ///< bit 20 300 #define NVIC_ISPR_SETPEND_21 (0x00200000U) ///< bit 21 301 #define NVIC_ISPR_SETPEND_22 (0x00400000U) ///< bit 22 302 #define NVIC_ISPR_SETPEND_23 (0x00800000U) ///< bit 23 303 #define NVIC_ISPR_SETPEND_24 (0x01000000U) ///< bit 24 304 #define NVIC_ISPR_SETPEND_25 (0x02000000U) ///< bit 25 305 #define NVIC_ISPR_SETPEND_26 (0x04000000U) ///< bit 26 306 #define NVIC_ISPR_SETPEND_27 (0x08000000U) ///< bit 27 307 #define NVIC_ISPR_SETPEND_28 (0x10000000U) ///< bit 28 308 #define NVIC_ISPR_SETPEND_29 (0x20000000U) ///< bit 29 309 #define NVIC_ISPR_SETPEND_30 (0x40000000U) ///< bit 30 310 #define NVIC_ISPR_SETPEND_31 (0x80000000U) ///< bit 31 311 312 //////////////////////////////////////////////////////////////////////////////// 313 /// @brief NVIC_ICPR Register Bit Definition 314 //////////////////////////////////////////////////////////////////////////////// 315 #define NVIC_ICPR_CLRPEND (0xFFFFFFFFU) ///< Interrupt clear-pending bits 316 #define NVIC_ICPR_CLRPEND_0 (0x00000001U) ///< bit 0 317 #define NVIC_ICPR_CLRPEND_1 (0x00000002U) ///< bit 1 318 #define NVIC_ICPR_CLRPEND_2 (0x00000004U) ///< bit 2 319 #define NVIC_ICPR_CLRPEND_3 (0x00000008U) ///< bit 3 320 #define NVIC_ICPR_CLRPEND_4 (0x00000010U) ///< bit 4 321 #define NVIC_ICPR_CLRPEND_5 (0x00000020U) ///< bit 5 322 #define NVIC_ICPR_CLRPEND_6 (0x00000040U) ///< bit 6 323 #define NVIC_ICPR_CLRPEND_7 (0x00000080U) ///< bit 7 324 #define NVIC_ICPR_CLRPEND_8 (0x00000100U) ///< bit 8 325 #define NVIC_ICPR_CLRPEND_9 (0x00000200U) ///< bit 9 326 #define NVIC_ICPR_CLRPEND_10 (0x00000400U) ///< bit 10 327 #define NVIC_ICPR_CLRPEND_11 (0x00000800U) ///< bit 11 328 #define NVIC_ICPR_CLRPEND_12 (0x00001000U) ///< bit 12 329 #define NVIC_ICPR_CLRPEND_13 (0x00002000U) ///< bit 13 330 #define NVIC_ICPR_CLRPEND_14 (0x00004000U) ///< bit 14 331 #define NVIC_ICPR_CLRPEND_15 (0x00008000U) ///< bit 15 332 #define NVIC_ICPR_CLRPEND_16 (0x00010000U) ///< bit 16 333 #define NVIC_ICPR_CLRPEND_17 (0x00020000U) ///< bit 17 334 #define NVIC_ICPR_CLRPEND_18 (0x00040000U) ///< bit 18 335 #define NVIC_ICPR_CLRPEND_19 (0x00080000U) ///< bit 19 336 #define NVIC_ICPR_CLRPEND_20 (0x00100000U) ///< bit 20 337 #define NVIC_ICPR_CLRPEND_21 (0x00200000U) ///< bit 21 338 #define NVIC_ICPR_CLRPEND_22 (0x00400000U) ///< bit 22 339 #define NVIC_ICPR_CLRPEND_23 (0x00800000U) ///< bit 23 340 #define NVIC_ICPR_CLRPEND_24 (0x01000000U) ///< bit 24 341 #define NVIC_ICPR_CLRPEND_25 (0x02000000U) ///< bit 25 342 #define NVIC_ICPR_CLRPEND_26 (0x04000000U) ///< bit 26 343 #define NVIC_ICPR_CLRPEND_27 (0x08000000U) ///< bit 27 344 #define NVIC_ICPR_CLRPEND_28 (0x10000000U) ///< bit 28 345 #define NVIC_ICPR_CLRPEND_29 (0x20000000U) ///< bit 29 346 #define NVIC_ICPR_CLRPEND_30 (0x40000000U) ///< bit 30 347 #define NVIC_ICPR_CLRPEND_31 (0x80000000U) ///< bit 31 348 349 //////////////////////////////////////////////////////////////////////////////// 350 /// @brief NVIC_IABR Register Bit Definition 351 //////////////////////////////////////////////////////////////////////////////// 352 #define NVIC_IABR_ACTIVE (0xFFFFFFFFU) ///< Interrupt active flags 353 #define NVIC_IABR_ACTIVE_0 (0x00000001U) ///< bit 0 354 #define NVIC_IABR_ACTIVE_1 (0x00000002U) ///< bit 1 355 #define NVIC_IABR_ACTIVE_2 (0x00000004U) ///< bit 2 356 #define NVIC_IABR_ACTIVE_3 (0x00000008U) ///< bit 3 357 #define NVIC_IABR_ACTIVE_4 (0x00000010U) ///< bit 4 358 #define NVIC_IABR_ACTIVE_5 (0x00000020U) ///< bit 5 359 #define NVIC_IABR_ACTIVE_6 (0x00000040U) ///< bit 6 360 #define NVIC_IABR_ACTIVE_7 (0x00000080U) ///< bit 7 361 #define NVIC_IABR_ACTIVE_8 (0x00000100U) ///< bit 8 362 #define NVIC_IABR_ACTIVE_9 (0x00000200U) ///< bit 9 363 #define NVIC_IABR_ACTIVE_10 (0x00000400U) ///< bit 10 364 #define NVIC_IABR_ACTIVE_11 (0x00000800U) ///< bit 11 365 #define NVIC_IABR_ACTIVE_12 (0x00001000U) ///< bit 12 366 #define NVIC_IABR_ACTIVE_13 (0x00002000U) ///< bit 13 367 #define NVIC_IABR_ACTIVE_14 (0x00004000U) ///< bit 14 368 #define NVIC_IABR_ACTIVE_15 (0x00008000U) ///< bit 15 369 #define NVIC_IABR_ACTIVE_16 (0x00010000U) ///< bit 16 370 #define NVIC_IABR_ACTIVE_17 (0x00020000U) ///< bit 17 371 #define NVIC_IABR_ACTIVE_18 (0x00040000U) ///< bit 18 372 #define NVIC_IABR_ACTIVE_19 (0x00080000U) ///< bit 19 373 #define NVIC_IABR_ACTIVE_20 (0x00100000U) ///< bit 20 374 #define NVIC_IABR_ACTIVE_21 (0x00200000U) ///< bit 21 375 #define NVIC_IABR_ACTIVE_22 (0x00400000U) ///< bit 22 376 #define NVIC_IABR_ACTIVE_23 (0x00800000U) ///< bit 23 377 #define NVIC_IABR_ACTIVE_24 (0x01000000U) ///< bit 24 378 #define NVIC_IABR_ACTIVE_25 (0x02000000U) ///< bit 25 379 #define NVIC_IABR_ACTIVE_26 (0x04000000U) ///< bit 26 380 #define NVIC_IABR_ACTIVE_27 (0x08000000U) ///< bit 27 381 #define NVIC_IABR_ACTIVE_28 (0x10000000U) ///< bit 28 382 #define NVIC_IABR_ACTIVE_29 (0x20000000U) ///< bit 29 383 #define NVIC_IABR_ACTIVE_30 (0x40000000U) ///< bit 30 384 #define NVIC_IABR_ACTIVE_31 (0x80000000U) ///< bit 31 385 386 //////////////////////////////////////////////////////////////////////////////// 387 /// @brief NVIC_PRI0 Register Bit Definition 388 //////////////////////////////////////////////////////////////////////////////// 389 #define NVIC_IPR0_PRI_0 (0x000000FFU) ///< Priority of interrupt 0 390 #define NVIC_IPR0_PRI_1 (0x0000FF00U) ///< Priority of interrupt 1 391 #define NVIC_IPR0_PRI_2 (0x00FF0000U) ///< Priority of interrupt 2 392 #define NVIC_IPR0_PRI_3 (0xFF000000U) ///< Priority of interrupt 3 393 394 //////////////////////////////////////////////////////////////////////////////// 395 /// @brief NVIC_PRI1 Register Bit Definition 396 //////////////////////////////////////////////////////////////////////////////// 397 #define NVIC_IPR1_PRI_4 (0x000000FFU) ///< Priority of interrupt 4 398 #define NVIC_IPR1_PRI_5 (0x0000FF00U) ///< Priority of interrupt 5 399 #define NVIC_IPR1_PRI_6 (0x00FF0000U) ///< Priority of interrupt 6 400 #define NVIC_IPR1_PRI_7 (0xFF000000U) ///< Priority of interrupt 7 401 402 //////////////////////////////////////////////////////////////////////////////// 403 /// @brief NVIC_PRI2 Register Bit Definition 404 //////////////////////////////////////////////////////////////////////////////// 405 #define NVIC_IPR2_PRI_8 (0x000000FFU) ///< Priority of interrupt 8 406 #define NVIC_IPR2_PRI_9 (0x0000FF00U) ///< Priority of interrupt 9 407 #define NVIC_IPR2_PRI_10 (0x00FF0000U) ///< Priority of interrupt 10 408 #define NVIC_IPR2_PRI_11 (0xFF000000U) ///< Priority of interrupt 11 409 410 //////////////////////////////////////////////////////////////////////////////// 411 /// @brief NVIC_PRI3 Register Bit Definition 412 //////////////////////////////////////////////////////////////////////////////// 413 #define NVIC_IPR3_PRI_12 (0x000000FFU) ///< Priority of interrupt 12 414 #define NVIC_IPR3_PRI_13 (0x0000FF00U) ///< Priority of interrupt 13 415 #define NVIC_IPR3_PRI_14 (0x00FF0000U) ///< Priority of interrupt 14 416 #define NVIC_IPR3_PRI_15 (0xFF000000U) ///< Priority of interrupt 15 417 418 //////////////////////////////////////////////////////////////////////////////// 419 /// @brief NVIC_PRI4 Register Bit Definition 420 //////////////////////////////////////////////////////////////////////////////// 421 #define NVIC_IPR4_PRI_16 (0x000000FFU) ///< Priority of interrupt 16 422 #define NVIC_IPR4_PRI_17 (0x0000FF00U) ///< Priority of interrupt 17 423 #define NVIC_IPR4_PRI_18 (0x00FF0000U) ///< Priority of interrupt 18 424 #define NVIC_IPR4_PRI_19 (0xFF000000U) ///< Priority of interrupt 19 425 426 //////////////////////////////////////////////////////////////////////////////// 427 /// @brief NVIC_PRI5 Register Bit Definition 428 //////////////////////////////////////////////////////////////////////////////// 429 #define NVIC_IPR5_PRI_20 (0x000000FFU) ///< Priority of interrupt 20 430 #define NVIC_IPR5_PRI_21 (0x0000FF00U) ///< Priority of interrupt 21 431 #define NVIC_IPR5_PRI_22 (0x00FF0000U) ///< Priority of interrupt 22 432 #define NVIC_IPR5_PRI_23 (0xFF000000U) ///< Priority of interrupt 23 433 434 //////////////////////////////////////////////////////////////////////////////// 435 /// @brief NVIC_PRI6 Register Bit Definition 436 //////////////////////////////////////////////////////////////////////////////// 437 #define NVIC_IPR6_PRI_24 (0x000000FFU) ///< Priority of interrupt 24 438 #define NVIC_IPR6_PRI_25 (0x0000FF00U) ///< Priority of interrupt 25 439 #define NVIC_IPR6_PRI_26 (0x00FF0000U) ///< Priority of interrupt 26 440 #define NVIC_IPR6_PRI_27 (0xFF000000U) ///< Priority of interrupt 27 441 442 //////////////////////////////////////////////////////////////////////////////// 443 /// @brief NVIC_PRI7 Register Bit Definition 444 //////////////////////////////////////////////////////////////////////////////// 445 #define NVIC_IPR7_PRI_28 (0x000000FFU) ///< Priority of interrupt 28 446 #define NVIC_IPR7_PRI_29 (0x0000FF00U) ///< Priority of interrupt 29 447 #define NVIC_IPR7_PRI_30 (0x00FF0000U) ///< Priority of interrupt 30 448 #define NVIC_IPR7_PRI_31 (0xFF000000U) ///< Priority of interrupt 31 449 450 //////////////////////////////////////////////////////////////////////////////// 451 /// @brief NVIC_PRI8 Register Bit Definition 452 //////////////////////////////////////////////////////////////////////////////// 453 #define NVIC_IPR7_PRI_32 (0x000000FFU) ///< Priority of interrupt 32 454 #define NVIC_IPR7_PRI_33 (0x0000FF00U) ///< Priority of interrupt 33 455 #define NVIC_IPR7_PRI_34 (0x00FF0000U) ///< Priority of interrupt 34 456 #define NVIC_IPR7_PRI_35 (0xFF000000U) ///< Priority of interrupt 35 457 458 //////////////////////////////////////////////////////////////////////////////// 459 /// @brief NVIC_PRI9 Register Bit Definition 460 //////////////////////////////////////////////////////////////////////////////// 461 #define NVIC_IPR7_PRI_36 (0x000000FFU) ///< Priority of interrupt 36 462 #define NVIC_IPR7_PRI_37 (0x0000FF00U) ///< Priority of interrupt 37 463 #define NVIC_IPR7_PRI_38 (0x00FF0000U) ///< Priority of interrupt 38 464 #define NVIC_IPR7_PRI_39 (0xFF000000U) ///< Priority of interrupt 39 465 466 //////////////////////////////////////////////////////////////////////////////// 467 /// @brief NVIC_PRI10 Register Bit Definition 468 //////////////////////////////////////////////////////////////////////////////// 469 #define NVIC_IPR7_PRI_40 (0x000000FFU) ///< Priority of interrupt 40 470 #define NVIC_IPR7_PRI_41 (0x0000FF00U) ///< Priority of interrupt 41 471 #define NVIC_IPR7_PRI_42 (0x00FF0000U) ///< Priority of interrupt 42 472 #define NVIC_IPR7_PRI_43 (0xFF000000U) ///< Priority of interrupt 43 473 474 //////////////////////////////////////////////////////////////////////////////// 475 /// @brief NVIC_PRI11 Register Bit Definition 476 //////////////////////////////////////////////////////////////////////////////// 477 #define NVIC_IPR7_PRI_44 (0x000000FFU) ///< Priority of interrupt 44 478 #define NVIC_IPR7_PRI_45 (0x0000FF00U) ///< Priority of interrupt 45 479 #define NVIC_IPR7_PRI_46 (0x00FF0000U) ///< Priority of interrupt 46 480 #define NVIC_IPR7_PRI_47 (0xFF000000U) ///< Priority of interrupt 47 481 482 //////////////////////////////////////////////////////////////////////////////// 483 /// @brief SCB_CPUID Register Bit Definition 484 //////////////////////////////////////////////////////////////////////////////// 485 #define SCB_CPUID_REVISION (0x0000000FU) ///< Implementation defined revision number 486 #define SCB_CPUID_PARTNO (0x0000FFF0U) ///< Number of processor within family 487 #define SCB_CPUID_Constant (0x000F0000U) ///< Reads as 0x0F 488 #define SCB_CPUID_VARIANT (0x00F00000U) ///< Implementation defined variant number 489 #define SCB_CPUID_IMPLEMENTER (0xFF000000U) ///< Implementer code. ARM is 0x41 490 491 //////////////////////////////////////////////////////////////////////////////// 492 /// @brief SCB_ICSR Register Bit Definition 493 //////////////////////////////////////////////////////////////////////////////// 494 #define SCB_ICSR_VECTACTIVE (0x000001FFU) ///< Active ISR number field 495 #define SCB_ICSR_RETTOBASE (0x00000800U) ///< All active exceptions minus the IPSR_current_exception yields the empty set 496 #define SCB_ICSR_VECTPENDING (0x003FF000U) ///< Pending ISR number field 497 #define SCB_ICSR_ISRPENDING (0x00400000U) ///< Interrupt pending flag 498 #define SCB_ICSR_ISRPREEMPT (0x00800000U) ///< It indicates that a pending interrupt becomes active in the next running cycle 499 #define SCB_ICSR_PENDSTCLR (0x02000000U) ///< Clear pending SysTick bit 500 #define SCB_ICSR_PENDSTSET (0x04000000U) ///< Set pending SysTick bit 501 #define SCB_ICSR_PENDSVCLR (0x08000000U) ///< Clear pending pendSV bit 502 #define SCB_ICSR_PENDSVSET (0x10000000U) ///< Set pending pendSV bit 503 #define SCB_ICSR_NMIPENDSET (0x80000000U) ///< Set pending NMI bit 504 505 //////////////////////////////////////////////////////////////////////////////// 506 /// @brief SCB_VTOR Register Bit Definition 507 //////////////////////////////////////////////////////////////////////////////// 508 #define SCB_VTOR_TBLOFF (0x1FFFFF80U) ///< Vector table base offset field 509 #define SCB_VTOR_TBLBASE (0x20000000U) ///< Table base in code(0) or RAM(1) 510 511 //////////////////////////////////////////////////////////////////////////////// 512 /// @brief SCB_AIRCR Register Bit Definition 513 //////////////////////////////////////////////////////////////////////////////// 514 #define SCB_AIRCR_VECTRESET (0x00000001U) ///< System Reset bit 515 #define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) ///< Clear active vector bit 516 #define SCB_AIRCR_SYSRESETREQ (0x00000004U) ///< Requests chip control logic to generate a reset 517 #define SCB_AIRCR_PRIGROUP (0x00000700U) ///< PRIGROUP[2:0] bits (Priority group) 518 #define SCB_AIRCR_PRIGROUP_0 (0x00000100U) ///< Bit 0 519 #define SCB_AIRCR_PRIGROUP_1 (0x00000200U) ///< Bit 1 520 #define SCB_AIRCR_PRIGROUP_2 (0x00000400U) ///< Bit 2 521 522 #define SCB_AIRCR_PRIGROUP0 (0x00000000U) ///< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) 523 #define SCB_AIRCR_PRIGROUP1 (0x00000100U) ///< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) 524 #define SCB_AIRCR_PRIGROUP2 (0x00000200U) ///< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) 525 #define SCB_AIRCR_PRIGROUP3 (0x00000300U) ///< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) 526 #define SCB_AIRCR_PRIGROUP4 (0x00000400U) ///< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) 527 #define SCB_AIRCR_PRIGROUP5 (0x00000500U) ///< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) 528 #define SCB_AIRCR_PRIGROUP6 (0x00000600U) ///< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) 529 #define SCB_AIRCR_PRIGROUP7 (0x00000700U) ///< Priority group=7 (no pre-emption priority, 8 bits of subpriority) 530 531 #define SCB_AIRCR_ENDIANESS (0x00008000U) ///< Data endianness bit 532 #define SCB_AIRCR_VECTKEY (0xFFFF0000U) ///< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) 533 534 //////////////////////////////////////////////////////////////////////////////// 535 /// @brief SCB_SCR Register Bit Definition 536 //////////////////////////////////////////////////////////////////////////////// 537 #define SCB_SCR_SLEEPONEXIT (0x02U) ///< Sleep on exit bit 538 #define SCB_SCR_SLEEPDEEP (0x04U) ///< Sleep deep bit 539 #define SCB_SCR_SEVONPEND (0x10U) ///< Wake up from WFE 540 541 //////////////////////////////////////////////////////////////////////////////// 542 /// @brief SCB_CCR Register Bit Definition 543 //////////////////////////////////////////////////////////////////////////////// 544 #define SCB_CCR_NONBASETHRDENA (0x0001U) ///< Thread mode can be entered from any level in Handler mode by controlled return value 545 #define SCB_CCR_USERSETMPEND (0x0002U) ///< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception 546 #define SCB_CCR_UNALIGN_TRP (0x0008U) ///< Trap for unaligned access 547 #define SCB_CCR_DIV_0_TRP (0x0010U) ///< Trap on Divide by 0 548 #define SCB_CCR_BFHFNMIGN (0x0100U) ///< Handlers running at priority -1 and -2 549 #define SCB_CCR_STKALIGN (0x0200U) ///< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned 550 551 //////////////////////////////////////////////////////////////////////////////// 552 /// @brief SCB_SHPR Register Bit Definition 553 //////////////////////////////////////////////////////////////////////////////// 554 #define SCB_SHPR_PRI_N (0x000000FFU) ///< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor 555 #define SCB_SHPR_PRI_N1 (0x0000FF00U) ///< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved 556 #define SCB_SHPR_PRI_N2 (0x00FF0000U) ///< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV 557 #define SCB_SHPR_PRI_N3 (0xFF000000U) ///< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick 558 559 //////////////////////////////////////////////////////////////////////////////// 560 /// @brief SCB_SHCSR Register Bit Definition 561 //////////////////////////////////////////////////////////////////////////////// 562 #define SCB_SHCSR_MEMFAULTACT (0x00000001U) ///< MemManage is active 563 #define SCB_SHCSR_BUSFAULTACT (0x00000002U) ///< BusFault is active 564 #define SCB_SHCSR_USGFAULTACT (0x00000008U) ///< UsageFault is active 565 #define SCB_SHCSR_SVCALLACT (0x00000080U) ///< SVCall is active 566 #define SCB_SHCSR_MONITORACT (0x00000100U) ///< Monitor is active 567 #define SCB_SHCSR_PENDSVACT (0x00000400U) ///< PendSV is active 568 #define SCB_SHCSR_SYSTICKACT (0x00000800U) ///< SysTick is active 569 #define SCB_SHCSR_USGFAULTPENDED (0x00001000U) ///< Usage Fault is pended 570 #define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) ///< MemManage is pended 571 #define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) ///< Bus Fault is pended 572 #define SCB_SHCSR_SVCALLPENDED (0x00008000U) ///< SVCall is pended 573 #define SCB_SHCSR_MEMFAULTENA (0x00010000U) ///< MemManage enable 574 #define SCB_SHCSR_BUSFAULTENA (0x00020000U) ///< Bus Fault enable 575 #define SCB_SHCSR_USGFAULTENA (0x00040000U) ///< UsageFault enable 576 577 //////////////////////////////////////////////////////////////////////////////// 578 /// @brief SCB_CFSR Register Bit Definition 579 //////////////////////////////////////////////////////////////////////////////// 580 ///< MFSR 581 #define SCB_CFSR_IACCVIOL (0x00000001U) ///< Instruction access violation 582 #define SCB_CFSR_DACCVIOL (0x00000002U) ///< Data access violation 583 #define SCB_CFSR_MUNSTKERR (0x00000008U) ///< Unstacking error 584 #define SCB_CFSR_MSTKERR (0x00000010U) ///< Stacking error 585 #define SCB_CFSR_MMARVALID (0x00000080U) ///< Memory Manage Address Register address valid flag 586 ///< BFSR 587 #define SCB_CFSR_IBUSERR (0x00000100U) ///< Instruction bus error flag 588 #define SCB_CFSR_PRECISERR (0x00000200U) ///< Precise data bus error 589 #define SCB_CFSR_IMPRECISERR (0x00000400U) ///< Imprecise data bus error 590 #define SCB_CFSR_UNSTKERR (0x00000800U) ///< Unstacking error 591 #define SCB_CFSR_STKERR (0x00001000U) ///< Stacking error 592 #define SCB_CFSR_BFARVALID (0x00008000U) ///< Bus Fault Address Register address valid flag 593 ///< UFSR 594 #define SCB_CFSR_UNDEFINSTR (0x00010000U) ///< The processor attempt to excecute an undefined instruction 595 #define SCB_CFSR_INVSTATE (0x00020000U) ///< Invalid combination of EPSR and instruction 596 #define SCB_CFSR_INVPC (0x00040000U) ///< Attempt to load EXC_RETURN into pc illegally 597 #define SCB_CFSR_NOCP (0x00080000U) ///< Attempt to use a coprocessor instruction 598 #define SCB_CFSR_UNALIGNED (0x01000000U) ///< Fault occurs when there is an attempt to make an unaligned memory access 599 #define SCB_CFSR_DIVBYZERO (0x02000000U) ///< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 600 601 //////////////////////////////////////////////////////////////////////////////// 602 /// @brief SCB_HFSR Register Bit Definition 603 //////////////////////////////////////////////////////////////////////////////// 604 #define SCB_HFSR_VECTTBL (0x00000002U) ///< Fault occures because of vector table read on exception processing 605 #define SCB_HFSR_FORCED (0x40000000U) ///< Hard Fault activated when a configurable Fault was received and cannot activate 606 #define SCB_HFSR_DEBUGEVT (0x80000000U) ///< Fault related to debug 607 608 //////////////////////////////////////////////////////////////////////////////// 609 /// @brief SCB_DFSR Register Bit Definition 610 //////////////////////////////////////////////////////////////////////////////// 611 #define SCB_DFSR_HALTED (0x01U) ///< Halt request flag 612 #define SCB_DFSR_BKPT (0x02U) ///< BKPT flag 613 #define SCB_DFSR_DWTTRAP (0x04U) ///< Data Watchpoint and Trace (DWT) flag 614 #define SCB_DFSR_VCATCH (0x08U) ///< Vector catch flag 615 #define SCB_DFSR_EXTERNAL (0x10U) ///< External debug request flag 616 617 //////////////////////////////////////////////////////////////////////////////// 618 /// @brief SCB_MMFAR Register Bit Definition 619 //////////////////////////////////////////////////////////////////////////////// 620 #define SCB_MMFAR_ADDRESS (0xFFFFFFFFU) ///< Mem Manage fault address field 621 622 //////////////////////////////////////////////////////////////////////////////// 623 /// @brief SCB_BFAR Register Bit Definition 624 //////////////////////////////////////////////////////////////////////////////// 625 #define SCB_BFAR_ADDRESS (0xFFFFFFFFU) ///< Bus fault address field 626 627 //////////////////////////////////////////////////////////////////////////////// 628 /// @brief SCB_AFSR Register Bit Definition 629 //////////////////////////////////////////////////////////////////////////////// 630 #define SCB_AFSR_IMPDEF (0xFFFFFFFFU) ///< Implementation defined 631 632 633 634 #endif 635 /// @} 636 637 /// @} 638 639 /// @} 640 641 //////////////////////////////////////////////////////////////////////////////// 642 643 //////////////////////////////////////////////////////////////////////////////// 644