1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_crs.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_CRS_H 22 #define __REG_CRS_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 44 //////////////////////////////////////////////////////////////////////////////// 45 /// @brief CRS Base Address Definition 46 //////////////////////////////////////////////////////////////////////////////// 47 #define CRS_BASE (APB1PERIPH_BASE + 0x6C00) ///< Base Address: 0x40006C00 48 49 50 51 //////////////////////////////////////////////////////////////////////////////// 52 /// @brief CRS Register Structure Definition 53 //////////////////////////////////////////////////////////////////////////////// 54 typedef struct { 55 __IO u32 CR; ///< Control Register offset: 0x00 56 __IO u32 CFGR; ///< Configuration Register offset: 0x04 57 __IO u32 ISR; ///< Interrupt and Status Register offset: 0x08 58 __IO u32 ICR; ///< Interrupt Flag Clear Register offset: 0x0C 59 } CRS_TypeDef; 60 61 62 63 //////////////////////////////////////////////////////////////////////////////// 64 /// @brief CRS type pointer Definition 65 //////////////////////////////////////////////////////////////////////////////// 66 #define CRS ((CRS_TypeDef*) CRS_BASE) 67 68 69 70 //////////////////////////////////////////////////////////////////////////////// 71 /// @brief CRS_CR Register Bit Definition 72 //////////////////////////////////////////////////////////////////////////////// 73 #define CRS_CR_OKIE_Pos (0) 74 #define CRS_CR_OKIE (0x01U << CRS_CR_OKIE_Pos) ///< SYNC event OK interrupt enable 75 #define CRS_CR_WARNIE_Pos (1) 76 #define CRS_CR_WARNIE (0x01U << CRS_CR_WARNIE_Pos) ///< SYNC warning interrupt enable 77 #define CRS_CR_ERRIE_Pos (2) 78 #define CRS_CR_ERRIE (0x01U << CRS_CR_ERRIE_Pos) ///< Synchronization or trimming error interrupt enable 79 #define CRS_CR_EXPTIE_Pos (3) 80 #define CRS_CR_EXPTIE (0x01U << CRS_CR_EXPTIE_Pos) ///< Expected SYNC interrupt enable 81 #define CRS_CR_CNTEN_Pos (5) 82 #define CRS_CR_CNTEN (0x01U << CRS_CR_CNTEN_Pos) ///< Frequency error counter enable 83 #define CRS_CR_AUTOTRIMEN_Pos (6) 84 #define CRS_CR_AUTOTRIMEN (0x01U << CRS_CR_AUTOTRIMEN_Pos) ///< Automatic trimming enable 85 #define CRS_CR_SWSYNC_Pos (7) 86 #define CRS_CR_SWSYNC (0x01U << CRS_CR_SWSYNC_Pos) ///< Generate software SYNC event 87 #define CRS_CR_TRIM_Pos (8) 88 #define CRS_CR_TRIM (0x3FFU << CRS_CR_TRIM_Pos) ///< HSI 48 oscillator smooth trimming 89 90 //////////////////////////////////////////////////////////////////////////////// 91 /// @brief CRS_CFGR Register Bit Definition 92 //////////////////////////////////////////////////////////////////////////////// 93 #define CRS_CFGR_RELOAD_Pos (0) 94 #define CRS_CFGR_RELOAD (0xFFFFU << CRS_CFGR_RELOAD_Pos) ///< Counter reload value 95 #define CRS_CFGR_FELIM_Pos (16) 96 #define CRS_CFGR_FELIM (0xFFU << CRS_CFGR_FELIM_Pos) ///< Frequency error limit 97 #define CRS_CFGR_DIV_Pos (24) 98 #define CRS_CFGR_DIV (0x07U << CRS_CFGR_DIV_Pos) ///< SYNC divider 99 #define CRS_CFGR_SRC_Pos (28) 100 #define CRS_CFGR_SRC (0x03U << CRS_CFGR_SRC_Pos) ///< SYNC signal source selection 101 #define CRS_CFGR_SRC_MCO (0x00U << CRS_CFGR_SRC_Pos) 102 #define CRS_CFGR_SRC_USBSOF (0x02U << CRS_CFGR_SRC_Pos) 103 #define CRS_CFGR_POL_Pos (31) 104 #define CRS_CFGR_POL (0x01U << CRS_CFGR_POL_Pos) ///< SYNC polarity selection 105 106 //////////////////////////////////////////////////////////////////////////////// 107 /// @brief CRS_ISR Register Bit Definition 108 //////////////////////////////////////////////////////////////////////////////// 109 #define CRS_ISR_OKIF_Pos (0) 110 #define CRS_ISR_OKIF (0x01U << CRS_ISR_OKIF_Pos) ///< SYNC event OK flag 111 #define CRS_ISR_WARNIF_Pos (1) 112 #define CRS_ISR_WARNIF (0x01U << CRS_ISR_WARNIF_Pos) ///< SYNC warning flag 113 #define CRS_ISR_ERRIF_Pos (2) 114 #define CRS_ISR_ERRIF (0x01U << CRS_ISR_ERRIF_Pos) ///< Error flag 115 #define CRS_ISR_EXPTIF_Pos (3) 116 #define CRS_ISR_EXPTIF (0x01U << CRS_ISR_EXPTIF_Pos) ///< Expected SYNC flag 117 #define CRS_ISR_ERR_Pos (8) 118 #define CRS_ISR_ERR (0x01U << CRS_ISR_ERR_Pos) ///< SYNC error 119 #define CRS_ISR_MISS_Pos (9) 120 #define CRS_ISR_MISS (0x01U << CRS_ISR_MISS_Pos) ///< SYNC missed 121 #define CRS_ISR_OVERFLOW_Pos (10) 122 #define CRS_ISR_OVERFLOW (0x01U << CRS_ISR_OVERFLOW_Pos) ///< Trimming overflow or underflow 123 #define CRS_ISR_FEDIR_Pos (15) 124 #define CRS_ISR_FEDIR (0x01U << CRS_ISR_FEDIR_Pos) ///< Frequency error direction 125 #define CRS_ISR_FECAP_Pos (16) 126 #define CRS_ISR_FECAP (0xFFFFU << CRS_ISR_FECAP_Pos) ///< Frequency error capture 127 128 //////////////////////////////////////////////////////////////////////////////// 129 /// @brief CRS_ICR Register Bit Definition 130 //////////////////////////////////////////////////////////////////////////////// 131 #define CRS_ICR_OK_Pos (0) 132 #define CRS_ICR_OK (0x01U << CRS_ICR_OK_Pos) ///< SYNC event OK clear flag 133 #define CRS_ICR_WARN_Pos (1) 134 #define CRS_ICR_WARN (0x01U << CRS_ICR_WARN_Pos) ///< SYNC warning clear flag 135 #define CRS_ICR_ERR_Pos (2) 136 #define CRS_ICR_ERR (0x01U << CRS_ICR_ERR_Pos) ///< Error clear flag 137 #define CRS_ICR_EXPT_Pos (3) 138 #define CRS_ICR_EXPT (0x01U << CRS_ICR_EXPT_Pos) ///< Expected SYNC clear flag 139 140 141 142 143 144 /// @} 145 146 /// @} 147 148 /// @} 149 150 //////////////////////////////////////////////////////////////////////////////// 151 #endif 152 //////////////////////////////////////////////////////////////////////////////// 153