1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_dac.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_DAC_H 22 #define __REG_DAC_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 44 //////////////////////////////////////////////////////////////////////////////// 45 /// @brief DAC Base Address Definition 46 //////////////////////////////////////////////////////////////////////////////// 47 #define DAC_BASE (APB1PERIPH_BASE + 0x7400) ///< Base Address: 0x40007400 48 49 50 51 //////////////////////////////////////////////////////////////////////////////// 52 /// @brief Digital to analog converter register 53 //////////////////////////////////////////////////////////////////////////////// 54 typedef struct { 55 __IO u32 CR; ///< DAC control register, offset: 0x00 56 __IO u32 SWTRIGR; ///< DAC software trigger register, offset: 0x04 57 __IO u32 DHR12R1; ///< Channel 1 12-bit right align data register, offset: 0x08 58 __IO u32 DHR12L1; ///< Channel 1 12-bit left align data register, offset: 0x0C 59 __IO u32 DHR8R1; ///< Channel 1 8-bit right align data register, offset: 0x10 60 __IO u32 DHR12R2; ///< Channel 2 12-bit right align data register, offset: 0x14 61 __IO u32 DHR12L2; ///< Channel 2 12-bit left align data register, offset: 0x18 62 __IO u32 DHR8R2; ///< Channel 2 8-bit right align data register, offset: 0x1C 63 __IO u32 DHR12RD; ///< Dual channel 12-bit right align data register,offset: 0x20 64 __IO u32 DHR12LD; ///< Dual channel 12-bit left align data register, offset: 0x24 65 __IO u32 DHR8RD; ///< Dual channel 8-bit right align data register, offset: 0x28 66 __IO u32 DOR1; ///< Channel 1 output register, offset: 0x2C 67 __IO u32 DOR2; ///< Channel 2 output register, offset: 0x30 68 } DAC_TypeDef; 69 70 71 72 //////////////////////////////////////////////////////////////////////////////// 73 /// @brief DAC type pointer Definition 74 //////////////////////////////////////////////////////////////////////////////// 75 #define DAC ((DAC_TypeDef*) DAC_BASE) 76 77 78 79 //////////////////////////////////////////////////////////////////////////////// 80 /// @brief DAC_CR Register Bit Definition 81 //////////////////////////////////////////////////////////////////////////////// 82 #define DAC_CR_EN1_Pos (0) 83 #define DAC_CR_EN1 (0x01U << DAC_CR_EN1_Pos) ///< DAC channel1 enable 84 #define DAC_CR_BOFF1_Pos (1) 85 #define DAC_CR_BOFF1 (0x01U << DAC_CR_BOFF1_Pos) ///< DAC channel1 output buffer disable 86 #define DAC_CR_TEN1_Pos (2) 87 #define DAC_CR_TEN1 (0x01U << DAC_CR_TEN1_Pos) ///< DAC channel1 Trigger enable 88 #define DAC_CR_TSEL1_Pos (3) 89 #define DAC_CR_TSEL1 (0x07U << DAC_CR_TSEL1_Pos) ///< TSEL1[2:0] (DAC channel1 Trigger selection) 90 #define DAC_CR_TSEL1_TIM1_TRIG (0x00U << DAC_CR_TSEL1_Pos) ///< TIM1_TRIG trigger 91 #define DAC_CR_TSEL1_TIM3_TRIG (0x01U << DAC_CR_TSEL1_Pos) ///< TIM3_TRIG trigger 92 #define DAC_CR_TSEL1_TIM2_TRIG (0x04U << DAC_CR_TSEL1_Pos) ///< TIM2_TRIG trigger 93 #define DAC_CR_TSEL1_TIM4_TRIG (0x05U << DAC_CR_TSEL1_Pos) ///< TIM4_TRIG trigger 94 #define DAC_CR_TSEL1_EXTI9 (0x06U << DAC_CR_TSEL1_Pos) ///< External interrupt line 9 trigger 95 #define DAC_CR_TSEL1_SOFTWARE (0x07U << DAC_CR_TSEL1_Pos) ///< Software trigger 96 #define DAC_CR_WAVE1_Pos (6) 97 #define DAC_CR_WAVE1 (0x03U << DAC_CR_WAVE1_Pos) ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) 98 #define DAC_CR_WAVE1_NONE (0x00U << DAC_CR_WAVE1_Pos) ///< Turn off waveform generation 99 #define DAC_CR_WAVE1_NOISE (0x01U << DAC_CR_WAVE1_Pos) ///< Noise waveform generation 100 #define DAC_CR_WAVE1_TRIANGLE (0x02U << DAC_CR_WAVE1_Pos) ///< Triangle wave generation 101 #define DAC_CR_MAMP1_Pos (8) 102 #define DAC_CR_MAMP1 (0x0FU << DAC_CR_MAMP1_Pos) ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) 103 #define DAC_CR_MAMP1_1 (0x00U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 1 104 #define DAC_CR_MAMP1_3 (0x01U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 3 105 #define DAC_CR_MAMP1_7 (0x02U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 7 106 #define DAC_CR_MAMP1_15 (0x03U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 15 107 #define DAC_CR_MAMP1_31 (0x04U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 31 108 #define DAC_CR_MAMP1_63 (0x05U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 63 109 #define DAC_CR_MAMP1_127 (0x06U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 127 110 #define DAC_CR_MAMP1_255 (0x07U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 255 111 #define DAC_CR_MAMP1_511 (0x08U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 511 112 #define DAC_CR_MAMP1_1023 (0x09U << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 1023 113 #define DAC_CR_MAMP1_2047 (0x0AU << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 2047 114 #define DAC_CR_MAMP1_4095 (0x0BU << DAC_CR_MAMP1_Pos) ///< Triangle wave amplitude equal to 4095 115 #define DAC_CR_DMAEN1_Pos (12) 116 #define DAC_CR_DMAEN1 (0x01U << DAC_CR_DMAEN1_Pos) ///< DAC channel1 DMA enable 117 #define DAC_CR_EN2_Pos (16) 118 #define DAC_CR_EN2 (0x01U << DAC_CR_EN2_Pos) ///< DAC channel2 enable 119 #define DAC_CR_BOFF2_Pos (17) 120 #define DAC_CR_BOFF2 (0x01U << DAC_CR_BOFF2_Pos) ///< DAC channel2 output buffer disable 121 #define DAC_CR_TEN2_Pos (18) 122 #define DAC_CR_TEN2 (0x01U << DAC_CR_TEN2_Pos) ///< DAC channel2 Trigger enable 123 #define DAC_CR_TSEL2_Pos (19) 124 #define DAC_CR_TSEL2 (0x07U << DAC_CR_TSEL2_Pos) ///< TSEL1[2:0] (DAC channel1 Trigger selection) 125 #define DAC_CR_TSEL2_TIM1_TRIG (0x00U << DAC_CR_TSEL2_Pos) ///< TIM1_TRIG trigger 126 #define DAC_CR_TSEL2_TIM3_TRIG (0x01U << DAC_CR_TSEL2_Pos) ///< TIM3_TRIG trigger 127 #define DAC_CR_TSEL2_TIM2_TRIG (0x04U << DAC_CR_TSEL2_Pos) ///< TIM2_TRIG trigger 128 #define DAC_CR_TSEL2_TIM4_TRIG (0x05U << DAC_CR_TSEL2_Pos) ///< TIM4_TRIG trigger 129 #define DAC_CR_TSEL2_EXTI9 (0x06U << DAC_CR_TSEL2_Pos) ///< External interrupt line 9 trigger 130 #define DAC_CR_TSEL2_SOFTWARE (0x07U << DAC_CR_TSEL2_Pos) ///< Software trigger 131 #define DAC_CR_WAVE2_Pos (22) 132 #define DAC_CR_WAVE2 (0x03U << DAC_CR_WAVE2_Pos) ///< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) 133 #define DAC_CR_WAVE2_NONE (0x00U << DAC_CR_WAVE2_Pos) ///< Turn off waveform generation 134 #define DAC_CR_WAVE2_NOISE (0x01U << DAC_CR_WAVE2_Pos) ///< Noise waveform generation 135 #define DAC_CR_WAVE2_TRIANGLE (0x02U << DAC_CR_WAVE2_Pos) ///< Triangle wave generation 136 #define DAC_CR_MAMP2_Pos (24) 137 #define DAC_CR_MAMP2 (0x0FU << DAC_CR_MAMP2_Pos) ///< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) 138 #define DAC_CR_MAMP2_1 (0x00U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 1 139 #define DAC_CR_MAMP2_3 (0x01U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 3 140 #define DAC_CR_MAMP2_7 (0x02U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 7 141 #define DAC_CR_MAMP2_15 (0x03U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 15 142 #define DAC_CR_MAMP2_31 (0x04U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 31 143 #define DAC_CR_MAMP2_63 (0x05U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 63 144 #define DAC_CR_MAMP2_127 (0x06U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 127 145 #define DAC_CR_MAMP2_255 (0x07U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 255 146 #define DAC_CR_MAMP2_511 (0x08U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 511 147 #define DAC_CR_MAMP2_1023 (0x09U << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 1023 148 #define DAC_CR_MAMP2_2047 (0x0AU << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 2047 149 #define DAC_CR_MAMP2_4095 (0x0BU << DAC_CR_MAMP2_Pos) ///< Triangle wave amplitude equal to 4095 150 #define DAC_CR_DMAEN2_Pos (28) 151 #define DAC_CR_DMAEN2 (0x01U << DAC_CR_DMAEN2_Pos) ///< DAC channel2 DMA enabled 152 153 //////////////////////////////////////////////////////////////////////////////// 154 /// @brief DAC_SWTRIGR Register Bit Definition 155 //////////////////////////////////////////////////////////////////////////////// 156 #define DAC_SWTRIGR_SWTRIG1_Pos (0) 157 #define DAC_SWTRIGR_SWTRIG1 (0x01U << DAC_SWTRIGR_SWTRIG1_Pos) ///< DAC channel1 software trigger 158 #define DAC_SWTRIGR_SWTRIG2_Pos (1) 159 #define DAC_SWTRIGR_SWTRIG2 (0x01U << DAC_SWTRIGR_SWTRIG2_Pos) ///< DAC channel2 software trigger 160 #define DAC_SWTRIGR_DACPRE_Pos (8) 161 #define DAC_SWTRIGR_DACPRE (0x7FU << DAC_SWTRIGR_DACPRE_Pos) ///< DAC prescale 162 163 //////////////////////////////////////////////////////////////////////////////// 164 /// @brief DAC_DHR12R1 Register Bit Definition 165 //////////////////////////////////////////////////////////////////////////////// 166 #define DAC_DHR12R1_DACC1DHR_Pos (0) 167 #define DAC_DHR12R1_DACC1DHR (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data 168 169 //////////////////////////////////////////////////////////////////////////////// 170 /// @brief DAC_DHR12L1 Register Bit Definition 171 //////////////////////////////////////////////////////////////////////////////// 172 #define DAC_DHR12L1_DACC1DHR_Pos (4) 173 #define DAC_DHR12L1_DACC1DHR (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) ///< DAC channel1 12-bit Left align data 174 175 //////////////////////////////////////////////////////////////////////////////// 176 /// @brief DAC_DHR8R1 Register Bit Definition 177 //////////////////////////////////////////////////////////////////////////////// 178 #define DAC_DHR8R1_DACC1DHR_Pos (0) 179 #define DAC_DHR8R1_DACC1DHR (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) ///< DAC channel1 8-bit Right align data 180 181 //////////////////////////////////////////////////////////////////////////////// 182 /// @brief DAC_DHR12R2 Register Bit Definition 183 //////////////////////////////////////////////////////////////////////////////// 184 #define DAC_DHR12R2_DACC2DHR_Pos (0) 185 #define DAC_DHR12R2_DACC2DHR (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data 186 187 //////////////////////////////////////////////////////////////////////////////// 188 /// @brief DAC_DHR12L2 Register Bit Definition 189 //////////////////////////////////////////////////////////////////////////////// 190 #define DAC_DHR12L2_DACC2DHR_Pos (4) 191 #define DAC_DHR12L2_DACC2DHR (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) ///< DAC channel2 12-bit Left align data 192 193 //////////////////////////////////////////////////////////////////////////////// 194 /// @brief DAC_DHR8R2 Register Bit Definition 195 //////////////////////////////////////////////////////////////////////////////// 196 #define DAC_DHR8R2_DACC2DHR_Pos (0) 197 #define DAC_DHR8R2_DACC2DHR (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) ///< DAC channel2 8-bit Right align data 198 199 //////////////////////////////////////////////////////////////////////////////// 200 /// @brief DAC_DHR12RD Register Bit Definition 201 //////////////////////////////////////////////////////////////////////////////// 202 #define DAC_DHR12RD_DACC1DHR_Pos (0) 203 #define DAC_DHR12RD_DACC1DHR (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data 204 #define DAC_DHR12RD_DACC2DHR_Pos (16) 205 #define DAC_DHR12RD_DACC2DHR (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data 206 207 //////////////////////////////////////////////////////////////////////////////// 208 /// @brief DAC_DHR12LD Register Bit Definition 209 //////////////////////////////////////////////////////////////////////////////// 210 #define DAC_DHR12LD_DACC1DHR_Pos (4) 211 #define DAC_DHR12LD_DACC1DHR (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) ///< DAC channel1 12-bit Right align data 212 #define DAC_DHR12LD_DACC2DHR_Pos (20) 213 #define DAC_DHR12LD_DACC2DHR (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) ///< DAC channel2 12-bit Right align data 214 215 //////////////////////////////////////////////////////////////////////////////// 216 /// @brief DAC_DHR8RD Register Bit Definition 217 //////////////////////////////////////////////////////////////////////////////// 218 #define DAC_DHR8RD_DACC1DHR_Pos (0) 219 #define DAC_DHR8RD_DACC1DHR (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) ///< DAC channel1 8-bit Right align data 220 #define DAC_DHR8RD_DACC2DHR_Pos (8) 221 #define DAC_DHR8RD_DACC2DHR (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) ///< DAC channel2 8-bit Right align data 222 223 //////////////////////////////////////////////////////////////////////////////// 224 /// @brief DAC_DOR1 Register Bit Definition 225 //////////////////////////////////////////////////////////////////////////////// 226 #define DAC_DOR1_DACC1DOR_Pos (0) 227 #define DAC_DOR1_DACC1DOR (0xFFFU << DAC_DOR1_DACC1DOR_Pos) ///< DAC channel1 data output 228 229 //////////////////////////////////////////////////////////////////////////////// 230 /// @brief DAC_DOR2 Register Bit Definition 231 //////////////////////////////////////////////////////////////////////////////// 232 #define DAC_DOR2_DACC2DOR_Pos (0) 233 #define DAC_DOR2_DACC2DOR (0xFFFU << DAC_DOR2_DACC2DOR_Pos) ///< DAC channel2 data output #endif 234 235 236 237 238 239 /// @} 240 241 /// @} 242 243 /// @} 244 245 //////////////////////////////////////////////////////////////////////////////// 246 #endif 247 //////////////////////////////////////////////////////////////////////////////// 248