1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_exti.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_EXTI_H 22 #define __REG_EXTI_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 44 45 //////////////////////////////////////////////////////////////////////////////// 46 /// @brief EXTI Base Address Definition 47 //////////////////////////////////////////////////////////////////////////////// 48 #define EXTI_BASE (APB2PERIPH_BASE + 0x0000) ///< Base Address: 0x40010000 49 50 51 52 //////////////////////////////////////////////////////////////////////////////// 53 /// @brief EXTI Registers Structure Definition 54 //////////////////////////////////////////////////////////////////////////////// 55 typedef struct { 56 __IO u32 CFGR; ///< configuration register, offset: 0x00 57 u32 Reserved; ///< Reserved offset: 0x04 58 __IO u32 CR[4]; ///< External interrupt configuration register, offset: 0x08 - 0x14 59 __IO u32 CFGR2; ///< configuration register offset: 0x18 60 __IO u32 PDETCSR; ///< Power detection configuration status register offset: 0x1C 61 __IO u32 VOSDLY; ///< VOS delay time offset: 0x20 62 u32 Reserved1[0x100 - 0x09]; ///< Reserved space 63 __IO u32 IMR; ///< Interrupt Mask Register offset: 0x00 + 0x400 64 __IO u32 EMR; ///< Event Mask Register offset: 0x04 + 0x400 65 __IO u32 RTSR; ///< Rising Trigger Status Register offset: 0x08 + 0x400 66 __IO u32 FTSR; ///< Falling Trigger Status Register offset: 0x0C + 0x400 67 __IO u32 SWIER; ///< Software Interrupt Enable Register offset: 0x10 + 0x400 68 __IO u32 PR; ///< Pending Register offset: 0x14 + 0x400 69 } EXTI_TypeDef; 70 71 72 73 //////////////////////////////////////////////////////////////////////////////// 74 /// @brief EXTI type pointer Definition 75 //////////////////////////////////////////////////////////////////////////////// 76 #define EXTI ((EXTI_TypeDef*) EXTI_BASE) 77 78 79 80 //////////////////////////////////////////////////////////////////////////////// 81 /// @brief EXTI_CFGR Register Bit Definition 82 //////////////////////////////////////////////////////////////////////////////// 83 #define EXTI_CFGR_MEMMODE_Pos (0) 84 #define EXTI_CFGR_MEMMODE (0x03U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config 85 #define EXTI_CFGR_MEMMODE_0 (0x01U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Bit 0 86 #define EXTI_CFGR_MEMMODE_1 (0x02U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Bit 1 87 #define EXTI_CFGR_FLASH_MEMORY (0x00U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 0 88 #define EXTI_CFGR_SYSTEM_MEMORY (0x01U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 1 89 #define EXTI_CFGR_SRAM_MEMORY (0x03U << EXTI_CFGR_MEMMODE_Pos) ///< EXTI_Memory Remap Config Mode 3 90 91 92 #define EXTI_CFGR_FC_SYNCEN_Pos (27) 93 #define EXTI_CFGR_FC_SYNCEN (0x01U << EXTI_CFGR_FC_SYNCEN_Pos) ///< FSMC synchronization enable 94 #define EXTI_CFGR_FC_ODATAEN_Pos (28) 95 #define EXTI_CFGR_FC_ODATAEN (0x01U << EXTI_CFGR_FC_ODATAEN_Pos) ///< FSMC Only used as data pin 96 #define EXTI_CFGR_MODESEL_Pos (29) ///< FSMC mode selection 97 #define EXTI_CFGR_MODESEL0 (0x00U << EXTI_CFGR_MODESEL0_Pos) ///< Compatible with 8080 protocol interface 98 #define EXTI_CFGR_MODESEL1 (0x01U << EXTI_CFGR_MODESEL1_Pos) ///< Compatible with NOR FLASH protocol interface 99 100 101 //////////////////////////////////////////////////////////////////////////////// 102 /// @brief EXTI_CR1 Register Bit Definition 103 //////////////////////////////////////////////////////////////////////////////// 104 #define EXTI_CR1_EXTI0_Pos (0) 105 #define EXTI_CR1_EXTI0 (0x0FU << EXTI_CR1_EXTI0_Pos) ///< EXTI 0 configuration 106 #define EXTI_CR1_EXTI0_PA (0x00U << EXTI_CR1_EXTI0_Pos) ///< PA[0] pin 107 #define EXTI_CR1_EXTI0_PB (0x01U << EXTI_CR1_EXTI0_Pos) ///< PB[0] pin 108 #define EXTI_CR1_EXTI0_PC (0x02U << EXTI_CR1_EXTI0_Pos) ///< PC[0] pin 109 #define EXTI_CR1_EXTI0_PD (0x03U << EXTI_CR1_EXTI0_Pos) ///< PD[0] pin 110 111 #define EXTI_CR1_EXTI1_Pos (4) 112 #define EXTI_CR1_EXTI1 (0x0FU << EXTI_CR1_EXTI1_Pos) ///< EXTI 1 configuration 113 #define EXTI_CR1_EXTI1_PA (0x00U << EXTI_CR1_EXTI1_Pos) ///< PA[1] pin 114 #define EXTI_CR1_EXTI1_PB (0x01U << EXTI_CR1_EXTI1_Pos) ///< PB[1] pin 115 #define EXTI_CR1_EXTI1_PC (0x02U << EXTI_CR1_EXTI1_Pos) ///< PC[1] pin 116 #define EXTI_CR1_EXTI1_PD (0x03U << EXTI_CR1_EXTI1_Pos) ///< PD[1] pin 117 118 #define EXTI_CR1_EXTI2_Pos (8) 119 #define EXTI_CR1_EXTI2 (0x0FU << EXTI_CR1_EXTI2_Pos) ///< EXTI 2 configuration 120 #define EXTI_CR1_EXTI2_PA (0x00U << EXTI_CR1_EXTI2_Pos) ///< PA[2] pin 121 #define EXTI_CR1_EXTI2_PB (0x01U << EXTI_CR1_EXTI2_Pos) ///< PB[2] pin 122 #define EXTI_CR1_EXTI2_PC (0x02U << EXTI_CR1_EXTI2_Pos) ///< PC[2] pin 123 #define EXTI_CR1_EXTI2_PD (0x03U << EXTI_CR1_EXTI2_Pos) ///< PD[2] pin 124 125 #define EXTI_CR1_EXTI3_Pos (12) 126 #define EXTI_CR1_EXTI3 (0x0FU << EXTI_CR1_EXTI3_Pos) ///< EXTI 3 configuration 127 #define EXTI_CR1_EXTI3_PA (0x00U << EXTI_CR1_EXTI3_Pos) ///< PA[3] pin 128 #define EXTI_CR1_EXTI3_PB (0x01U << EXTI_CR1_EXTI3_Pos) ///< PB[3] pin 129 #define EXTI_CR1_EXTI3_PC (0x02U << EXTI_CR1_EXTI3_Pos) ///< PC[3] pin 130 #define EXTI_CR1_EXTI3_PD (0x03U << EXTI_CR1_EXTI3_Pos) ///< PD[3] pin 131 132 //////////////////////////////////////////////////////////////////////////////// 133 /// @brief EXTI_CR2 Register Bit Definition 134 //////////////////////////////////////////////////////////////////////////////// 135 #define EXTI_CR2_EXTI4_Pos (0) 136 #define EXTI_CR2_EXTI4 (0x0FU << EXTI_CR2_EXTI4_Pos) ///< EXTI 4 configuration 137 #define EXTI_CR2_EXTI4_PA (0x00U << EXTI_CR2_EXTI4_Pos) ///< PA[4] pin 138 #define EXTI_CR2_EXTI4_PB (0x01U << EXTI_CR2_EXTI4_Pos) ///< PB[4] pin 139 #define EXTI_CR2_EXTI4_PC (0x02U << EXTI_CR2_EXTI4_Pos) ///< PC[4] pin 140 #define EXTI_CR2_EXTI4_PD (0x03U << EXTI_CR2_EXTI4_Pos) ///< PD[4] pin 141 142 #define EXTI_CR2_EXTI5_Pos (4) 143 #define EXTI_CR2_EXTI5 (0x0FU << EXTI_CR2_EXTI5_Pos) ///< EXTI 5 configuration 144 #define EXTI_CR2_EXTI5_PA (0x00U << EXTI_CR2_EXTI5_Pos) ///< PA[5] pin 145 #define EXTI_CR2_EXTI5_PB (0x01U << EXTI_CR2_EXTI5_Pos) ///< PB[5] pin 146 #define EXTI_CR2_EXTI5_PC (0x02U << EXTI_CR2_EXTI5_Pos) ///< PC[5] pin 147 #define EXTI_CR2_EXTI5_PD (0x03U << EXTI_CR2_EXTI5_Pos) ///< PD[5] pin 148 149 #define EXTI_CR2_EXTI6_Pos (8) 150 #define EXTI_CR2_EXTI6 (0x0FU << EXTI_CR2_EXTI6_Pos) ///< EXTI 6 configuration 151 #define EXTI_CR2_EXTI6_PA (0x00U << EXTI_CR2_EXTI6_Pos) ///< PA[6] pin 152 #define EXTI_CR2_EXTI6_PB (0x01U << EXTI_CR2_EXTI6_Pos) ///< PB[6] pin 153 #define EXTI_CR2_EXTI6_PC (0x02U << EXTI_CR2_EXTI6_Pos) ///< PC[6] pin 154 #define EXTI_CR2_EXTI6_PD (0x03U << EXTI_CR2_EXTI6_Pos) ///< PD[6] pin 155 156 #define EXTI_CR2_EXTI7_Pos (12) 157 #define EXTI_CR2_EXTI7 (0x0FU << EXTI_CR2_EXTI7_Pos) ///< EXTI 7 configuration 158 #define EXTI_CR2_EXTI7_PA (0x00U << EXTI_CR2_EXTI7_Pos) ///< PA[7] pin 159 #define EXTI_CR2_EXTI7_PB (0x01U << EXTI_CR2_EXTI7_Pos) ///< PB[7] pin 160 #define EXTI_CR2_EXTI7_PC (0x02U << EXTI_CR2_EXTI7_Pos) ///< PC[7] pin 161 #define EXTI_CR2_EXTI7_PD (0x03U << EXTI_CR2_EXTI7_Pos) ///< PD[7] pin 162 163 //////////////////////////////////////////////////////////////////////////////// 164 /// @brief EXTI_CR3 Register Bit Definition 165 //////////////////////////////////////////////////////////////////////////////// 166 #define EXTI_CR3_EXTI8_Pos (0) 167 #define EXTI_CR3_EXTI8 (0x0FU << EXTI_CR3_EXTI8_Pos) ///< EXTI 8 configuration 168 #define EXTI_CR3_EXTI8_PA (0x00U << EXTI_CR3_EXTI8_Pos) ///< PA[8] pin 169 #define EXTI_CR3_EXTI8_PB (0x01U << EXTI_CR3_EXTI8_Pos) ///< PB[8] pin 170 #define EXTI_CR3_EXTI8_PC (0x02U << EXTI_CR3_EXTI8_Pos) ///< PC[8] pin 171 #define EXTI_CR3_EXTI8_PD (0x03U << EXTI_CR3_EXTI8_Pos) ///< PD[8] pin 172 173 #define EXTI_CR3_EXTI9_Pos (4) 174 #define EXTI_CR3_EXTI9 (0x0FU << EXTI_CR3_EXTI9_Pos) ///< EXTI 9 configuration 175 #define EXTI_CR3_EXTI9_PA (0x00U << EXTI_CR3_EXTI9_Pos) ///< PA[9] pin 176 #define EXTI_CR3_EXTI9_PB (0x01U << EXTI_CR3_EXTI9_Pos) ///< PB[9] pin 177 #define EXTI_CR3_EXTI9_PC (0x02U << EXTI_CR3_EXTI9_Pos) ///< PC[9] pin 178 #define EXTI_CR3_EXTI9_PD (0x03U << EXTI_CR3_EXTI9_Pos) ///< PD[9] pin 179 180 #define EXTI_CR3_EXTI10_Pos (8) 181 #define EXTI_CR3_EXTI10 (0x0FU << EXTI_CR3_EXTI10_Pos) ///< EXTI 10 configuration 182 #define EXTI_CR3_EXTI10_PA (0x00U << EXTI_CR3_EXTI10_Pos) ///< PA[10] pin 183 #define EXTI_CR3_EXTI10_PB (0x01U << EXTI_CR3_EXTI10_Pos) ///< PB[10] pin 184 #define EXTI_CR3_EXTI10_PC (0x02U << EXTI_CR3_EXTI10_Pos) ///< PC[10] pin 185 #define EXTI_CR3_EXTI10_PD (0x03U << EXTI_CR3_EXTI10_Pos) ///< PD[10] pin 186 187 #define EXTI_CR3_EXTI11_Pos (12) 188 #define EXTI_CR3_EXTI11 (0x0FU << EXTI_CR3_EXTI11_Pos) ///< EXTI 11 configuration 189 #define EXTI_CR3_EXTI11_PA (0x00U << EXTI_CR3_EXTI11_Pos) ///< PA[11] pin 190 #define EXTI_CR3_EXTI11_PB (0x01U << EXTI_CR3_EXTI11_Pos) ///< PB[11] pin 191 #define EXTI_CR3_EXTI11_PC (0x02U << EXTI_CR3_EXTI11_Pos) ///< PC[11] pin 192 #define EXTI_CR3_EXTI11_PD (0x03U << EXTI_CR3_EXTI11_Pos) ///< PD[11] pin 193 194 //////////////////////////////////////////////////////////////////////////////// 195 /// @brief EXTI_CR4 Register Bit Definition 196 //////////////////////////////////////////////////////////////////////////////// 197 #define EXTI_CR4_EXTI12_Pos (0) 198 #define EXTI_CR4_EXTI12 (0x0FU << EXTI_CR4_EXTI12_Pos) ///< EXTI 12 configuration 199 #define EXTI_CR4_EXTI12_PA (0x00U << EXTI_CR4_EXTI12_Pos) ///< PA[12] pin 200 #define EXTI_CR4_EXTI12_PB (0x01U << EXTI_CR4_EXTI12_Pos) ///< PB[12] pin 201 #define EXTI_CR4_EXTI12_PC (0x02U << EXTI_CR4_EXTI12_Pos) ///< PC[12] pin 202 #define EXTI_CR4_EXTI12_PD (0x03U << EXTI_CR4_EXTI12_Pos) ///< PD[12] pin 203 204 #define EXTI_CR4_EXTI13_Pos (4) 205 #define EXTI_CR4_EXTI13 (0x0FU << EXTI_CR4_EXTI13_Pos) ///< EXTI 13 configuration 206 #define EXTI_CR4_EXTI13_PA (0x00U << EXTI_CR4_EXTI13_Pos) ///< PA[13] pin 207 #define EXTI_CR4_EXTI13_PB (0x01U << EXTI_CR4_EXTI13_Pos) ///< PB[13] pin 208 #define EXTI_CR4_EXTI13_PC (0x02U << EXTI_CR4_EXTI13_Pos) ///< PC[13] pin 209 #define EXTI_CR4_EXTI13_PD (0x03U << EXTI_CR4_EXTI13_Pos) ///< PD[13] pin 210 211 #define EXTI_CR4_EXTI14_Pos (8) 212 #define EXTI_CR4_EXTI14 (0x0FU << EXTI_CR4_EXTI14_Pos) ///< EXTI 14 configuration 213 #define EXTI_CR4_EXTI14_PA (0x00U << EXTI_CR4_EXTI14_Pos) ///< PA[14] pin 214 #define EXTI_CR4_EXTI14_PB (0x01U << EXTI_CR4_EXTI14_Pos) ///< PB[14] pin 215 #define EXTI_CR4_EXTI14_PC (0x02U << EXTI_CR4_EXTI14_Pos) ///< PC[14] pin 216 #define EXTI_CR4_EXTI14_PD (0x03U << EXTI_CR4_EXTI14_Pos) ///< PD[14] pin 217 218 #define EXTI_CR4_EXTI15_Pos (12) 219 #define EXTI_CR4_EXTI15 (0x0FU << EXTI_CR4_EXTI15_Pos) ///< EXTI 15 configuration 220 #define EXTI_CR4_EXTI15_PA (0x00U << EXTI_CR4_EXTI15_Pos) ///< PA[15] pin 221 #define EXTI_CR4_EXTI15_PB (0x01U << EXTI_CR4_EXTI15_Pos) ///< PB[15] pin 222 #define EXTI_CR4_EXTI15_PC (0x02U << EXTI_CR4_EXTI15_Pos) ///< PC[15] pin 223 #define EXTI_CR4_EXTI15_PD (0x03U << EXTI_CR4_EXTI15_Pos) ///< PD[15] pin 224 //////////////////////////////////////////////////////////////////////////////// 225 /// @brief EXTI_CFGR2 Register Bit Definition 226 //////////////////////////////////////////////////////////////////////////////// 227 #define EXTI_CFGR2_I2C1_Pos (16) 228 #define EXTI_CFGR2_I2C1_OD (0x00U << EXTI_CFGR2_I2C1_Pos) ///< Select open drain mode 229 #define EXTI_CFGR2_I2C1_PP (0x01U << EXTI_CFGR2_I2C1_Pos) ///< Select Push-pull mode 230 #define EXTI_CFGR2_I2C2_Pos (17) 231 #define EXTI_CFGR2_I2C2_OD (0x00U << EXTI_CFGR2_I2C2_Pos) ///< Select open drain mode 232 #define EXTI_CFGR2_I2C2_PP (0x01U << EXTI_CFGR2_I2C2_Pos) ///< Select Push-pull mode 233 #define EXTI_CFGR2_ETPHY_Pos (20) 234 #define EXTI_CFGR2_ETPHY_MII (0x00U << EXTI_CFGR2_ETPHY_Pos) ///< Select MII port 235 #define EXTI_CFGR2_ETPHY_RMII (0x01U << EXTI_CFGR2_ETPHY_Pos) ///< Select RMII port 236 #define EXTI_CFGR2_MAC_SPD_Pos (20) 237 #define EXTI_CFGR2_MAC_SPD_10 (0x00U << EXTI_CFGR2_ETPHY_Pos) ///< Select MAC_SPD 10 Mbps 238 #define EXTI_CFGR2_MAC_SPD_100 (0x01U << EXTI_CFGR2_ETPHY_Pos) ///< Select MAC_SPD 100 Mbps 239 //////////////////////////////////////////////////////////////////////////////// 240 /// @brief EXTI_PDETCSR Register Bit Definition 241 //////////////////////////////////////////////////////////////////////////////// 242 #define EXTI_PDETCSR_PVDE_Pos (0) 243 #define EXTI_PDETCSR_PVDE (0x01U << EXTI_PDETCSR_PVDE_Pos) ///< PVD Enable 244 #define EXTI_PDETCSR_PLS_Pos (1) 245 #define EXTI_PDETCSR_PLS_1_7 (0x00U << EXTI_PDETCSR_PLS_Pos) ///< PVD 1.7mV 246 #define EXTI_PDETCSR_PLS_2_0 (0x01U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.0mV 247 #define EXTI_PDETCSR_PLS_2_3 (0x02U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.3mV 248 #define EXTI_PDETCSR_PLS_2_6 (0x03U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.6mV 249 #define EXTI_PDETCSR_PLS_2_9 (0x04U << EXTI_PDETCSR_PLS_Pos) ///< PVD 2.9mV 250 #define EXTI_PDETCSR_PLS_3_2 (0x05U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.2mV 251 #define EXTI_PDETCSR_PLS_3_5 (0x06U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.5mV 252 #define EXTI_PDETCSR_PLS_3_8 (0x07U << EXTI_PDETCSR_PLS_Pos) ///< PVD 3.8mV 253 #define EXTI_PDETCSR_PLS_4_1 (0x08U << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.1mV 254 #define EXTI_PDETCSR_PLS_4_4 (0x09U << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.4mV 255 #define EXTI_PDETCSR_PLS_4_7 (0x0AU << EXTI_PDETCSR_PLS_Pos) ///< PVD 4.7mV 256 #define EXTI_PDETCSR_PVDO_Pos (5) 257 #define EXTI_PDETCSR_PVDO (0x01U << EXTI_PDETCSR_PVDO_Pos) ///< PVD Output state 258 #define EXTI_PDETCSR_VDTO_Pos (6) 259 #define EXTI_PDETCSR_VDTO (0x01U << EXTI_PDETCSR_VDTO_Pos) ///< VDTO Output state 260 #define EXTI_PDETCSR_VDTE_Pos (8) 261 #define EXTI_PDETCSR_VDTE (0x01U << EXTI_PDETCSR_VDTE_Pos) ///< VDT Enable 262 #define EXTI_PDETCSR_VDTLS_Pos (9) 263 #define EXTI_PDETCSR_VDTLS0 (0x00U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 0.9V 264 #define EXTI_PDETCSR_VDTLS1 (0x01U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.0V 265 #define EXTI_PDETCSR_VDTLS2 (0x02U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.1V 266 #define EXTI_PDETCSR_VDTLS3 (0x03U << EXTI_PDETCSR_VDTLS_Pos) ///< select VDT 1.2V 267 #define EXTI_PDETCSR_VBATDIV3_Pos (11) 268 #define EXTI_PDETCSR_VBATDIV3 (0x01U << EXTI_PDETCSR_VBATDIV3_Pos) ///< PVD Enable 269 //////////////////////////////////////////////////////////////////////////////// 270 /// @brief EXTI_VOSDLY Register Bit Definition 271 //////////////////////////////////////////////////////////////////////////////// 272 #define EXTI_EXTI_VOSDLY (0x3FFU) ///< VOS delay time 273 274 //////////////////////////////////////////////////////////////////////////////// 275 /// @brief EXTI_IMR Register Bit Definition 276 //////////////////////////////////////////////////////////////////////////////// 277 #define EXTI_IMR_0_Pos (0) 278 #define EXTI_IMR_0 (0x01U << EXTI_IMR_0_Pos) ///< Interrupt Mask on line 0 279 #define EXTI_IMR_1_Pos (1) 280 #define EXTI_IMR_1 (0x01U << EXTI_IMR_1_Pos) ///< Interrupt Mask on line 1 281 #define EXTI_IMR_2_Pos (2) 282 #define EXTI_IMR_2 (0x01U << EXTI_IMR_2_Pos) ///< Interrupt Mask on line 2 283 #define EXTI_IMR_3_Pos (3) 284 #define EXTI_IMR_3 (0x01U << EXTI_IMR_3_Pos) ///< Interrupt Mask on line 3 285 #define EXTI_IMR_4_Pos (4) 286 #define EXTI_IMR_4 (0x01U << EXTI_IMR_4_Pos) ///< Interrupt Mask on line 4 287 #define EXTI_IMR_5_Pos (5) 288 #define EXTI_IMR_5 (0x01U << EXTI_IMR_5_Pos) ///< Interrupt Mask on line 5 289 #define EXTI_IMR_6_Pos (6) 290 #define EXTI_IMR_6 (0x01U << EXTI_IMR_6_Pos) ///< Interrupt Mask on line 6 291 #define EXTI_IMR_7_Pos (7) 292 #define EXTI_IMR_7 (0x01U << EXTI_IMR_7_Pos) ///< Interrupt Mask on line 7 293 #define EXTI_IMR_8_Pos (8) 294 #define EXTI_IMR_8 (0x01U << EXTI_IMR_8_Pos) ///< Interrupt Mask on line 8 295 #define EXTI_IMR_9_Pos (9) 296 #define EXTI_IMR_9 (0x01U << EXTI_IMR_9_Pos) ///< Interrupt Mask on line 9 297 #define EXTI_IMR_10_Pos (10) 298 #define EXTI_IMR_10 (0x01U << EXTI_IMR_10_Pos) ///< Interrupt Mask on line 10 299 #define EXTI_IMR_11_Pos (11) 300 #define EXTI_IMR_11 (0x01U << EXTI_IMR_11_Pos) ///< Interrupt Mask on line 11 301 #define EXTI_IMR_12_Pos (12) 302 #define EXTI_IMR_12 (0x01U << EXTI_IMR_12_Pos) ///< Interrupt Mask on line 12 303 #define EXTI_IMR_13_Pos (13) 304 #define EXTI_IMR_13 (0x01U << EXTI_IMR_13_Pos) ///< Interrupt Mask on line 13 305 #define EXTI_IMR_14_Pos (14) 306 #define EXTI_IMR_14 (0x01U << EXTI_IMR_14_Pos) ///< Interrupt Mask on line 14 307 #define EXTI_IMR_15_Pos (15) 308 #define EXTI_IMR_15 (0x01U << EXTI_IMR_15_Pos) ///< Interrupt Mask on line 15 309 #define EXTI_IMR_16_Pos (16) 310 #define EXTI_IMR_16 (0x01U << EXTI_IMR_16_Pos) ///< Interrupt Mask on line 16 311 312 313 314 315 316 317 //////////////////////////////////////////////////////////////////////////////// 318 /// @brief EXTI_EMR Register Bit Definition 319 //////////////////////////////////////////////////////////////////////////////// 320 #define EXTI_EMR_0_Pos (0) 321 #define EXTI_EMR_0 (0x01U << EXTI_EMR_0_Pos) ///< Event Mask on line 0 322 #define EXTI_EMR_1_Pos (1) 323 #define EXTI_EMR_1 (0x01U << EXTI_EMR_1_Pos) ///< Event Mask on line 1 324 #define EXTI_EMR_2_Pos (2) 325 #define EXTI_EMR_2 (0x01U << EXTI_EMR_2_Pos) ///< Event Mask on line 2 326 #define EXTI_EMR_3_Pos (3) 327 #define EXTI_EMR_3 (0x01U << EXTI_EMR_3_Pos) ///< Event Mask on line 3 328 #define EXTI_EMR_4_Pos (4) 329 #define EXTI_EMR_4 (0x01U << EXTI_EMR_4_Pos) ///< Event Mask on line 4 330 #define EXTI_EMR_5_Pos (5) 331 #define EXTI_EMR_5 (0x01U << EXTI_EMR_5_Pos) ///< Event Mask on line 5 332 #define EXTI_EMR_6_Pos (6) 333 #define EXTI_EMR_6 (0x01U << EXTI_EMR_6_Pos) ///< Event Mask on line 6 334 #define EXTI_EMR_7_Pos (7) 335 #define EXTI_EMR_7 (0x01U << EXTI_EMR_7_Pos) ///< Event Mask on line 7 336 #define EXTI_EMR_8_Pos (8) 337 #define EXTI_EMR_8 (0x01U << EXTI_EMR_8_Pos) ///< Event Mask on line 8 338 #define EXTI_EMR_9_Pos (9) 339 #define EXTI_EMR_9 (0x01U << EXTI_EMR_9_Pos) ///< Event Mask on line 9 340 #define EXTI_EMR_10_Pos (10) 341 #define EXTI_EMR_10 (0x01U << EXTI_EMR_10_Pos) ///< Event Mask on line 10 342 #define EXTI_EMR_11_Pos (11) 343 #define EXTI_EMR_11 (0x01U << EXTI_EMR_11_Pos) ///< Event Mask on line 11 344 #define EXTI_EMR_12_Pos (12) 345 #define EXTI_EMR_12 (0x01U << EXTI_EMR_12_Pos) ///< Event Mask on line 12 346 #define EXTI_EMR_13_Pos (13) 347 #define EXTI_EMR_13 (0x01U << EXTI_EMR_13_Pos) ///< Event Mask on line 13 348 #define EXTI_EMR_14_Pos (14) 349 #define EXTI_EMR_14 (0x01U << EXTI_EMR_14_Pos) ///< Event Mask on line 14 350 #define EXTI_EMR_15_Pos (15) 351 #define EXTI_EMR_15 (0x01U << EXTI_EMR_15_Pos) ///< Event Mask on line 15 352 #define EXTI_EMR_16_Pos (16) 353 #define EXTI_EMR_16 (0x01U << EXTI_EMR_16_Pos) ///< Event Mask on line 16 354 355 356 357 358 359 360 //////////////////////////////////////////////////////////////////////////////// 361 /// @brief EXTI_RTSR Register Bit Definition 362 //////////////////////////////////////////////////////////////////////////////// 363 #define EXTI_RTSR_0_Pos (0) 364 #define EXTI_RTSR_0 (0x01U << EXTI_RTSR_0_Pos) ///< Rising trigger event configuration bit of line 0 365 #define EXTI_RTSR_1_Pos (1) 366 #define EXTI_RTSR_1 (0x01U << EXTI_RTSR_1_Pos) ///< Rising trigger event configuration bit of line 1 367 #define EXTI_RTSR_2_Pos (2) 368 #define EXTI_RTSR_2 (0x01U << EXTI_RTSR_2_Pos) ///< Rising trigger event configuration bit of line 2 369 #define EXTI_RTSR_3_Pos (3) 370 #define EXTI_RTSR_3 (0x01U << EXTI_RTSR_3_Pos) ///< Rising trigger event configuration bit of line 3 371 #define EXTI_RTSR_4_Pos (4) 372 #define EXTI_RTSR_4 (0x01U << EXTI_RTSR_4_Pos) ///< Rising trigger event configuration bit of line 4 373 #define EXTI_RTSR_5_Pos (5) 374 #define EXTI_RTSR_5 (0x01U << EXTI_RTSR_5_Pos) ///< Rising trigger event configuration bit of line 5 375 #define EXTI_RTSR_6_Pos (6) 376 #define EXTI_RTSR_6 (0x01U << EXTI_RTSR_6_Pos) ///< Rising trigger event configuration bit of line 6 377 #define EXTI_RTSR_7_Pos (7) 378 #define EXTI_RTSR_7 (0x01U << EXTI_RTSR_7_Pos) ///< Rising trigger event configuration bit of line 7 379 #define EXTI_RTSR_8_Pos (8) 380 #define EXTI_RTSR_8 (0x01U << EXTI_RTSR_8_Pos) ///< Rising trigger event configuration bit of line 8 381 #define EXTI_RTSR_9_Pos (9) 382 #define EXTI_RTSR_9 (0x01U << EXTI_RTSR_9_Pos) ///< Rising trigger event configuration bit of line 9 383 #define EXTI_RTSR_10_Pos (10) 384 #define EXTI_RTSR_10 (0x01U << EXTI_RTSR_10_Pos) ///< Rising trigger event configuration bit of line 10 385 #define EXTI_RTSR_11_Pos (11) 386 #define EXTI_RTSR_11 (0x01U << EXTI_RTSR_11_Pos) ///< Rising trigger event configuration bit of line 11 387 #define EXTI_RTSR_12_Pos (12) 388 #define EXTI_RTSR_12 (0x01U << EXTI_RTSR_12_Pos) ///< Rising trigger event configuration bit of line 12 389 #define EXTI_RTSR_13_Pos (13) 390 #define EXTI_RTSR_13 (0x01U << EXTI_RTSR_13_Pos) ///< Rising trigger event configuration bit of line 13 391 #define EXTI_RTSR_14_Pos (14) 392 #define EXTI_RTSR_14 (0x01U << EXTI_RTSR_14_Pos) ///< Rising trigger event configuration bit of line 14 393 #define EXTI_RTSR_15_Pos (15) 394 #define EXTI_RTSR_15 (0x01U << EXTI_RTSR_15_Pos) ///< Rising trigger event configuration bit of line 15 395 #define EXTI_RTSR_16_Pos (16) 396 #define EXTI_RTSR_16 (0x01U << EXTI_RTSR_16_Pos) ///< Rising trigger event configuration bit of line 16 397 398 399 400 401 402 403 //////////////////////////////////////////////////////////////////////////////// 404 /// @brief EXTI_FTSR Register Bit Definition 405 //////////////////////////////////////////////////////////////////////////////// 406 #define EXTI_FTSR_0_Pos (0) 407 #define EXTI_FTSR_0 (0x01U << EXTI_FTSR_0_Pos) ///< Falling trigger event configuration bit of line 0 408 #define EXTI_FTSR_1_Pos (1) 409 #define EXTI_FTSR_1 (0x01U << EXTI_FTSR_1_Pos) ///< Falling trigger event configuration bit of line 1 410 #define EXTI_FTSR_2_Pos (2) 411 #define EXTI_FTSR_2 (0x01U << EXTI_FTSR_2_Pos) ///< Falling trigger event configuration bit of line 2 412 #define EXTI_FTSR_3_Pos (3) 413 #define EXTI_FTSR_3 (0x01U << EXTI_FTSR_3_Pos) ///< Falling trigger event configuration bit of line 3 414 #define EXTI_FTSR_4_Pos (4) 415 #define EXTI_FTSR_4 (0x01U << EXTI_FTSR_4_Pos) ///< Falling trigger event configuration bit of line 4 416 #define EXTI_FTSR_5_Pos (5) 417 #define EXTI_FTSR_5 (0x01U << EXTI_FTSR_5_Pos) ///< Falling trigger event configuration bit of line 5 418 #define EXTI_FTSR_6_Pos (6) 419 #define EXTI_FTSR_6 (0x01U << EXTI_FTSR_6_Pos) ///< Falling trigger event configuration bit of line 6 420 #define EXTI_FTSR_7_Pos (7) 421 #define EXTI_FTSR_7 (0x01U << EXTI_FTSR_7_Pos) ///< Falling trigger event configuration bit of line 7 422 #define EXTI_FTSR_8_Pos (8) 423 #define EXTI_FTSR_8 (0x01U << EXTI_FTSR_8_Pos) ///< Falling trigger event configuration bit of line 8 424 #define EXTI_FTSR_9_Pos (9) 425 #define EXTI_FTSR_9 (0x01U << EXTI_FTSR_9_Pos) ///< Falling trigger event configuration bit of line 9 426 #define EXTI_FTSR_10_Pos (10) 427 #define EXTI_FTSR_10 (0x01U << EXTI_FTSR_10_Pos) ///< Falling trigger event configuration bit of line 10 428 #define EXTI_FTSR_11_Pos (11) 429 #define EXTI_FTSR_11 (0x01U << EXTI_FTSR_11_Pos) ///< Falling trigger event configuration bit of line 11 430 #define EXTI_FTSR_12_Pos (12) 431 #define EXTI_FTSR_12 (0x01U << EXTI_FTSR_12_Pos) ///< Falling trigger event configuration bit of line 12 432 #define EXTI_FTSR_13_Pos (13) 433 #define EXTI_FTSR_13 (0x01U << EXTI_FTSR_13_Pos) ///< Falling trigger event configuration bit of line 13 434 #define EXTI_FTSR_14_Pos (14) 435 #define EXTI_FTSR_14 (0x01U << EXTI_FTSR_14_Pos) ///< Falling trigger event configuration bit of line 14 436 #define EXTI_FTSR_15_Pos (15) 437 #define EXTI_FTSR_15 (0x01U << EXTI_FTSR_15_Pos) ///< Falling trigger event configuration bit of line 15 438 #define EXTI_FTSR_16_Pos (16) 439 #define EXTI_FTSR_16 (0x01U << EXTI_FTSR_16_Pos) ///< Falling trigger event configuration bit of line 16 440 441 442 443 444 445 446 //////////////////////////////////////////////////////////////////////////////// 447 /// @brief EXTI_SWIER Register Bit Definition 448 //////////////////////////////////////////////////////////////////////////////// 449 #define EXTI_SWIER_0_Pos (0) 450 #define EXTI_SWIER_0 (0x01U << EXTI_SWIER_0_Pos) ///< Software Interrupt on line 0 451 #define EXTI_SWIER_1_Pos (1) 452 #define EXTI_SWIER_1 (0x01U << EXTI_SWIER_1_Pos) ///< Software Interrupt on line 1 453 #define EXTI_SWIER_2_Pos (2) 454 #define EXTI_SWIER_2 (0x01U << EXTI_SWIER_2_Pos) ///< Software Interrupt on line 2 455 #define EXTI_SWIER_3_Pos (3) 456 #define EXTI_SWIER_3 (0x01U << EXTI_SWIER_3_Pos) ///< Software Interrupt on line 3 457 #define EXTI_SWIER_4_Pos (4) 458 #define EXTI_SWIER_4 (0x01U << EXTI_SWIER_4_Pos) ///< Software Interrupt on line 4 459 #define EXTI_SWIER_5_Pos (5) 460 #define EXTI_SWIER_5 (0x01U << EXTI_SWIER_5_Pos) ///< Software Interrupt on line 5 461 #define EXTI_SWIER_6_Pos (6) 462 #define EXTI_SWIER_6 (0x01U << EXTI_SWIER_6_Pos) ///< Software Interrupt on line 6 463 #define EXTI_SWIER_7_Pos (7) 464 #define EXTI_SWIER_7 (0x01U << EXTI_SWIER_7_Pos) ///< Software Interrupt on line 7 465 #define EXTI_SWIER_8_Pos (8) 466 #define EXTI_SWIER_8 (0x01U << EXTI_SWIER_8_Pos) ///< Software Interrupt on line 8 467 #define EXTI_SWIER_9_Pos (9) 468 #define EXTI_SWIER_9 (0x01U << EXTI_SWIER_9_Pos) ///< Software Interrupt on line 9 469 #define EXTI_SWIER_10_Pos (10) 470 #define EXTI_SWIER_10 (0x01U << EXTI_SWIER_10_Pos) ///< Software Interrupt on line 10 471 #define EXTI_SWIER_11_Pos (11) 472 #define EXTI_SWIER_11 (0x01U << EXTI_SWIER_11_Pos) ///< Software Interrupt on line 11 473 #define EXTI_SWIER_12_Pos (12) 474 #define EXTI_SWIER_12 (0x01U << EXTI_SWIER_12_Pos) ///< Software Interrupt on line 12 475 #define EXTI_SWIER_13_Pos (13) 476 #define EXTI_SWIER_13 (0x01U << EXTI_SWIER_13_Pos) ///< Software Interrupt on line 13 477 #define EXTI_SWIER_14_Pos (14) 478 #define EXTI_SWIER_14 (0x01U << EXTI_SWIER_14_Pos) ///< Software Interrupt on line 14 479 #define EXTI_SWIER_15_Pos (15) 480 #define EXTI_SWIER_15 (0x01U << EXTI_SWIER_15_Pos) ///< Software Interrupt on line 15 481 #define EXTI_SWIER_16_Pos (16) 482 #define EXTI_SWIER_16 (0x01U << EXTI_SWIER_16_Pos) ///< Software Interrupt on line 16 483 484 485 486 487 488 489 //////////////////////////////////////////////////////////////////////////////// 490 /// @brief EXTI_PR Register Bit Definition 491 //////////////////////////////////////////////////////////////////////////////// 492 #define EXTI_PR_0_Pos (0) 493 #define EXTI_PR_0 (0x01U << EXTI_PR_0_Pos) ///< Pending bit 0 494 #define EXTI_PR_1_Pos (1) 495 #define EXTI_PR_1 (0x01U << EXTI_PR_1_Pos) ///< Pending bit 1 496 #define EXTI_PR_2_Pos (2) 497 #define EXTI_PR_2 (0x01U << EXTI_PR_2_Pos) ///< Pending bit 2 498 #define EXTI_PR_3_Pos (3) 499 #define EXTI_PR_3 (0x01U << EXTI_PR_3_Pos) ///< Pending bit 3 500 #define EXTI_PR_4_Pos (4) 501 #define EXTI_PR_4 (0x01U << EXTI_PR_4_Pos) ///< Pending bit 4 502 #define EXTI_PR_5_Pos (5) 503 #define EXTI_PR_5 (0x01U << EXTI_PR_5_Pos) ///< Pending bit 5 504 #define EXTI_PR_6_Pos (6) 505 #define EXTI_PR_6 (0x01U << EXTI_PR_6_Pos) ///< Pending bit 6 506 #define EXTI_PR_7_Pos (7) 507 #define EXTI_PR_7 (0x01U << EXTI_PR_7_Pos) ///< Pending bit 7 508 #define EXTI_PR_8_Pos (8) 509 #define EXTI_PR_8 (0x01U << EXTI_PR_8_Pos) ///< Pending bit 8 510 #define EXTI_PR_9_Pos (9) 511 #define EXTI_PR_9 (0x01U << EXTI_PR_9_Pos) ///< Pending bit 9 512 #define EXTI_PR_10_Pos (10) 513 #define EXTI_PR_10 (0x01U << EXTI_PR_10_Pos) ///< Pending bit 10 514 #define EXTI_PR_11_Pos (11) 515 #define EXTI_PR_11 (0x01U << EXTI_PR_11_Pos) ///< Pending bit 11 516 #define EXTI_PR_12_Pos (12) 517 #define EXTI_PR_12 (0x01U << EXTI_PR_12_Pos) ///< Pending bit 12 518 #define EXTI_PR_13_Pos (13) 519 #define EXTI_PR_13 (0x01U << EXTI_PR_13_Pos) ///< Pending bit 13 520 #define EXTI_PR_14_Pos (14) 521 #define EXTI_PR_14 (0x01U << EXTI_PR_14_Pos) ///< Pending bit 14 522 #define EXTI_PR_15_Pos (15) 523 #define EXTI_PR_15 (0x01U << EXTI_PR_15_Pos) ///< Pending bit 15 524 #define EXTI_PR_16_Pos (16) 525 #define EXTI_PR_16 (0x01U << EXTI_PR_16_Pos) ///< Pending bit 16 526 527 528 529 530 531 532 533 534 535 536 /// @} 537 538 /// @} 539 540 /// @} 541 542 //////////////////////////////////////////////////////////////////////////////// 543 #endif 544 //////////////////////////////////////////////////////////////////////////////// 545