1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_fsmc.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_FSMC_H 22 #define __REG_FSMC_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 //////////////////////////////////////////////////////////////////////////////// 40 /// @brief FLASH Base Address Definition 41 //////////////////////////////////////////////////////////////////////////////// 42 43 #define FSMC_BANK1_ADDR (0x60000000UL ) 44 #define FSMC_BANK2_ADDR (0x60000000UL + 0x4000000 ) 45 #define FSMC_BANK3_ADDR (0x60000000UL + 0x8000000 ) 46 #define FSMC_BANK4_ADDR (0x60000000UL + 0xc000000 ) 47 #define FSMC_BASE (0x60000000UL + 0x40000000) ///< Base Address: 0xA0000000 48 49 //////////////////////////////////////////////////////////////////////////////// 50 /// @brief FSMC Registers Structure Definition 51 //////////////////////////////////////////////////////////////////////////////// 52 53 typedef struct { 54 __IO u32 Reservedoffset0x00; ///< Reserved Register offset: 0x00 55 __IO u32 Reservedoffset0x04; ///< Reserved Register offset: 0x04 56 __IO u32 Reservedoffset0x08; ///< Reserved Register offset: 0x08 57 __IO u32 Reservedoffset0x0c; ///< Reserved Register offset: 0x0c 58 __IO u32 Reservedoffset0x10; ///< Reserved Register offset: 0x10 59 __IO u32 Reservedoffset0x14; ///< Reserved Register offset: 0x14 60 __IO u32 Reservedoffset0x18; ///< Reserved Register offset: 0x18 61 __IO u32 Reservedoffset0x1c; ///< Reserved Register offset: 0x1c 62 __IO u32 Reservedoffset0x20; ///< Reserved Register offset: 0x20 63 __IO u32 Reservedoffset0x24; ///< Reserved Register offset: 0x24 64 __IO u32 Reservedoffset0x28; ///< Reserved Register offset: 0x28 65 __IO u32 Reservedoffset0x2c; ///< Reserved Register offset: 0x2c 66 __IO u32 Reservedoffset0x30; ///< Reserved Register offset: 0x30 67 __IO u32 Reservedoffset0x34; ///< Reserved Register offset: 0x34 68 __IO u32 Reservedoffset0x38; ///< Reserved Register offset: 0x38 69 __IO u32 Reservedoffset0x3c; ///< Reserved Register offset: 0x3c 70 __IO u32 Reservedoffset0x40; ///< Reserved Register offset: 0x40 71 __IO u32 Reservedoffset0x44; ///< Reserved Register offset: 0x44 72 __IO u32 Reservedoffset0x48; ///< Reserved Register offset: 0x48 73 __IO u32 Reservedoffset0x4c; ///< Reserved Register offset: 0x4c 74 __IO u32 Reservedoffset0x50; ///< Reserved Register offset: 0x50 75 __IO u32 SMSKR; ///< SMSKR control Register offset: 0x54 76 __IO u32 Reservedoffset0x58; ///< Reserved Register offset: 0x58 77 __IO u32 Reservedoffset0x5c; ///< Reserved Register offset: 0x5c 78 __IO u32 Reservedoffset0x60; ///< Reserved Register offset: 0x60 79 __IO u32 Reservedoffset0x64; ///< Reserved Register offset: 0x64 80 __IO u32 Reservedoffset0x68; ///< Reserved Register offset: 0x68 81 __IO u32 Reservedoffset0x6c; ///< Reserved Register offset: 0x6c 82 __IO u32 Reservedoffset0x70; ///< Reserved Register offset: 0x70 83 __IO u32 Reservedoffset0x74; ///< Reserved Register offset: 0x74 84 __IO u32 Reservedoffset0x78; ///< Reserved Register offset: 0x78 85 __IO u32 Reservedoffset0x7c; ///< Reserved Register offset: 0x7c 86 __IO u32 Reservedoffset0x80; ///< Reserved Register offset: 0x80 87 __IO u32 Reservedoffset0x84; ///< Reserved Register offset: 0x84 88 __IO u32 Reservedoffset0x88; ///< Reserved Register offset: 0x88 89 __IO u32 Reservedoffset0x8c; ///< Reserved Register offset: 0x8c 90 __IO u32 Reservedoffset0x90; ///< Reserved Register offset: 0x90 91 __IO u32 SMTMGR_SET0; ///< SMTMGR_SET Register 0 offset: 0x94 92 __IO u32 SMTMGR_SET1; ///< SMTMGR_SET Register 1 offset: 0x98 93 __IO u32 SMTMGR_SET2; ///< SMTMGR_SET Register 2 offset: 0x9c 94 __IO u32 Reservedoffset0xA0; ///< Reserved Register offset: 0xa0 95 __IO u32 SMCTLR; ///< Reserved Register offset: 0xa4 96 __IO u32 Reservedoffset0xA8; ///< Reserved Register offset: 0xa8 97 __IO u32 Reservedoffset0xAC; ///< Reserved Register offset: 0xac 98 } FSMC_TypeDef; 99 100 101 102 103 //////////////////////////////////////////////////////////////////////////////// 104 /// @brief FSMC type pointer Definition 105 //////////////////////////////////////////////////////////////////////////////// 106 #define FSMC ((FSMC_TypeDef*) FSMC_BASE) 107 108 //////////////////////////////////////////////////////////////////////////////// 109 /// @brief FSMC_SMSKR Register Bit Definition 110 //////////////////////////////////////////////////////////////////////////////// 111 #define FSMC_SMSKR_REG_SELECT_Pos (8) 112 #define FSMC_SMSKR_REG_SELECT0 (0x00U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 0 113 #define FSMC_SMSKR_REG_SELECT1 (0x01U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 1 114 #define FSMC_SMSKR_REG_SELECT2 (0x02U << FSMC_SMSKR_REG_SELECT_Pos) ///< timing parameter configures the register group 2 115 #define FSMC_SMSKR_MEM_TYPE_Pos (5) 116 #define FSMC_SMSKR_MEM_TYPE0 (0x00U << FSMC_SMSKR_MEM_TYPE_Pos) ///< SDRAM 117 #define FSMC_SMSKR_MEM_TYPE1 (0x01U << FSMC_SMSKR_MEM_TYPE_Pos) ///< SRAM 118 #define FSMC_SMSKR_MEM_TYPE2 (0x02U << FSMC_SMSKR_MEM_TYPE_Pos) ///< FLASH 119 #define FSMC_SMSKR_MEM_SIZE_Pos (0) 120 #define FSMC_SMSKR_MEM_SIZE_64K (0x01U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 64KB 121 #define FSMC_SMSKR_MEM_SIZE_128K (0x02U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 128KB 122 #define FSMC_SMSKR_MEM_SIZE_256K (0x03U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 256KB 123 #define FSMC_SMSKR_MEM_SIZE_512K (0x04U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 512KB 124 #define FSMC_SMSKR_MEM_SIZE_1M (0x05U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 1MB 125 #define FSMC_SMSKR_MEM_SIZE_2M (0x06U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 2MB 126 #define FSMC_SMSKR_MEM_SIZE_4M (0x07U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 4MB 127 #define FSMC_SMSKR_MEM_SIZE_8M (0x08U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 8MB 128 #define FSMC_SMSKR_MEM_SIZE_16M (0x09U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 16MB 129 #define FSMC_SMSKR_MEM_SIZE_32M (0x10U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 32MB 130 #define FSMC_SMSKR_MEM_SIZE_64M (0x11U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 64MB 131 #define FSMC_SMSKR_MEM_SIZE_128M (0x12U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 128MB 132 #define FSMC_SMSKR_MEM_SIZE_256M (0x13U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 256MB 133 #define FSMC_SMSKR_MEM_SIZE_512M (0x14U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 512MB 134 #define FSMC_SMSKR_MEM_SIZE_1G (0x15U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 1GB 135 #define FSMC_SMSKR_MEM_SIZE_2G (0x16U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 2GB 136 #define FSMC_SMSKR_MEM_SIZE_4G (0x17U << FSMC_SMSKR_MEM_SIZE_Pos) ///< external DEVICE size 4GB 137 138 //////////////////////////////////////////////////////////////////////////////// 139 /// @brief FSMC_SMTMGR_SET0/1/2 Register Bit Definition 140 //////////////////////////////////////////////////////////////////////////////// 141 #define FSMC_SMTMGR_SET_SM_READ_PIPE_Pos (28) 142 #define FSMC_SMTMGR_SET_SM_READ_PIPE (0x03U << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) ///< The period of the latched read data 143 #define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos (27) 144 #define FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE (0x01U << FSMC_SMTMGR_SET_LOW_FREG_SYNC_DEVICE_Pos) ///< Access low frequency synchronization devices 145 #define FSMC_SMTMGR_SET_READ_MODE_Pos (26) 146 #define FSMC_SMTMGR_SET_READ_MODE (0x01U << FSMC_SMTMGR_SET_READ_MODE_Pos) ///< The Hready_RESP signal is from an external DEVICE 147 #define FSMC_SMTMGR_SET_T_WP_Pos (10) 148 #define FSMC_SMTMGR_SET_T_WP (0x3FU << FSMC_SMTMGR_SET_T_WP_Pos) ///< Write pulse width 64 clock cycles 149 #define FSMC_SMTMGR_SET_T_WR_Pos (8) 150 #define FSMC_SMTMGR_SET_T_WR (0x03U << FSMC_SMTMGR_SET_T_WR_Pos) ///< Address/data retention time for write operations is 3 clock cycles 151 #define FSMC_SMTMGR_SET_T_AS_Pos (6) 152 #define FSMC_SMTMGR_SET_T_AS (0x03U << FSMC_SMTMGR_SET_T_AS_Pos) ///< The address establishment time of write operation is 3 clock cycles 153 #define FSMC_SMTMGR_SET_T_RC_Pos (0) 154 #define FSMC_SMTMGR_SET_T_RC (0x3FU << FSMC_SMTMGR_SET_T_RC_Pos) ///< Read operation cycle 64 clock cycles 155 156 //////////////////////////////////////////////////////////////////////////////// 157 /// @brief FSMC_SMCTLR Register Bit Definition 158 //////////////////////////////////////////////////////////////////////////////// 159 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos (13) 160 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET2 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) 161 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 16 bits 162 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 32 bits 163 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 64 bits 164 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 128 bits 165 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET2_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos) ///< Memory data bus bit width 8 bits 166 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos (10) 167 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET1 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) 168 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 16 bits 169 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 32 bits 170 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 64 bits 171 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 128 bits 172 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET1_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos) ///< Memory data bus bit width 8 bits 173 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos (7) 174 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET0 (0x07U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) 175 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_16 (0x00U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 16 bits 176 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_32 (0x01U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 32 bits 177 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_64 (0x02U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 64 bits 178 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_128 (0x03U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 128 bits 179 #define FSMC_SMCTLR_SM_DATA_WIDTH_SET0_8 (0x04U << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos) ///< Memory data bus bit width 8 bits 180 181 182 183 184 185 186 /// @} 187 188 /// @} 189 190 /// @} 191 192 //////////////////////////////////////////////////////////////////////////////// 193 #endif //__REG_FSMC_H 194 //////////////////////////////////////////////////////////////////////////////// 195