1 /** @file reg_het.h 2 * @brief HET Register Layer Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Definitions 8 * - Types 9 * - Interface Prototypes 10 * . 11 * which are relevant for the HET driver. 12 */ 13 14 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 15 16 #ifndef __REG_HET_H__ 17 #define __REG_HET_H__ 18 19 #include "sys_common.h" 20 #include "gio.h" 21 22 23 24 /* USER CODE BEGIN (0) */ 25 /* USER CODE END */ 26 27 /* Het Register Frame Definition */ 28 /** @struct hetBase 29 * @brief HET Base Register Definition 30 * 31 * This structure is used to access the HET module registers. 32 */ 33 /** @typedef hetBASE_t 34 * @brief HET Register Frame Type Definition 35 * 36 * This type is used to access the HET Registers. 37 */ 38 39 typedef volatile struct hetBase 40 { 41 uint32 GCR; /**< 0x0000: Global control register */ 42 uint32 PFR; /**< 0x0004: Prescale factor register */ 43 uint32 ADDR; /**< 0x0008: Current address register */ 44 uint32 OFF1; /**< 0x000C: Interrupt offset register 1 */ 45 uint32 OFF2; /**< 0x0010: Interrupt offset register 2 */ 46 uint32 INTENAS; /**< 0x0014: Interrupt enable set register */ 47 uint32 INTENAC; /**< 0x0018: Interrupt enable clear register */ 48 uint32 EXC1; /**< 0x001C: Exception control register 1 */ 49 uint32 EXC2; /**< 0x0020: Exception control register 2 */ 50 uint32 PRY; /**< 0x0024: Interrupt priority register */ 51 uint32 FLG; /**< 0x0028: Interrupt flag register */ 52 uint32 AND; /**< 0x002C: AND share control register */ 53 uint32 rsvd1; /**< 0x0030: Reserved */ 54 uint32 HRSH; /**< 0x0034: High resolution share register */ 55 uint32 XOR; /**< 0x0038: XOR share register */ 56 uint32 REQENS; /**< 0x003C: Request enable set register */ 57 uint32 REQENC; /**< 0x0040: Request enable clear register */ 58 uint32 REQDS; /**< 0x0044: Request destination select register */ 59 uint32 rsvd2; /**< 0x0048: Reserved */ 60 uint32 DIR; /**< 0x004C: Direction register */ 61 uint32 DIN; /**< 0x0050: Data input register */ 62 uint32 DOUT; /**< 0x0054: Data output register */ 63 uint32 DSET; /**< 0x0058: Data output set register */ 64 uint32 DCLR; /**< 0x005C: Data output clear register */ 65 uint32 PDR; /**< 0x0060: Open drain register */ 66 uint32 PULDIS; /**< 0x0064: Pull disable register */ 67 uint32 PSL; /**< 0x0068: Pull select register */ 68 uint32 rsvd3; /**< 0x006C: Reserved */ 69 uint32 rsvd4; /**< 0x0070: Reserved */ 70 uint32 PCR; /**< 0x0074: Parity control register */ 71 uint32 PAR; /**< 0x0078: Parity address register */ 72 uint32 PPR; /**< 0x007C: Parity pin select register */ 73 uint32 SFPRLD; /**< 0x0080: Suppression filter preload register */ 74 uint32 SFENA; /**< 0x0084: Suppression filter enable register */ 75 uint32 rsvd5; /**< 0x0088: Reserved */ 76 uint32 LBPSEL; /**< 0x008C: Loop back pair select register */ 77 uint32 LBPDIR; /**< 0x0090: Loop back pair direction register */ 78 uint32 PINDIS; /**< 0x0094: Pin disable register */ 79 uint32 rsvd6; /**< 0x0098: Reserved */ 80 uint32 HWAPINSEL;/**< 0x009C: HWAG Pin select register */ 81 uint32 HWAGCR0; /**< 0x00A0: HWAG Global control register 0 */ 82 uint32 HWAGCR1; /**< 0x00A4: HWAG Global control register 1 */ 83 uint32 HWAGCR2; /**< 0x00A8: HWAG Global control register 2 */ 84 uint32 HWAENASET;/**< 0x00AC: HWAG Interrupt enable set register */ 85 uint32 HWAENACLR;/**< 0x00B0: HWAG Interrupt enable clear register*/ 86 uint32 HWALVLSET;/**< 0x00B4: HWAG Interrupt level set register */ 87 uint32 HWALVLCLR;/**< 0x00B8: HWAG Interrupt level clear register */ 88 uint32 HWAFLG; /**< 0x00BC: HWAG Interrupt flag register */ 89 uint32 HWAOFF1; /**< 0x00C0: HWAG Interrupt offset 1 register */ 90 uint32 HWAOFF2; /**< 0x00C4: HWAG Interrupt offset 2 register */ 91 uint32 HWAACNT; /**< 0x00C8: HWAG Angle value register */ 92 uint32 HWAPCNT1; /**< 0x00CC: HWAG Period value register 1 */ 93 uint32 HWAPCNT; /**< 0x00D0: HWAG Period value register */ 94 uint32 HWASTWD; /**< 0x00D4: HWAG Step width register */ 95 uint32 HWATHNB; /**< 0x00D8: HWAG Teeth number register */ 96 uint32 HWATHVL; /**< 0x00DC: HWAG Teeth Value register */ 97 uint32 HWAFIL; /**< 0x00E0: HWAG Filter register */ 98 uint32 rsvd7; /**< 0x00E4: Reserved */ 99 uint32 HWAFIL2; /**< 0x00E8: HWAG Second filter register */ 100 uint32 rsvd8; /**< 0x00EC: Reserved */ 101 uint32 HWAANGI; /**< 0x00F0: HWAG Angle increment register */ 102 } hetBASE_t; 103 104 105 /** @def hetREG1 106 * @brief HET Register Frame Pointer 107 * 108 * This pointer is used by the HET driver to access the het module registers. 109 */ 110 #define hetREG1 ((hetBASE_t *)0xFFF7B800U) 111 112 113 /** @def hetPORT1 114 * @brief HET GIO Port Register Pointer 115 * 116 * Pointer used by the GIO driver to access I/O PORT of HET1 117 * (use the GIO drivers to access the port pins). 118 */ 119 #define hetPORT1 ((gioPORT_t *)0xFFF7B84CU) 120 121 122 /** @def hetREG2 123 * @brief HET2 Register Frame Pointer 124 * 125 * This pointer is used by the HET driver to access the het module registers. 126 */ 127 #define hetREG2 ((hetBASE_t *)0xFFF7B900U) 128 129 130 /** @def hetPORT2 131 * @brief HET2 GIO Port Register Pointer 132 * 133 * Pointer used by the GIO driver to access I/O PORT of HET2 134 * (use the GIO drivers to access the port pins). 135 */ 136 #define hetPORT2 ((gioPORT_t *)0xFFF7B94CU) 137 138 #define hetRAM1 ((hetRAMBASE_t *)0xFF460000U) 139 140 #define hetRAM2 ((hetRAMBASE_t *)0xFF440000U) 141 142 #define NHET1RAMPARLOC (*(volatile uint32 *)0xFF462000U) 143 #define NHET1RAMLOC (*(volatile uint32 *)0xFF460000U) 144 145 #define NHET2RAMPARLOC (*(volatile uint32 *)0xFF442000U) 146 #define NHET2RAMLOC (*(volatile uint32 *)0xFF440000U) 147 148 /* USER CODE BEGIN (1) */ 149 /* USER CODE END */ 150 151 152 #endif 153