1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_iwdg.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_IWDG_H 22 #define __REG_IWDG_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 //////////////////////////////////////////////////////////////////////////////// 40 /// @brief IWDG Base Address Definition 41 //////////////////////////////////////////////////////////////////////////////// 42 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) ///< Base Address: 0x40003000 43 44 //////////////////////////////////////////////////////////////////////////////// 45 /// @brief IWDG Register Structure Definition 46 //////////////////////////////////////////////////////////////////////////////// 47 typedef struct { 48 __IO u32 KR; ///< Key Register offset: 0x00 49 __IO u32 PR; ///< Prescaler Register offset: 0x04 50 __IO u32 RLR; ///< Reload Register offset: 0x08 51 __IO u32 SR; ///< Status Register offset: 0x0C 52 __IO u32 CR; ///< Control Register offset: 0x10 53 __IO u32 IGEN; ///< Interrupt Generator Register offset: 0x14 54 __IO u32 CNT; ///< Interrupt Generator count Register offset: 0x18 55 __IO u32 PS; ///< Prescaler count Register offset: 0x1C 56 } IWDG_TypeDef; 57 58 //////////////////////////////////////////////////////////////////////////////// 59 /// @brief IWDG type pointer Definition 60 //////////////////////////////////////////////////////////////////////////////// 61 #define IWDG ((IWDG_TypeDef*) IWDG_BASE) 62 63 //////////////////////////////////////////////////////////////////////////////// 64 /// @brief IWDG_KR Register Bit Definition 65 //////////////////////////////////////////////////////////////////////////////// 66 #define IWDG_KEYR_KEY_Pos (0) 67 #define IWDG_KEYR_KEY (0xFFFFU << IWDG_KEYR_KEY_Pos) ///< Key Value 68 69 //////////////////////////////////////////////////////////////////////////////// 70 /// @brief IWDG_PR Register Bit Definition 71 //////////////////////////////////////////////////////////////////////////////// 72 #define IWDG_PR_PRE_Pos (0) 73 #define IWDG_PR_PRE (0x07U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 4 74 #define IWDG_PR_PRE_DIV4 (0x00U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 4 75 #define IWDG_PR_PRE_DIV8 (0x01U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 8 76 #define IWDG_PR_PRE_DIV16 (0x02U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 16 77 #define IWDG_PR_PRE_DIV32 (0x03U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 32 78 #define IWDG_PR_PRE_DIV64 (0x04U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 64 79 #define IWDG_PR_PRE_DIV128 (0x05U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 128 80 #define IWDG_PR_PRE_DIV256 (0x06U << IWDG_PR_PRE_Pos) ///< Prescaler divided by 256 81 82 //////////////////////////////////////////////////////////////////////////////// 83 /// @brief IWDG_RLR Register Bit Definition 84 //////////////////////////////////////////////////////////////////////////////// 85 #define IWDG_RLR_RL_Pos (0) 86 #define IWDG_RLR_RL (0x0FFFU << IWDG_RLR_RL_Pos) ///< Watchdog counter reload value 87 88 //////////////////////////////////////////////////////////////////////////////// 89 /// @brief IWDG_SR Register Bit Definition 90 //////////////////////////////////////////////////////////////////////////////// 91 #define IWDG_SR_PVU_Pos (0) 92 #define IWDG_SR_PVU (0x01U << IWDG_SR_PVU_Pos) ///< Watchdog prescaler value update 93 #define IWDG_SR_RVU_Pos (1) 94 #define IWDG_SR_RVU (0x01U << IWDG_SR_RVU_Pos) ///< Watchdog counter reload value update 95 96 #define IWDG_SR_IVU_Pos (2) 97 #define IWDG_SR_IVU (0x01U << IWDG_SR_IVU_Pos) 98 99 #define IWDG_SR_UPDATE_Pos (3) 100 #define IWDG_SR_UPDATE (0x01U << IWDG_SR_UPDATE_Pos) 101 102 //////////////////////////////////////////////////////////////////////////////// 103 /// @brief IWDG_CR Register Bit Definition 104 //////////////////////////////////////////////////////////////////////////////// 105 #define IWDG_CR_IRQSEL_Pos (0) 106 #define IWDG_CR_IRQSEL (0x01U << IWDG_CR_IRQSEL_Pos) ///< IWDG overflow operation selection 107 #define IWDG_CR_IRQCLR_Pos (1) 108 #define IWDG_CR_IRQCLR (0x01U << IWDG_CR_IRQCLR_Pos) ///< IWDG interrupt clear 109 110 //////////////////////////////////////////////////////////////////////////////// 111 /// @brief IWDG_IGRN Register Bit Definition 112 //////////////////////////////////////////////////////////////////////////////// 113 #define IWDG_IGEN_IGEN_Pos (0) 114 #define IWDG_IGEN_IGEN (0xFFFU << IWDG_CR_IRQSEL_Pos) ///< IWDG Interrupt Generate value 115 116 117 /// @} 118 119 /// @} 120 121 /// @} 122 123 //////////////////////////////////////////////////////////////////////////////// 124 #endif 125 //////////////////////////////////////////////////////////////////////////////// 126