1 /** @file reg_pbist.h 2 * @brief PBIST Register Layer Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Definitions 8 * - Types 9 * . 10 * which are relevant for the System driver. 11 */ 12 13 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 14 15 #ifndef __REG_PBIST_H__ 16 #define __REG_PBIST_H__ 17 18 #include "sys_common.h" 19 20 /* USER CODE BEGIN (0) */ 21 /* USER CODE END */ 22 23 /* PBIST Register Frame Definition */ 24 /** @struct pbistBase 25 * @brief PBIST Base Register Definition 26 * 27 * This structure is used to access the PBIST module registers. 28 */ 29 /** @typedef pbistBASE_t 30 * @brief PBIST Register Frame Type Definition 31 * 32 * This type is used to access the PBIST Registers. 33 */ 34 typedef volatile struct pbistBase 35 { 36 uint32 RAMT; /* 0x0160: RAM Configuration Register */ 37 uint32 DLR; /* 0x0164: Datalogger Register */ 38 uint32 rsvd1[6U]; /* 0x0168 */ 39 uint32 PACT; /* 0x0180: PBIST Activate Register */ 40 uint32 PBISTID; /* 0x0184: PBIST ID Register */ 41 uint32 OVER; /* 0x0188: Override Register */ 42 uint32 rsvd2; /* 0x018C */ 43 uint32 FSRF0; /* 0x0190: Fail Status Fail Register 0 */ 44 uint32 FSRF1; /* 0x0194: Fail Status Fail Register 1 */ 45 uint32 FSRC0; /* 0x0198: Fail Status Count Register 0 */ 46 uint32 FSRC1; /* 0x019C: Fail Status Count Register 1 */ 47 uint32 FSRA0; /* 0x01A0: Fail Status Address 0 Register */ 48 uint32 FSRA1; /* 0x01A4: Fail Status Address 1 Register */ 49 uint32 FSRDL0; /* 0x01A8: Fail Status Data Register 0 */ 50 uint32 rsvd3; /* 0x01AC */ 51 uint32 FSRDL1; /* 0x01B0: Fail Status Data Register 1 */ 52 uint32 rsvd4[3U]; /* 0x01B4 */ 53 uint32 ROM; /* 0x01C0: ROM Mask Register */ 54 uint32 ALGO; /* 0x01C4: Algorithm Mask Register */ 55 uint32 RINFOL; /* 0x01C8: RAM Info Mask Lower Register */ 56 uint32 RINFOU; /* 0x01CC: RAM Info Mask Upper Register */ 57 } pbistBASE_t; 58 59 #define pbistREG ((pbistBASE_t *)0xFFFFE560U) 60 61 /* USER CODE BEGIN (1) */ 62 /* USER CODE END */ 63 64 65 #endif 66