1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_pwr.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_PWR_H 22 #define __REG_PWR_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 44 //////////////////////////////////////////////////////////////////////////////// 45 /// @brief PWR Base Address Definition 46 //////////////////////////////////////////////////////////////////////////////// 47 #define PWR_BASE (APB1PERIPH_BASE + 0x7000) ///< Base Address: 0x40007000 48 49 50 51 52 53 //////////////////////////////////////////////////////////////////////////////// 54 /// @brief PWR Register Structure Definition 55 //////////////////////////////////////////////////////////////////////////////// 56 typedef struct { 57 union { 58 __IO u32 CR; ///< Control register, offset: 0x00 59 __IO u32 CR1; 60 }; 61 union { 62 __IO u32 CSR; ///< Control Status register offset: 0x04 63 __IO u32 CSR1; 64 }; 65 __IO u32 CR2; ///< Control register 2 offset: 0x08 66 __IO u32 CR3; ///< Control register 3 offset: 0x0C 67 __IO u32 CR4; ///< Control register 4 offset: 0x10 68 __IO u32 CR5; ///< Control register 5 offset: 0x14 69 __IO u32 CR6; ///< Control register 6 offset: 0x18 70 __IO u32 SR; ///< Status register offset: 0x1C 71 __IO u32 SCR; ///< clear status register offset: 0x20 72 __IO u32 CFGR; ///< Configuration register offset: 0x24 73 } PWR_TypeDef; 74 75 //////////////////////////////////////////////////////////////////////////////// 76 /// @brief PWR type pointer Definition 77 //////////////////////////////////////////////////////////////////////////////// 78 #define PWR ((PWR_TypeDef*) PWR_BASE) 79 80 81 82 //////////////////////////////////////////////////////////////////////////////// 83 /// @brief PWR_CR register Bit definition 84 //////////////////////////////////////////////////////////////////////////////// 85 #define PWR_CR_LDPS_Pos (0) 86 #define PWR_CR_LDPS (0x01U << PWR_CR_LDPS_Pos) ///< Domain Write Protction 87 88 #define PWR_CR_PDDS_Pos (1) 89 #define PWR_CR_PDDS (0x01U << PWR_CR_PDDS_Pos) ///< Power Down Deepsleep 90 #define PWR_CR_CSBF_Pos (3) 91 #define PWR_CR_CSBF (0x01U << PWR_CR_CSBF_Pos) ///< Clear Standby Flag 92 #define PWR_CR_LPR_Pos (13) 93 #define PWR_CR_LPR (0x01U << PWR_CR_LPR_Pos) ///< Low power run 94 #define PWR_CR_VOS_Pos (14) 95 #define PWR_CR_VOS0 (0x00U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.80V 96 #define PWR_CR_VOS1 (0x01U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.70V 97 #define PWR_CR_VOS2 (0x02U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.60V 98 #define PWR_CR_VOS3 (0x03U << PWR_CR_VOS_Pos) ///< Modulator Voltage Output Select 1.55V 99 100 //////////////////////////////////////////////////////////////////////////////// 101 /// @brief PWR_CSR register Bit definition 102 //////////////////////////////////////////////////////////////////////////////// 103 #define PWR_CSR_SBF_Pos (1) 104 #define PWR_CSR_SBF (0x01U << PWR_CSR_SBF_Pos) ///< Standby Flag 105 #define PWR_CSR_VOSRDY_Pos (14) 106 #define PWR_CSR_VOSRDY (0x01U << PWR_CR_VOSRDY_Pos) ///< Voltage Modulator Output Selection Ready 107 //////////////////////////////////////////////////////////////////////////////// 108 /// @brief PWR_CR2 register Bit definition 109 //////////////////////////////////////////////////////////////////////////////// 110 #define PWR_CR2_EWUP1_Pos (0) 111 #define PWR_CR2_EWUP1 (0x01U << PWR_CR2_EWUP1_Pos) ///< Enable WKUP1 wake-up pin 112 #define PWR_CR2_EWUP2_Pos (1) 113 #define PWR_CR2_EWUP2 (0x01U << PWR_CR2_EWUP2_Pos) ///< Enable WKUP2 wake-up pin 114 #define PWR_CR2_EWUP3_Pos (2) 115 #define PWR_CR2_EWUP3 (0x01U << PWR_CR2_EWUP3_Pos) ///< Enable WKUP3 wake-up pin 116 #define PWR_CR2_EWUP4_Pos (3) 117 #define PWR_CR2_EWUP4 (0x01U << PWR_CR2_EWUP4_Pos) ///< Enable WKUP4 wake-up pin 118 #define PWR_CR2_EWUP5_Pos (4) 119 #define PWR_CR2_EWUP5 (0x01U << PWR_CR2_EWUP5_Pos) ///< Enable WKUP5 wake-up pin 120 #define PWR_CR2_EWUP6_Pos (5) 121 #define PWR_CR2_EWUP6 (0x01U << PWR_CR2_EWUP6_Pos) ///< Enable WKUP6 wake-up pin 122 #define PWR_CR2_ENWU_Pos (15) 123 #define PWR_CR2_ENWU (0x01U << PWR_CR2_ENWU_Pos) ///< Enable wakeup module 124 //////////////////////////////////////////////////////////////////////////////// 125 /// @brief PWR_CR3 register Bit definition 126 //////////////////////////////////////////////////////////////////////////////// 127 #define PWR_CR3_WP1_Pos (0) 128 #define PWR_CR3_WP1 (0x01U << PWR_CR3_WP1_Pos) ///< WKUP1 used for event polarity detection 129 #define PWR_CR3_WP2_Pos (1) 130 #define PWR_CR3_WP2 (0x01U << PWR_CR3_WP2_Pos) ///< WKUP2 used for event polarity detection 131 #define PWR_CR3_WP3_Pos (2) 132 #define PWR_CR3_WP3 (0x01U << PWR_CR3_WP3_Pos) ///< WKUP3 used for event polarity detection 133 #define PWR_CR3_WP4_Pos (3) 134 #define PWR_CR3_WP4 (0x01U << PWR_CR3_WP4_Pos) ///< WKUP4 used for event polarity detection 135 #define PWR_CR3_WP5_Pos (4) 136 #define PWR_CR3_WP5 (0x01U << PWR_CR3_WP5_Pos) ///< WKUP5 used for event polarity detection 137 #define PWR_CR3_WP6_Pos (5) 138 #define PWR_CR3_WP6 (0x01U << PWR_CR3_WP6_Pos) ///< WKUP6 used for event polarity detection 139 //////////////////////////////////////////////////////////////////////////////// 140 /// @brief PWR_CR4 register Bit definition 141 //////////////////////////////////////////////////////////////////////////////// 142 #define PWR_CR4_FILTSEL0_Pos (0) 143 #define PWR_CR4_FILTSEL0 (0x01U << PWR_CR4_FILTSEL0_Pos) ///< selection wake-up source 144 #define PWR_CR4_FILTE0_Pos (2) 145 #define PWR_CR4_FILTE0 (0x01U << PWR_CR4_FILTE0_Pos) ///< enable Filter 0 146 #define PWR_CR4_FILTF0_Pos (4) 147 #define PWR_CR4_FILTF0 (0x01U << PWR_CR4_FILTF0_Pos) ///< Whether the wake source passes through filter 0 148 #define PWR_CR4_FILTCNT0_Pos (8) 149 #define PWR_CR4_FILTCNT0 (0xFFU << PWR_CR4_FILTCNT0_Pos) ///< Filter 0 counter 150 //////////////////////////////////////////////////////////////////////////////// 151 /// @brief PWR_CR5 register Bit definition 152 //////////////////////////////////////////////////////////////////////////////// 153 #define PWR_CR5_FILTSEL1_Pos (0) 154 #define PWR_CR5_FILTSEL1 (0x01U << PWR_CR5_FILTSEL1_Pos) ///< selection wake-up source 155 #define PWR_CR5_FILTE1_Pos (2) 156 #define PWR_CR5_FILTE1 (0x01U << PWR_CR5_FILTE1_Pos) ///< enable Filter 1 157 #define PWR_CR5_FILTF1_Pos (4) 158 #define PWR_CR5_FILTF1 (0x01U << PWR_CR5_FILTF1_Pos) ///< Whether the wake source passes through filter 1 159 #define PWR_CR5_FILTCNT1_Pos (8) 160 #define PWR_CR5_FILTCNT1 (0xFFU << PWR_CR5_FILTCNT1_Pos) ///< Filter 1 counter 161 //////////////////////////////////////////////////////////////////////////////// 162 /// @brief PWR_CR6 register Bit definition 163 //////////////////////////////////////////////////////////////////////////////// 164 #define PWR_CR6_STDBY_FS_W_Pos (0) 165 #define PWR_CR6_STDBY_FS_W1 (0x00U << PWR_CR6_STDBY_FS_W_Pos) ///< 1 LSI cycle wake 166 #define PWR_CR6_STDBY_FS_W2 (0x01U << PWR_CR6_STDBY_FS_W_Pos) ///< 2 LSI cycle wake 167 #define PWR_CR6_STDBY_FS_W3 (0x02U << PWR_CR6_STDBY_FS_W_Pos) ///< 3 LSI cycle wake 168 #define PWR_CR6_STDBY_FS_W4 (0x03U << PWR_CR6_STDBY_FS_W_Pos) ///< 4 LSI cycle wake 169 #define PWR_CR6_STDBY_FS_W5 (0x04U << PWR_CR6_STDBY_FS_W_Pos) ///< 5 LSI cycle wake 170 #define PWR_CR6_STDBY_FS_W6 (0x05U << PWR_CR6_STDBY_FS_W_Pos) ///< 6 LSI cycle wake 171 #define PWR_CR6_STDBY_FS_W7 (0x06U << PWR_CR6_STDBY_FS_W_Pos) ///< 7 LSI cycle wake 172 #define PWR_CR6_STDBY_FS_W8 (0x07U << PWR_CR6_STDBY_FS_W_Pos) ///< 8 LSI cycle wake 173 //////////////////////////////////////////////////////////////////////////////// 174 /// @brief PWR_SR register Bit definition 175 //////////////////////////////////////////////////////////////////////////////// 176 #define PWR_SR_WUF1_Pos (0) 177 #define PWR_SR_WUF1 (0x01U << PWR_SR_WUF1_Pos) ///< wake-up flag 1 178 #define PWR_SR_WUF2_Pos (1) 179 #define PWR_SR_WUF2 (0x01U << PWR_SR_WUF2_Pos) ///< wake-up flag 2 180 #define PWR_SR_WUF3_Pos (2) 181 #define PWR_SR_WUF3 (0x01U << PWR_SR_WUF3_Pos) ///< wake-up flag 3 182 #define PWR_SR_WUF4_Pos (3) 183 #define PWR_SR_WUF4 (0x01U << PWR_SR_WUF4_Pos) ///< wake-up flag 4 184 #define PWR_SR_WUF5_Pos (4) 185 #define PWR_SR_WUF5 (0x01U << PWR_SR_WUF5_Pos) ///< wake-up flag 5 186 #define PWR_SR_WUF6_Pos (5) 187 #define PWR_SR_WUF6 (0x01U << PWR_SR_WUF6_Pos) ///< wake-up flag 6 188 //////////////////////////////////////////////////////////////////////////////// 189 /// @brief PWR_SCR register Bit definition 190 //////////////////////////////////////////////////////////////////////////////// 191 #define PWR_SCR_CWUF1_Pos (0) 192 #define PWR_SCR_CWUF1 (0x01U << PWR_SCR_CWUF1_Pos) ///< clear wake-up flag 1 193 #define PWR_SCR_CWUF2_Pos (1) 194 #define PWR_SCR_CWUF2 (0x01U << PWR_SCR_CWUF2_Pos) ///< clear wake-up flag 2 195 #define PWR_SCR_CWUF3_Pos (2) 196 #define PWR_SCR_CWUF3 (0x01U << PWR_SCR_CWUF3_Pos) ///< clear wake-up flag 3 197 #define PWR_SCR_CWUF4_Pos (3) 198 #define PWR_SCR_CWUF4 (0x01U << PWR_SCR_CWUF4_Pos) ///< clear wake-up flag 4 199 #define PWR_SCR_CWUF5_Pos (4) 200 #define PWR_SCR_CWUF5 (0x01U << PWR_SCR_CWUF5_Pos) ///< clear wake-up flag 5 201 #define PWR_SCR_CWUF6_Pos (5) 202 #define PWR_SCR_CWUF6 (0x01U << PWR_SCR_CWUF6_Pos) ///< clear wake-up flag 6 203 //////////////////////////////////////////////////////////////////////////////// 204 /// @brief PWR_CFGR register Bit definition 205 //////////////////////////////////////////////////////////////////////////////// 206 #define PWR_CFGR_LSICALSEL_Pos (0) 207 #define PWR_CFGR_LSICALSEL (0x1FU << PWR_CFGR_LSICALSEL_Pos) ///< Enable internal clock calibration 208 #define PWR_CFGR_LSICAL_Pos (5) 209 #define PWR_CFGR_LSICAL (0x1FU << PWR_CFGR_LSICAL_Pos) ///< Internal high-speed clock calibration 210 211 /// @} 212 213 /// @} 214 215 /// @} 216 217 //////////////////////////////////////////////////////////////////////////////// 218 #endif 219 //////////////////////////////////////////////////////////////////////////////// 220