1 /** @file reg_stc.h 2 * @brief STC Register Layer Header File 3 * @date 29.May.2013 4 * @version 03.05.02 5 * 6 * This file contains: 7 * - Definitions 8 * - Types 9 * . 10 * which are relevant for the System driver. 11 */ 12 13 /* (c) Texas Instruments 2009-2013, All rights reserved. */ 14 15 #ifndef __REG_STC_H__ 16 #define __REG_STC_H__ 17 18 #include "sys_common.h" 19 20 /* USER CODE BEGIN (0) */ 21 /* USER CODE END */ 22 23 /* Stc Register Frame Definition */ 24 /** @struct stcBase 25 * @brief STC Base Register Definition 26 * 27 * This structure is used to access the STC module registers. 28 */ 29 /** @typedef stcBASE_t 30 * @brief STC Register Frame Type Definition 31 * 32 * This type is used to access the STC Registers. 33 */ 34 typedef volatile struct stcBase 35 { 36 uint32 STCGCR0; /**< 0x0000: STC Control Register 0 */ 37 uint32 STCGCR1; /**< 0x0004: STC Control Register 1 */ 38 uint32 STCTPR; /**< 0x0008: STC Self-Test Run Timeout Counter Preload Register */ 39 uint32 STCCADDR; /**< 0x000C: STC Self-Test Current ROM Address Register */ 40 uint32 STCCICR; /**< 0x0010: STC Self-Test Current Interval Count Register */ 41 uint32 STCGSTAT; /**< 0x0014: STC Self-Test Global Status Register */ 42 uint32 STCFSTAT; /**< 0x0018: STC Self-Test Fail Status Register */ 43 uint32 CPU1_CURMISR3; /**< 0x001C: STC CPU1 Current MISR Register */ 44 uint32 CPU1_CURMISR2; /**< 0x0020: STC CPU1 Current MISR Register */ 45 uint32 CPU1_CURMISR1; /**< 0x0024: STC CPU1 Current MISR Register */ 46 uint32 CPU1_CURMISR0; /**< 0x0028: STC CPU1 Current MISR Register */ 47 uint32 CPU2_CURMISR3; /**< 0x002C: STC CPU1 Current MISR Register */ 48 uint32 CPU2_CURMISR2; /**< 0x0030: STC CPU1 Current MISR Register */ 49 uint32 CPU2_CURMISR1; /**< 0x0034: STC CPU1 Current MISR Register */ 50 uint32 CPU2_CURMISR0; /**< 0x0038: STC CPU1 Current MISR Register */ 51 uint32 STCSCSCR; /**< 0x003C: STC Signature Compare Self-Check Register */ 52 } stcBASE_t; 53 54 #define stcREG ((stcBASE_t *)0xFFFFE600U) 55 56 /* USER CODE BEGIN (1) */ 57 /* USER CODE END */ 58 59 60 #endif 61