1 //***************************************************************************** 2 // 3 // am_reg_itm.h 4 //! @file 5 //! 6 //! @brief Register macros for the ITM module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_ITM_H 45 #define AM_REG_ITM_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_ITM_NUM_MODULES 1 53 #define AM_REG_ITMn(n) \ 54 (REG_ITM_BASEADDR + 0x00000000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_ITM_STIM0_O 0xE0000000 62 #define AM_REG_ITM_STIM1_O 0xE0000004 63 #define AM_REG_ITM_STIM2_O 0xE0000008 64 #define AM_REG_ITM_STIM3_O 0xE000000C 65 #define AM_REG_ITM_STIM4_O 0xE0000010 66 #define AM_REG_ITM_STIM5_O 0xE0000014 67 #define AM_REG_ITM_STIM6_O 0xE0000018 68 #define AM_REG_ITM_STIM7_O 0xE000001C 69 #define AM_REG_ITM_STIM8_O 0xE0000020 70 #define AM_REG_ITM_STIM9_O 0xE0000024 71 #define AM_REG_ITM_STIM10_O 0xE0000028 72 #define AM_REG_ITM_STIM11_O 0xE000002C 73 #define AM_REG_ITM_STIM12_O 0xE0000030 74 #define AM_REG_ITM_STIM13_O 0xE0000034 75 #define AM_REG_ITM_STIM14_O 0xE0000038 76 #define AM_REG_ITM_STIM15_O 0xE000003C 77 #define AM_REG_ITM_STIM16_O 0xE0000040 78 #define AM_REG_ITM_STIM17_O 0xE0000044 79 #define AM_REG_ITM_STIM18_O 0xE0000048 80 #define AM_REG_ITM_STIM19_O 0xE000004C 81 #define AM_REG_ITM_STIM20_O 0xE0000050 82 #define AM_REG_ITM_STIM21_O 0xE0000054 83 #define AM_REG_ITM_STIM22_O 0xE0000058 84 #define AM_REG_ITM_STIM23_O 0xE000005C 85 #define AM_REG_ITM_STIM24_O 0xE0000060 86 #define AM_REG_ITM_STIM25_O 0xE0000064 87 #define AM_REG_ITM_STIM26_O 0xE0000068 88 #define AM_REG_ITM_STIM27_O 0xE000006C 89 #define AM_REG_ITM_STIM28_O 0xE0000070 90 #define AM_REG_ITM_STIM29_O 0xE0000074 91 #define AM_REG_ITM_STIM30_O 0xE0000078 92 #define AM_REG_ITM_STIM31_O 0xE000007C 93 #define AM_REG_ITM_TER_O 0xE0000E00 94 #define AM_REG_ITM_TPR_O 0xE0000E40 95 #define AM_REG_ITM_TCR_O 0xE0000E80 96 #define AM_REG_ITM_LOCKSREG_O 0xE0000FB4 97 #define AM_REG_ITM_PID4_O 0xE0000FD0 98 #define AM_REG_ITM_PID5_O 0xE0000FD4 99 #define AM_REG_ITM_PID6_O 0xE0000FD8 100 #define AM_REG_ITM_PID7_O 0xE0000FDC 101 #define AM_REG_ITM_PID0_O 0xE0000FE0 102 #define AM_REG_ITM_PID1_O 0xE0000FE4 103 #define AM_REG_ITM_PID2_O 0xE0000FE8 104 #define AM_REG_ITM_PID3_O 0xE0000FEC 105 #define AM_REG_ITM_CID0_O 0xE0000FF0 106 #define AM_REG_ITM_CID1_O 0xE0000FF4 107 #define AM_REG_ITM_CID2_O 0xE0000FF8 108 #define AM_REG_ITM_CID3_O 0xE0000FFC 109 #define AM_REG_ITM_LOCKAREG_O 0xE0000FB0 110 111 //***************************************************************************** 112 // 113 // Key values. 114 // 115 //***************************************************************************** 116 #define AM_REG_ITM_LOCKAREG_KEYVAL 0xC5ACCE55 117 118 //***************************************************************************** 119 // 120 // ITM_STIM0 - Stimulus Port Register 0 121 // 122 //***************************************************************************** 123 // Stimulus Port Register 0. 124 #define AM_REG_ITM_STIM0_STIM0_S 0 125 #define AM_REG_ITM_STIM0_STIM0_M 0xFFFFFFFF 126 #define AM_REG_ITM_STIM0_STIM0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 127 128 //***************************************************************************** 129 // 130 // ITM_STIM1 - Stimulus Port Register 1 131 // 132 //***************************************************************************** 133 // Stimulus Port Register 1. 134 #define AM_REG_ITM_STIM1_STIM1_S 0 135 #define AM_REG_ITM_STIM1_STIM1_M 0xFFFFFFFF 136 #define AM_REG_ITM_STIM1_STIM1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 137 138 //***************************************************************************** 139 // 140 // ITM_STIM2 - Stimulus Port Register 2 141 // 142 //***************************************************************************** 143 // Stimulus Port Register 2. 144 #define AM_REG_ITM_STIM2_STIM2_S 0 145 #define AM_REG_ITM_STIM2_STIM2_M 0xFFFFFFFF 146 #define AM_REG_ITM_STIM2_STIM2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 147 148 //***************************************************************************** 149 // 150 // ITM_STIM3 - Stimulus Port Register 3 151 // 152 //***************************************************************************** 153 // Stimulus Port Register 3. 154 #define AM_REG_ITM_STIM3_STIM3_S 0 155 #define AM_REG_ITM_STIM3_STIM3_M 0xFFFFFFFF 156 #define AM_REG_ITM_STIM3_STIM3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 157 158 //***************************************************************************** 159 // 160 // ITM_STIM4 - Stimulus Port Register 4 161 // 162 //***************************************************************************** 163 // Stimulus Port Register 4. 164 #define AM_REG_ITM_STIM4_STIM4_S 0 165 #define AM_REG_ITM_STIM4_STIM4_M 0xFFFFFFFF 166 #define AM_REG_ITM_STIM4_STIM4(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 167 168 //***************************************************************************** 169 // 170 // ITM_STIM5 - Stimulus Port Register 5 171 // 172 //***************************************************************************** 173 // Stimulus Port Register 5. 174 #define AM_REG_ITM_STIM5_STIM5_S 0 175 #define AM_REG_ITM_STIM5_STIM5_M 0xFFFFFFFF 176 #define AM_REG_ITM_STIM5_STIM5(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 177 178 //***************************************************************************** 179 // 180 // ITM_STIM6 - Stimulus Port Register 6 181 // 182 //***************************************************************************** 183 // Stimulus Port Register 6. 184 #define AM_REG_ITM_STIM6_STIM6_S 0 185 #define AM_REG_ITM_STIM6_STIM6_M 0xFFFFFFFF 186 #define AM_REG_ITM_STIM6_STIM6(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 187 188 //***************************************************************************** 189 // 190 // ITM_STIM7 - Stimulus Port Register 7 191 // 192 //***************************************************************************** 193 // Stimulus Port Register 7. 194 #define AM_REG_ITM_STIM7_STIM7_S 0 195 #define AM_REG_ITM_STIM7_STIM7_M 0xFFFFFFFF 196 #define AM_REG_ITM_STIM7_STIM7(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 197 198 //***************************************************************************** 199 // 200 // ITM_STIM8 - Stimulus Port Register 8 201 // 202 //***************************************************************************** 203 // Stimulus Port Register 8. 204 #define AM_REG_ITM_STIM8_STIM8_S 0 205 #define AM_REG_ITM_STIM8_STIM8_M 0xFFFFFFFF 206 #define AM_REG_ITM_STIM8_STIM8(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 207 208 //***************************************************************************** 209 // 210 // ITM_STIM9 - Stimulus Port Register 9 211 // 212 //***************************************************************************** 213 // Stimulus Port Register 9. 214 #define AM_REG_ITM_STIM9_STIM9_S 0 215 #define AM_REG_ITM_STIM9_STIM9_M 0xFFFFFFFF 216 #define AM_REG_ITM_STIM9_STIM9(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 217 218 //***************************************************************************** 219 // 220 // ITM_STIM10 - Stimulus Port Register 10 221 // 222 //***************************************************************************** 223 // Stimulus Port Register 10. 224 #define AM_REG_ITM_STIM10_STIM10_S 0 225 #define AM_REG_ITM_STIM10_STIM10_M 0xFFFFFFFF 226 #define AM_REG_ITM_STIM10_STIM10(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 227 228 //***************************************************************************** 229 // 230 // ITM_STIM11 - Stimulus Port Register 11 231 // 232 //***************************************************************************** 233 // Stimulus Port Register 11. 234 #define AM_REG_ITM_STIM11_STIM11_S 0 235 #define AM_REG_ITM_STIM11_STIM11_M 0xFFFFFFFF 236 #define AM_REG_ITM_STIM11_STIM11(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 237 238 //***************************************************************************** 239 // 240 // ITM_STIM12 - Stimulus Port Register 12 241 // 242 //***************************************************************************** 243 // Stimulus Port Register 12. 244 #define AM_REG_ITM_STIM12_STIM12_S 0 245 #define AM_REG_ITM_STIM12_STIM12_M 0xFFFFFFFF 246 #define AM_REG_ITM_STIM12_STIM12(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 247 248 //***************************************************************************** 249 // 250 // ITM_STIM13 - Stimulus Port Register 13 251 // 252 //***************************************************************************** 253 // Stimulus Port Register 13. 254 #define AM_REG_ITM_STIM13_STIM13_S 0 255 #define AM_REG_ITM_STIM13_STIM13_M 0xFFFFFFFF 256 #define AM_REG_ITM_STIM13_STIM13(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 257 258 //***************************************************************************** 259 // 260 // ITM_STIM14 - Stimulus Port Register 14 261 // 262 //***************************************************************************** 263 // Stimulus Port Register 14. 264 #define AM_REG_ITM_STIM14_STIM14_S 0 265 #define AM_REG_ITM_STIM14_STIM14_M 0xFFFFFFFF 266 #define AM_REG_ITM_STIM14_STIM14(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 267 268 //***************************************************************************** 269 // 270 // ITM_STIM15 - Stimulus Port Register 15 271 // 272 //***************************************************************************** 273 // Stimulus Port Register 15. 274 #define AM_REG_ITM_STIM15_STIM15_S 0 275 #define AM_REG_ITM_STIM15_STIM15_M 0xFFFFFFFF 276 #define AM_REG_ITM_STIM15_STIM15(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 277 278 //***************************************************************************** 279 // 280 // ITM_STIM16 - Stimulus Port Register 16 281 // 282 //***************************************************************************** 283 // Stimulus Port Register 16. 284 #define AM_REG_ITM_STIM16_STIM16_S 0 285 #define AM_REG_ITM_STIM16_STIM16_M 0xFFFFFFFF 286 #define AM_REG_ITM_STIM16_STIM16(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 287 288 //***************************************************************************** 289 // 290 // ITM_STIM17 - Stimulus Port Register 17 291 // 292 //***************************************************************************** 293 // Stimulus Port Register 17. 294 #define AM_REG_ITM_STIM17_STIM17_S 0 295 #define AM_REG_ITM_STIM17_STIM17_M 0xFFFFFFFF 296 #define AM_REG_ITM_STIM17_STIM17(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 297 298 //***************************************************************************** 299 // 300 // ITM_STIM18 - Stimulus Port Register 18 301 // 302 //***************************************************************************** 303 // Stimulus Port Register 18. 304 #define AM_REG_ITM_STIM18_STIM18_S 0 305 #define AM_REG_ITM_STIM18_STIM18_M 0xFFFFFFFF 306 #define AM_REG_ITM_STIM18_STIM18(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 307 308 //***************************************************************************** 309 // 310 // ITM_STIM19 - Stimulus Port Register 19 311 // 312 //***************************************************************************** 313 // Stimulus Port Register 19. 314 #define AM_REG_ITM_STIM19_STIM19_S 0 315 #define AM_REG_ITM_STIM19_STIM19_M 0xFFFFFFFF 316 #define AM_REG_ITM_STIM19_STIM19(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 317 318 //***************************************************************************** 319 // 320 // ITM_STIM20 - Stimulus Port Register 20 321 // 322 //***************************************************************************** 323 // Stimulus Port Register 20. 324 #define AM_REG_ITM_STIM20_STIM20_S 0 325 #define AM_REG_ITM_STIM20_STIM20_M 0xFFFFFFFF 326 #define AM_REG_ITM_STIM20_STIM20(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 327 328 //***************************************************************************** 329 // 330 // ITM_STIM21 - Stimulus Port Register 21 331 // 332 //***************************************************************************** 333 // Stimulus Port Register 21. 334 #define AM_REG_ITM_STIM21_STIM21_S 0 335 #define AM_REG_ITM_STIM21_STIM21_M 0xFFFFFFFF 336 #define AM_REG_ITM_STIM21_STIM21(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 337 338 //***************************************************************************** 339 // 340 // ITM_STIM22 - Stimulus Port Register 22 341 // 342 //***************************************************************************** 343 // Stimulus Port Register 22. 344 #define AM_REG_ITM_STIM22_STIM22_S 0 345 #define AM_REG_ITM_STIM22_STIM22_M 0xFFFFFFFF 346 #define AM_REG_ITM_STIM22_STIM22(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 347 348 //***************************************************************************** 349 // 350 // ITM_STIM23 - Stimulus Port Register 23 351 // 352 //***************************************************************************** 353 // Stimulus Port Register 23. 354 #define AM_REG_ITM_STIM23_STIM23_S 0 355 #define AM_REG_ITM_STIM23_STIM23_M 0xFFFFFFFF 356 #define AM_REG_ITM_STIM23_STIM23(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 357 358 //***************************************************************************** 359 // 360 // ITM_STIM24 - Stimulus Port Register 24 361 // 362 //***************************************************************************** 363 // Stimulus Port Register 24. 364 #define AM_REG_ITM_STIM24_STIM24_S 0 365 #define AM_REG_ITM_STIM24_STIM24_M 0xFFFFFFFF 366 #define AM_REG_ITM_STIM24_STIM24(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 367 368 //***************************************************************************** 369 // 370 // ITM_STIM25 - Stimulus Port Register 25 371 // 372 //***************************************************************************** 373 // Stimulus Port Register 25. 374 #define AM_REG_ITM_STIM25_STIM25_S 0 375 #define AM_REG_ITM_STIM25_STIM25_M 0xFFFFFFFF 376 #define AM_REG_ITM_STIM25_STIM25(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 377 378 //***************************************************************************** 379 // 380 // ITM_STIM26 - Stimulus Port Register 26 381 // 382 //***************************************************************************** 383 // Stimulus Port Register 26. 384 #define AM_REG_ITM_STIM26_STIM26_S 0 385 #define AM_REG_ITM_STIM26_STIM26_M 0xFFFFFFFF 386 #define AM_REG_ITM_STIM26_STIM26(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 387 388 //***************************************************************************** 389 // 390 // ITM_STIM27 - Stimulus Port Register 27 391 // 392 //***************************************************************************** 393 // Stimulus Port Register 27. 394 #define AM_REG_ITM_STIM27_STIM27_S 0 395 #define AM_REG_ITM_STIM27_STIM27_M 0xFFFFFFFF 396 #define AM_REG_ITM_STIM27_STIM27(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 397 398 //***************************************************************************** 399 // 400 // ITM_STIM28 - Stimulus Port Register 28 401 // 402 //***************************************************************************** 403 // Stimulus Port Register 28. 404 #define AM_REG_ITM_STIM28_STIM28_S 0 405 #define AM_REG_ITM_STIM28_STIM28_M 0xFFFFFFFF 406 #define AM_REG_ITM_STIM28_STIM28(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 407 408 //***************************************************************************** 409 // 410 // ITM_STIM29 - Stimulus Port Register 29 411 // 412 //***************************************************************************** 413 // Stimulus Port Register 29. 414 #define AM_REG_ITM_STIM29_STIM29_S 0 415 #define AM_REG_ITM_STIM29_STIM29_M 0xFFFFFFFF 416 #define AM_REG_ITM_STIM29_STIM29(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 417 418 //***************************************************************************** 419 // 420 // ITM_STIM30 - Stimulus Port Register 30 421 // 422 //***************************************************************************** 423 // Stimulus Port Register 30. 424 #define AM_REG_ITM_STIM30_STIM30_S 0 425 #define AM_REG_ITM_STIM30_STIM30_M 0xFFFFFFFF 426 #define AM_REG_ITM_STIM30_STIM30(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 427 428 //***************************************************************************** 429 // 430 // ITM_STIM31 - Stimulus Port Register 31 431 // 432 //***************************************************************************** 433 // Stimulus Port Register 31. 434 #define AM_REG_ITM_STIM31_STIM31_S 0 435 #define AM_REG_ITM_STIM31_STIM31_M 0xFFFFFFFF 436 #define AM_REG_ITM_STIM31_STIM31(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 437 438 //***************************************************************************** 439 // 440 // ITM_TER - Trace Enable Register. 441 // 442 //***************************************************************************** 443 // Bit mask to enable tracing on ITM stimulus ports. One bit per stimulus port.. 444 #define AM_REG_ITM_TER_STIMENA_S 0 445 #define AM_REG_ITM_TER_STIMENA_M 0xFFFFFFFF 446 #define AM_REG_ITM_TER_STIMENA(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 447 448 //***************************************************************************** 449 // 450 // ITM_TPR - Trace Privilege Register. 451 // 452 //***************************************************************************** 453 // Bit mask to enable tracing on ITM stimulus ports. bit[0] = stimulus 454 // ports[7:0], bit[1] = stimulus ports[15:8], bit[2] = stimulus ports[23:16], 455 // bit[3] = stimulus ports[31:24]. 456 #define AM_REG_ITM_TPR_PRIVMASK_S 0 457 #define AM_REG_ITM_TPR_PRIVMASK_M 0x0000000F 458 #define AM_REG_ITM_TPR_PRIVMASK(n) (((uint32_t)(n) << 0) & 0x0000000F) 459 460 //***************************************************************************** 461 // 462 // ITM_TCR - Trace Control Register. 463 // 464 //***************************************************************************** 465 // Set when ITM events present and being drained. 466 #define AM_REG_ITM_TCR_BUSY_S 23 467 #define AM_REG_ITM_TCR_BUSY_M 0x00800000 468 #define AM_REG_ITM_TCR_BUSY(n) (((uint32_t)(n) << 23) & 0x00800000) 469 470 // ATB ID for CoreSight system. 471 #define AM_REG_ITM_TCR_ATB_ID_S 16 472 #define AM_REG_ITM_TCR_ATB_ID_M 0x007F0000 473 #define AM_REG_ITM_TCR_ATB_ID(n) (((uint32_t)(n) << 16) & 0x007F0000) 474 475 // Global Timestamp Frequency. 476 #define AM_REG_ITM_TCR_TS_FREQ_S 10 477 #define AM_REG_ITM_TCR_TS_FREQ_M 0x00000C00 478 #define AM_REG_ITM_TCR_TS_FREQ(n) (((uint32_t)(n) << 10) & 0x00000C00) 479 480 // Timestamp prescaler: 0b00 = no prescaling 0b01 = divide by 4 0b10 = divide by 481 // 16 0b11 = divide by 64. 482 #define AM_REG_ITM_TCR_TS_PRESCALE_S 8 483 #define AM_REG_ITM_TCR_TS_PRESCALE_M 0x00000300 484 #define AM_REG_ITM_TCR_TS_PRESCALE(n) (((uint32_t)(n) << 8) & 0x00000300) 485 486 // Enable SWV behavior – count on TPIUEMIT and TPIUBAUD. 487 #define AM_REG_ITM_TCR_SWV_ENABLE_S 4 488 #define AM_REG_ITM_TCR_SWV_ENABLE_M 0x00000010 489 #define AM_REG_ITM_TCR_SWV_ENABLE(n) (((uint32_t)(n) << 4) & 0x00000010) 490 491 // Enables the DWT stimulus. 492 #define AM_REG_ITM_TCR_DWT_ENABLE_S 3 493 #define AM_REG_ITM_TCR_DWT_ENABLE_M 0x00000008 494 #define AM_REG_ITM_TCR_DWT_ENABLE(n) (((uint32_t)(n) << 3) & 0x00000008) 495 496 // Enables sync packets for TPIU. 497 #define AM_REG_ITM_TCR_SYNC_ENABLE_S 2 498 #define AM_REG_ITM_TCR_SYNC_ENABLE_M 0x00000004 499 #define AM_REG_ITM_TCR_SYNC_ENABLE(n) (((uint32_t)(n) << 2) & 0x00000004) 500 501 // Enables differential timestamps. Differential timestamps are emitted when a 502 // packet is written to the FIFO with a non-zero timestamp counter, and when the 503 // timestamp counter overflows. Timestamps are emitted during idle times after a 504 // fixed number of cycles. This provides a time reference for packets and inter- 505 // packet gaps. 506 #define AM_REG_ITM_TCR_TS_ENABLE_S 1 507 #define AM_REG_ITM_TCR_TS_ENABLE_M 0x00000002 508 #define AM_REG_ITM_TCR_TS_ENABLE(n) (((uint32_t)(n) << 1) & 0x00000002) 509 510 // Enable ITM. This is the master enable, and must be set before ITM Stimulus 511 // and Trace Enable registers can be written. 512 #define AM_REG_ITM_TCR_ITM_ENABLE_S 0 513 #define AM_REG_ITM_TCR_ITM_ENABLE_M 0x00000001 514 #define AM_REG_ITM_TCR_ITM_ENABLE(n) (((uint32_t)(n) << 0) & 0x00000001) 515 516 //***************************************************************************** 517 // 518 // ITM_LOCKSREG - Lock Status Register 519 // 520 //***************************************************************************** 521 // You cannot implement 8-bit lock accesses. 522 #define AM_REG_ITM_LOCKSREG_BYTEACC_S 2 523 #define AM_REG_ITM_LOCKSREG_BYTEACC_M 0x00000004 524 #define AM_REG_ITM_LOCKSREG_BYTEACC(n) (((uint32_t)(n) << 2) & 0x00000004) 525 526 // Write access to component is blocked. All writes are ignored, reads are 527 // permitted. 528 #define AM_REG_ITM_LOCKSREG_ACCESS_S 1 529 #define AM_REG_ITM_LOCKSREG_ACCESS_M 0x00000002 530 #define AM_REG_ITM_LOCKSREG_ACCESS(n) (((uint32_t)(n) << 1) & 0x00000002) 531 532 // Indicates that a lock mechanism exists for this component. 533 #define AM_REG_ITM_LOCKSREG_PRESENT_S 0 534 #define AM_REG_ITM_LOCKSREG_PRESENT_M 0x00000001 535 #define AM_REG_ITM_LOCKSREG_PRESENT(n) (((uint32_t)(n) << 0) & 0x00000001) 536 537 //***************************************************************************** 538 // 539 // ITM_PID4 - Peripheral Identification Register 4 540 // 541 //***************************************************************************** 542 // Peripheral Identification 4. 543 #define AM_REG_ITM_PID4_PID4_S 0 544 #define AM_REG_ITM_PID4_PID4_M 0xFFFFFFFF 545 #define AM_REG_ITM_PID4_PID4(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 546 547 //***************************************************************************** 548 // 549 // ITM_PID5 - Peripheral Identification Register 5 550 // 551 //***************************************************************************** 552 // Peripheral Identification 5. 553 #define AM_REG_ITM_PID5_PID5_S 0 554 #define AM_REG_ITM_PID5_PID5_M 0xFFFFFFFF 555 #define AM_REG_ITM_PID5_PID5(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 556 557 //***************************************************************************** 558 // 559 // ITM_PID6 - Peripheral Identification Register 6 560 // 561 //***************************************************************************** 562 // Peripheral Identification 6. 563 #define AM_REG_ITM_PID6_PID6_S 0 564 #define AM_REG_ITM_PID6_PID6_M 0xFFFFFFFF 565 #define AM_REG_ITM_PID6_PID6(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 566 567 //***************************************************************************** 568 // 569 // ITM_PID7 - Peripheral Identification Register 7 570 // 571 //***************************************************************************** 572 // Peripheral Identification 7. 573 #define AM_REG_ITM_PID7_PID7_S 0 574 #define AM_REG_ITM_PID7_PID7_M 0xFFFFFFFF 575 #define AM_REG_ITM_PID7_PID7(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 576 577 //***************************************************************************** 578 // 579 // ITM_PID0 - Peripheral Identification Register 0 580 // 581 //***************************************************************************** 582 // Peripheral Identification 0. 583 #define AM_REG_ITM_PID0_PID0_S 0 584 #define AM_REG_ITM_PID0_PID0_M 0xFFFFFFFF 585 #define AM_REG_ITM_PID0_PID0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 586 587 //***************************************************************************** 588 // 589 // ITM_PID1 - Peripheral Identification Register 1 590 // 591 //***************************************************************************** 592 // Peripheral Identification 1. 593 #define AM_REG_ITM_PID1_PID1_S 0 594 #define AM_REG_ITM_PID1_PID1_M 0xFFFFFFFF 595 #define AM_REG_ITM_PID1_PID1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 596 597 //***************************************************************************** 598 // 599 // ITM_PID2 - Peripheral Identification Register 2 600 // 601 //***************************************************************************** 602 // Peripheral Identification 2. 603 #define AM_REG_ITM_PID2_PID2_S 0 604 #define AM_REG_ITM_PID2_PID2_M 0xFFFFFFFF 605 #define AM_REG_ITM_PID2_PID2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 606 607 //***************************************************************************** 608 // 609 // ITM_PID3 - Peripheral Identification Register 3 610 // 611 //***************************************************************************** 612 // Peripheral Identification 3. 613 #define AM_REG_ITM_PID3_PID3_S 0 614 #define AM_REG_ITM_PID3_PID3_M 0xFFFFFFFF 615 #define AM_REG_ITM_PID3_PID3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 616 617 //***************************************************************************** 618 // 619 // ITM_CID0 - Component Identification Register 1 620 // 621 //***************************************************************************** 622 // Component Identification 1. 623 #define AM_REG_ITM_CID0_CID0_S 0 624 #define AM_REG_ITM_CID0_CID0_M 0xFFFFFFFF 625 #define AM_REG_ITM_CID0_CID0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 626 627 //***************************************************************************** 628 // 629 // ITM_CID1 - Component Identification Register 1 630 // 631 //***************************************************************************** 632 // Component Identification 1. 633 #define AM_REG_ITM_CID1_CID1_S 0 634 #define AM_REG_ITM_CID1_CID1_M 0xFFFFFFFF 635 #define AM_REG_ITM_CID1_CID1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 636 637 //***************************************************************************** 638 // 639 // ITM_CID2 - Component Identification Register 2 640 // 641 //***************************************************************************** 642 // Component Identification 2. 643 #define AM_REG_ITM_CID2_CID2_S 0 644 #define AM_REG_ITM_CID2_CID2_M 0xFFFFFFFF 645 #define AM_REG_ITM_CID2_CID2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 646 647 //***************************************************************************** 648 // 649 // ITM_CID3 - Component Identification Register 3 650 // 651 //***************************************************************************** 652 // Component Identification 3. 653 #define AM_REG_ITM_CID3_CID3_S 0 654 #define AM_REG_ITM_CID3_CID3_M 0xFFFFFFFF 655 #define AM_REG_ITM_CID3_CID3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF) 656 657 #endif // AM_REG_ITM_H 658