1 //***************************************************************************** 2 // 3 // am_reg_pwrctrl.h 4 //! @file 5 //! 6 //! @brief Register macros for the PWRCTRL module 7 // 8 //***************************************************************************** 9 10 //***************************************************************************** 11 // 12 // Copyright (c) 2017, Ambiq Micro 13 // All rights reserved. 14 // 15 // Redistribution and use in source and binary forms, with or without 16 // modification, are permitted provided that the following conditions are met: 17 // 18 // 1. Redistributions of source code must retain the above copyright notice, 19 // this list of conditions and the following disclaimer. 20 // 21 // 2. Redistributions in binary form must reproduce the above copyright 22 // notice, this list of conditions and the following disclaimer in the 23 // documentation and/or other materials provided with the distribution. 24 // 25 // 3. Neither the name of the copyright holder nor the names of its 26 // contributors may be used to endorse or promote products derived from this 27 // software without specific prior written permission. 28 // 29 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 30 // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 31 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 32 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 33 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 // POSSIBILITY OF SUCH DAMAGE. 40 // 41 // This is part of revision 1.2.11 of the AmbiqSuite Development Package. 42 // 43 //***************************************************************************** 44 #ifndef AM_REG_PWRCTRL_H 45 #define AM_REG_PWRCTRL_H 46 47 //***************************************************************************** 48 // 49 // Instance finder. (1 instance(s) available) 50 // 51 //***************************************************************************** 52 #define AM_REG_PWRCTRL_NUM_MODULES 1 53 #define AM_REG_PWRCTRLn(n) \ 54 (REG_PWRCTRL_BASEADDR + 0x00000000 * n) 55 56 //***************************************************************************** 57 // 58 // Register offsets. 59 // 60 //***************************************************************************** 61 #define AM_REG_PWRCTRL_SUPPLYSRC_O 0x00000000 62 #define AM_REG_PWRCTRL_POWERSTATUS_O 0x00000004 63 #define AM_REG_PWRCTRL_DEVICEEN_O 0x00000008 64 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_O 0x0000000C 65 #define AM_REG_PWRCTRL_MEMEN_O 0x00000010 66 #define AM_REG_PWRCTRL_PWRONSTATUS_O 0x00000014 67 #define AM_REG_PWRCTRL_SRAMCTRL_O 0x00000018 68 #define AM_REG_PWRCTRL_ADCSTATUS_O 0x0000001C 69 #define AM_REG_PWRCTRL_MISCOPT_O 0x00000020 70 71 //***************************************************************************** 72 // 73 // PWRCTRL_SUPPLYSRC - Memory and Core Voltage Supply Source Select Register 74 // 75 //***************************************************************************** 76 // Switches the CORE DOMAIN from BUCK mode (if enabled) to LDO when CPU is in 77 // DEEP SLEEP. If all the devices are off then this does not matter and LDO (low 78 // power mode) is used 79 #define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_S 2 80 #define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_M 0x00000004 81 #define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP(n) (((uint32_t)(n) << 2) & 0x00000004) 82 #define AM_REG_PWRCTRL_SUPPLYSRC_SWITCH_LDO_IN_SLEEP_EN 0x00000004 83 84 // Enables and Selects the Core Buck as the supply for the low-voltage power 85 // domain. 86 #define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_S 1 87 #define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_M 0x00000002 88 #define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN(n) (((uint32_t)(n) << 1) & 0x00000002) 89 #define AM_REG_PWRCTRL_SUPPLYSRC_COREBUCKEN_EN 0x00000002 90 91 // Enables and select the Memory Buck as the supply for the Flash and SRAM power 92 // domain. 93 #define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_S 0 94 #define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_M 0x00000001 95 #define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN(n) (((uint32_t)(n) << 0) & 0x00000001) 96 #define AM_REG_PWRCTRL_SUPPLYSRC_MEMBUCKEN_EN 0x00000001 97 98 //***************************************************************************** 99 // 100 // PWRCTRL_POWERSTATUS - Power Status Register for MCU supplies and peripherals 101 // 102 //***************************************************************************** 103 // Indicates whether the Core low-voltage domain is supplied from the LDO or the 104 // Buck. 105 #define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_S 1 106 #define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_M 0x00000002 107 #define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON(n) (((uint32_t)(n) << 1) & 0x00000002) 108 #define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_LDO 0x00000000 109 #define AM_REG_PWRCTRL_POWERSTATUS_COREBUCKON_BUCK 0x00000002 110 111 // Indicate whether the Memory power domain is supplied from the LDO or the 112 // Buck. 113 #define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_S 0 114 #define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_M 0x00000001 115 #define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON(n) (((uint32_t)(n) << 0) & 0x00000001) 116 #define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_LDO 0x00000000 117 #define AM_REG_PWRCTRL_POWERSTATUS_MEMBUCKON_BUCK 0x00000001 118 119 //***************************************************************************** 120 // 121 // PWRCTRL_DEVICEEN - DEVICE ENABLES for SHELBY 122 // 123 //***************************************************************************** 124 // Enable PDM Digital Block 125 #define AM_REG_PWRCTRL_DEVICEEN_PDM_S 10 126 #define AM_REG_PWRCTRL_DEVICEEN_PDM_M 0x00000400 127 #define AM_REG_PWRCTRL_DEVICEEN_PDM(n) (((uint32_t)(n) << 10) & 0x00000400) 128 #define AM_REG_PWRCTRL_DEVICEEN_PDM_EN 0x00000400 129 #define AM_REG_PWRCTRL_DEVICEEN_PDM_DIS 0x00000000 130 131 // Enable ADC Digital Block 132 #define AM_REG_PWRCTRL_DEVICEEN_ADC_S 9 133 #define AM_REG_PWRCTRL_DEVICEEN_ADC_M 0x00000200 134 #define AM_REG_PWRCTRL_DEVICEEN_ADC(n) (((uint32_t)(n) << 9) & 0x00000200) 135 #define AM_REG_PWRCTRL_DEVICEEN_ADC_EN 0x00000200 136 #define AM_REG_PWRCTRL_DEVICEEN_ADC_DIS 0x00000000 137 138 // Enable UART 1 139 #define AM_REG_PWRCTRL_DEVICEEN_UART1_S 8 140 #define AM_REG_PWRCTRL_DEVICEEN_UART1_M 0x00000100 141 #define AM_REG_PWRCTRL_DEVICEEN_UART1(n) (((uint32_t)(n) << 8) & 0x00000100) 142 #define AM_REG_PWRCTRL_DEVICEEN_UART1_EN 0x00000100 143 #define AM_REG_PWRCTRL_DEVICEEN_UART1_DIS 0x00000000 144 145 // Enable UART 0 146 #define AM_REG_PWRCTRL_DEVICEEN_UART0_S 7 147 #define AM_REG_PWRCTRL_DEVICEEN_UART0_M 0x00000080 148 #define AM_REG_PWRCTRL_DEVICEEN_UART0(n) (((uint32_t)(n) << 7) & 0x00000080) 149 #define AM_REG_PWRCTRL_DEVICEEN_UART0_EN 0x00000080 150 #define AM_REG_PWRCTRL_DEVICEEN_UART0_DIS 0x00000000 151 152 // Enable IO MASTER 5 153 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_S 6 154 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_M 0x00000040 155 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5(n) (((uint32_t)(n) << 6) & 0x00000040) 156 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_EN 0x00000040 157 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER5_DIS 0x00000000 158 159 // Enable IO MASTER 4 160 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_S 5 161 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_M 0x00000020 162 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4(n) (((uint32_t)(n) << 5) & 0x00000020) 163 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_EN 0x00000020 164 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER4_DIS 0x00000000 165 166 // Enable IO MASTER 3 167 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_S 4 168 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_M 0x00000010 169 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3(n) (((uint32_t)(n) << 4) & 0x00000010) 170 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_EN 0x00000010 171 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER3_DIS 0x00000000 172 173 // Enable IO MASTER 2 174 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_S 3 175 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_M 0x00000008 176 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2(n) (((uint32_t)(n) << 3) & 0x00000008) 177 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_EN 0x00000008 178 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER2_DIS 0x00000000 179 180 // Enable IO MASTER 1 181 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_S 2 182 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_M 0x00000004 183 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1(n) (((uint32_t)(n) << 2) & 0x00000004) 184 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_EN 0x00000004 185 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER1_DIS 0x00000000 186 187 // Enable IO MASTER 0 188 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_S 1 189 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_M 0x00000002 190 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0(n) (((uint32_t)(n) << 1) & 0x00000002) 191 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_EN 0x00000002 192 #define AM_REG_PWRCTRL_DEVICEEN_IO_MASTER0_DIS 0x00000000 193 194 // Enable IO SLAVE 195 #define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_S 0 196 #define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_M 0x00000001 197 #define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE(n) (((uint32_t)(n) << 0) & 0x00000001) 198 #define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_EN 0x00000001 199 #define AM_REG_PWRCTRL_DEVICEEN_IO_SLAVE_DIS 0x00000000 200 201 //***************************************************************************** 202 // 203 // PWRCTRL_SRAMPWDINSLEEP - Powerdown an SRAM Banks in Deep Sleep mode 204 // 205 //***************************************************************************** 206 // Enable CACHE BANKS to power down in deep sleep 207 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_S 31 208 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_M 0x80000000 209 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP(n) (((uint32_t)(n) << 31) & 0x80000000) 210 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_EN 0x80000000 211 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_CACHE_PWD_SLP_DIS 0x00000000 212 213 // Selects which SRAM banks are powered down in deep sleep mode, causing the 214 // contents of the bank to be lost. 215 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_S 0 216 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_M 0x000007FF 217 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN(n) (((uint32_t)(n) << 0) & 0x000007FF) 218 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_NONE 0x00000000 219 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM0 0x00000001 220 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM1 0x00000002 221 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM2 0x00000004 222 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP0_SRAM3 0x00000008 223 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP1 0x00000010 224 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP2 0x00000020 225 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP3 0x00000040 226 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP4 0x00000080 227 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP5 0x00000100 228 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP6 0x00000200 229 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_GROUP7 0x00000400 230 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM8K 0x00000001 231 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM16K 0x00000003 232 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM32K 0x0000000F 233 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM64K 0x0000001F 234 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_SRAM128K 0x0000007F 235 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER8K 0x000007FE 236 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER16K 0x000007FC 237 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER24K 0x000007F8 238 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER32K 0x000007F0 239 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER64K 0x000007E0 240 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALLBUTLOWER128K 0x00000780 241 #define AM_REG_PWRCTRL_SRAMPWDINSLEEP_SRAMSLEEPPOWERDOWN_ALL 0x000007FF 242 243 //***************************************************************************** 244 // 245 // PWRCTRL_MEMEN - Disables individual banks of the MEMORY array 246 // 247 //***************************************************************************** 248 // Enable CACHE BANK 2 249 #define AM_REG_PWRCTRL_MEMEN_CACHEB2_S 31 250 #define AM_REG_PWRCTRL_MEMEN_CACHEB2_M 0x80000000 251 #define AM_REG_PWRCTRL_MEMEN_CACHEB2(n) (((uint32_t)(n) << 31) & 0x80000000) 252 #define AM_REG_PWRCTRL_MEMEN_CACHEB2_EN 0x80000000 253 #define AM_REG_PWRCTRL_MEMEN_CACHEB2_DIS 0x00000000 254 255 // Enable CACHE BANK 0 256 #define AM_REG_PWRCTRL_MEMEN_CACHEB0_S 29 257 #define AM_REG_PWRCTRL_MEMEN_CACHEB0_M 0x20000000 258 #define AM_REG_PWRCTRL_MEMEN_CACHEB0(n) (((uint32_t)(n) << 29) & 0x20000000) 259 #define AM_REG_PWRCTRL_MEMEN_CACHEB0_EN 0x20000000 260 #define AM_REG_PWRCTRL_MEMEN_CACHEB0_DIS 0x00000000 261 262 // Enable FLASH1 263 #define AM_REG_PWRCTRL_MEMEN_FLASH1_S 12 264 #define AM_REG_PWRCTRL_MEMEN_FLASH1_M 0x00001000 265 #define AM_REG_PWRCTRL_MEMEN_FLASH1(n) (((uint32_t)(n) << 12) & 0x00001000) 266 #define AM_REG_PWRCTRL_MEMEN_FLASH1_EN 0x00001000 267 #define AM_REG_PWRCTRL_MEMEN_FLASH1_DIS 0x00000000 268 269 // Enable FLASH 0 270 #define AM_REG_PWRCTRL_MEMEN_FLASH0_S 11 271 #define AM_REG_PWRCTRL_MEMEN_FLASH0_M 0x00000800 272 #define AM_REG_PWRCTRL_MEMEN_FLASH0(n) (((uint32_t)(n) << 11) & 0x00000800) 273 #define AM_REG_PWRCTRL_MEMEN_FLASH0_EN 0x00000800 274 #define AM_REG_PWRCTRL_MEMEN_FLASH0_DIS 0x00000000 275 276 // Enables power for selected SRAM banks (else an access to its address space to 277 // generate a Hard Fault). 278 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_S 0 279 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_M 0x000007FF 280 #define AM_REG_PWRCTRL_MEMEN_SRAMEN(n) (((uint32_t)(n) << 0) & 0x000007FF) 281 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_NONE 0x00000000 282 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM0 0x00000001 283 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM1 0x00000002 284 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM2 0x00000004 285 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP0_SRAM3 0x00000008 286 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP1 0x00000010 287 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP2 0x00000020 288 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP3 0x00000040 289 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP4 0x00000080 290 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP5 0x00000100 291 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP6 0x00000200 292 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_GROUP7 0x00000400 293 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM8K 0x00000001 294 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM16K 0x00000003 295 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM32K 0x0000000F 296 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM64K 0x0000001F 297 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM128K 0x0000007F 298 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_SRAM256K 0x000007FF 299 #define AM_REG_PWRCTRL_MEMEN_SRAMEN_ALL 0x000007FF 300 301 //***************************************************************************** 302 // 303 // PWRCTRL_PWRONSTATUS - POWER ON Status 304 // 305 //***************************************************************************** 306 // This bit is 1 if power is supplied to CACHE BANK 2 307 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_S 21 308 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2_M 0x00200000 309 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB2(n) (((uint32_t)(n) << 21) & 0x00200000) 310 311 // This bit is 1 if power is supplied to CACHE BANK 0 312 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_S 19 313 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0_M 0x00080000 314 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_CACHEB0(n) (((uint32_t)(n) << 19) & 0x00080000) 315 316 // This bit is 1 if power is supplied to SRAM domain PD_GRP7 317 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_S 18 318 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM_M 0x00040000 319 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP7_SRAM(n) (((uint32_t)(n) << 18) & 0x00040000) 320 321 // This bit is 1 if power is supplied to SRAM domain PD_GRP6 322 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_S 17 323 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM_M 0x00020000 324 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP6_SRAM(n) (((uint32_t)(n) << 17) & 0x00020000) 325 326 // This bit is 1 if power is supplied to SRAM domain PD_GRP5 327 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_S 16 328 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM_M 0x00010000 329 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP5_SRAM(n) (((uint32_t)(n) << 16) & 0x00010000) 330 331 // This bit is 1 if power is supplied to SRAM domain PD_GRP4 332 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_S 15 333 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM_M 0x00008000 334 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP4_SRAM(n) (((uint32_t)(n) << 15) & 0x00008000) 335 336 // This bit is 1 if power is supplied to SRAM domain PD_GRP3 337 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_S 14 338 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM_M 0x00004000 339 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP3_SRAM(n) (((uint32_t)(n) << 14) & 0x00004000) 340 341 // This bit is 1 if power is supplied to SRAM domain PD_GRP2 342 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_S 13 343 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM_M 0x00002000 344 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP2_SRAM(n) (((uint32_t)(n) << 13) & 0x00002000) 345 346 // This bit is 1 if power is supplied to SRAM domain PD_GRP1 347 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_S 12 348 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM_M 0x00001000 349 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP1_SRAM(n) (((uint32_t)(n) << 12) & 0x00001000) 350 351 // This bit is 1 if power is supplied to SRAM domain PD_SRAM0_3 352 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_S 11 353 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3_M 0x00000800 354 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM3(n) (((uint32_t)(n) << 11) & 0x00000800) 355 356 // This bit is 1 if power is supplied to SRAM domain PD_SRAM0_2 357 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_S 10 358 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2_M 0x00000400 359 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM2(n) (((uint32_t)(n) << 10) & 0x00000400) 360 361 // This bit is 1 if power is supplied to SRAM domain SRAM0_1 362 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_S 9 363 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1_M 0x00000200 364 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM1(n) (((uint32_t)(n) << 9) & 0x00000200) 365 366 // This bit is 1 if power is supplied to SRAM domain SRAM0_0 367 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_S 8 368 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0_M 0x00000100 369 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_GRP0_SRAM0(n) (((uint32_t)(n) << 8) & 0x00000100) 370 371 // This bit is 1 if power is supplied to domain PD_ADC 372 #define AM_REG_PWRCTRL_PWRONSTATUS_PDADC_S 7 373 #define AM_REG_PWRCTRL_PWRONSTATUS_PDADC_M 0x00000080 374 #define AM_REG_PWRCTRL_PWRONSTATUS_PDADC(n) (((uint32_t)(n) << 7) & 0x00000080) 375 376 // This bit is 1 if power is supplied to domain PD_FLAM1 377 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_S 6 378 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1_M 0x00000040 379 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM1(n) (((uint32_t)(n) << 6) & 0x00000040) 380 381 // This bit is 1 if power is supplied to domain PD_FLAM0 382 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_S 5 383 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0_M 0x00000020 384 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_FLAM0(n) (((uint32_t)(n) << 5) & 0x00000020) 385 386 // This bit is 1 if power is supplied to domain PD_PDM 387 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM_S 4 388 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM_M 0x00000010 389 #define AM_REG_PWRCTRL_PWRONSTATUS_PD_PDM(n) (((uint32_t)(n) << 4) & 0x00000010) 390 391 // This bit is 1 if power is supplied to power domain C, which supplies IOM3-5. 392 #define AM_REG_PWRCTRL_PWRONSTATUS_PDC_S 3 393 #define AM_REG_PWRCTRL_PWRONSTATUS_PDC_M 0x00000008 394 #define AM_REG_PWRCTRL_PWRONSTATUS_PDC(n) (((uint32_t)(n) << 3) & 0x00000008) 395 396 // This bit is 1 if power is supplied to power domain B, which supplies IOM0-2. 397 #define AM_REG_PWRCTRL_PWRONSTATUS_PDB_S 2 398 #define AM_REG_PWRCTRL_PWRONSTATUS_PDB_M 0x00000004 399 #define AM_REG_PWRCTRL_PWRONSTATUS_PDB(n) (((uint32_t)(n) << 2) & 0x00000004) 400 401 // This bit is 1 if power is supplied to power domain A, which supplies IOS and 402 // UART0,1. 403 #define AM_REG_PWRCTRL_PWRONSTATUS_PDA_S 1 404 #define AM_REG_PWRCTRL_PWRONSTATUS_PDA_M 0x00000002 405 #define AM_REG_PWRCTRL_PWRONSTATUS_PDA(n) (((uint32_t)(n) << 1) & 0x00000002) 406 407 //***************************************************************************** 408 // 409 // PWRCTRL_SRAMCTRL - SRAM Control register 410 // 411 //***************************************************************************** 412 // Enables top-level clock gating in the SRAM block. This bit should be enabled 413 // for lowest power operation. 414 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_S 2 415 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_M 0x00000004 416 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE(n) (((uint32_t)(n) << 2) & 0x00000004) 417 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_EN 0x00000004 418 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_MASTER_CLKGATE_DIS 0x00000000 419 420 // Enables individual per-RAM clock gating in the SRAM block. This bit should 421 // be enabled for lowest power operation. 422 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_S 1 423 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_M 0x00000002 424 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE(n) (((uint32_t)(n) << 1) & 0x00000002) 425 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_EN 0x00000002 426 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_CLKGATE_DIS 0x00000000 427 428 // Enable LS (light sleep) of cache RAMs. When this bit is set, the RAMS will 429 // be put into light sleep mode while inactive. NOTE: if the SRAM is actively 430 // used, this may have an adverse affect on power since entering/exiting LS mode 431 // may consume more power than would be saved. 432 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_S 0 433 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_M 0x00000001 434 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP(n) (((uint32_t)(n) << 0) & 0x00000001) 435 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_EN 0x00000001 436 #define AM_REG_PWRCTRL_SRAMCTRL_SRAM_LIGHT_SLEEP_DIS 0x00000000 437 438 //***************************************************************************** 439 // 440 // PWRCTRL_ADCSTATUS - Power Status Register for ADC Block 441 // 442 //***************************************************************************** 443 // This bit indicates that the ADC REFBUF is powered down 444 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD_S 5 445 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD_M 0x00000020 446 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFBUF_PWD(n) (((uint32_t)(n) << 5) & 0x00000020) 447 448 // This bit indicates that the ADC REFKEEP is powered down 449 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD_S 4 450 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD_M 0x00000010 451 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_REFKEEP_PWD(n) (((uint32_t)(n) << 4) & 0x00000010) 452 453 // This bit indicates that the ADC VBAT resistor divider is powered down 454 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_VBAT_PWD_S 3 455 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_VBAT_PWD_M 0x00000008 456 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_VBAT_PWD(n) (((uint32_t)(n) << 3) & 0x00000008) 457 458 // This bit indicates that the ADC temperature sensor input buffer is powered 459 // down 460 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD_S 2 461 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD_M 0x00000004 462 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_VPTAT_PWD(n) (((uint32_t)(n) << 2) & 0x00000004) 463 464 // This bit indicates that the ADC Band Gap is powered down 465 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_BGT_PWD_S 1 466 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_BGT_PWD_M 0x00000002 467 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_BGT_PWD(n) (((uint32_t)(n) << 1) & 0x00000002) 468 469 // This bit indicates that the ADC is powered down 470 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_PWD_S 0 471 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_PWD_M 0x00000001 472 #define AM_REG_PWRCTRL_ADCSTATUS_ADC_PWD(n) (((uint32_t)(n) << 0) & 0x00000001) 473 474 //***************************************************************************** 475 // 476 // PWRCTRL_MISCOPT - Power Optimization Control Bits 477 // 478 //***************************************************************************** 479 // Setting this bit will enable the MEM LDO to be in LPMODE during deep sleep 480 // even when the ctimers or stimers are running 481 #define AM_REG_PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS_S 2 482 #define AM_REG_PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS_M 0x00000004 483 #define AM_REG_PWRCTRL_MISCOPT_DIS_LDOLPMODE_TIMERS(n) (((uint32_t)(n) << 2) & 0x00000004) 484 485 #endif // AM_REG_PWRCTRL_H 486