1 /* 2 * Copyright (c) 2006-2024, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2022-10-10 RT-Thread the first version, 9 * compatible to riscv-v-spec-1.0 10 */ 11 #ifndef __RVV_CONTEXT_1_0_H__ 12 #define __RVV_CONTEXT_1_0_H__ 13 14 #if defined(ARCH_VECTOR_VLEN_128) 15 #define CTX_VECTOR_REGS 64 16 #elif defined(ARCH_VECTOR_VLEN_256) 17 #define CTX_VECTOR_REGS 128 18 #else 19 #error "No supported VLEN" 20 #endif /* VLEN */ 21 22 #define CTX_VECTOR_REG_NR (CTX_VECTOR_REGS + 4) 23 24 #ifdef __ASSEMBLY__ 25 26 /** 27 * ================================== 28 * VECTOR EXTENSION 29 * ================================== 30 */ 31 32 #define VEC_FRAME_VSTART (0 * REGBYTES) 33 #define VEC_FRAME_VTYPE (1 * REGBYTES) 34 #define VEC_FRAME_VL (2 * REGBYTES) 35 #define VEC_FRAME_VCSR (3 * REGBYTES) 36 #define VEC_FRAME_V0 (4 * REGBYTES) 37 38 .macro GET_VEC_FRAME_LEN, xreg 39 csrr \xreg, vlenb 40 slli \xreg, \xreg, 5 41 addi \xreg, \xreg, 4 * REGBYTES 42 .endm 43 44 /** 45 * @brief save vector extension hardware state 46 * 47 * @param dst register storing bottom of storage block 48 * 49 */ 50 .macro SAVE_VECTOR, dst 51 mv t1, \dst 52 53 csrr t0, vstart 54 STORE t0, VEC_FRAME_VSTART(t1) 55 csrr t0, vtype 56 STORE t0, VEC_FRAME_VTYPE(t1) 57 csrr t0, vl 58 STORE t0, VEC_FRAME_VL(t1) 59 csrr t0, vcsr 60 STORE t0, VEC_FRAME_VCSR(t1) 61 62 addi t1, t1, VEC_FRAME_V0 63 64 // config vector setting, 65 // t2 is updated to length of a vector group in bytes 66 VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8) 67 68 vse8.v v0, (t1) 69 add t1, t1, t2 70 vse8.v v8, (t1) 71 add t1, t1, t2 72 vse8.v v16, (t1) 73 add t1, t1, t2 74 vse8.v v24, (t1) 75 .endm 76 77 /** 78 * @brief restore vector extension hardware states 79 * 80 * @param dst register storing bottom of storage block 81 * 82 */ 83 .macro RESTORE_VECTOR, dst 84 // restore vector registers first since it will modify vector states 85 mv t0, \dst 86 addi t1, t0, VEC_FRAME_V0 87 88 VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8) 89 90 vle8.v v0, (t1) 91 add t1, t1, t2 92 vle8.v v8, (t1) 93 add t1, t1, t2 94 vle8.v v16, (t1) 95 add t1, t1, t2 96 vle8.v v24, (t1) 97 98 mv t1, t0 99 100 LOAD t0, VEC_FRAME_VSTART(t1) 101 csrw vstart, t0 102 LOAD t0, VEC_FRAME_VCSR(t1) 103 csrw vcsr, t0 104 105 LOAD t0, VEC_FRAME_VTYPE(t1) 106 LOAD t3, VEC_FRAME_VL(t1) 107 VEC_CONFIG_SET_VL_VTYPE(t3, t0) 108 .endm 109 110 #endif 111 112 #endif /* __RVV_CONTEXT_H__ */ 113