1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2006-09-06     XuXinming    first version
9  * 2006-09-16     Bernard      modify according to code style
10  */
11 
12 #ifndef __S3C44B0_H__
13 #define __S3C44B0_H__
14 
15 #ifdef __cplusplus
16 extern "C" {
17 #endif
18 
19 /**
20  * @addtogroup S3C44B0
21  */
22 /*@{*/
23 
24 /*------------------------------------------------------------------------
25  *    ASIC Address Definition
26  *----------------------------------------------------------------------*/
27 #define S3C_REG     *(volatile unsigned int *)
28 #define S3C_REGW    *(volatile unsigned short *)
29 #define S3C_REGB    *(volatile unsigned char *)
30 
31 /* System */
32 #define SYSCFG      (S3C_REG(0x1c00000))
33 
34 /* Cache */
35 #define NCACHBE0    (S3C_REG(0x1c00004))
36 #define NCACHBE1    (S3C_REG(0x1c00008))
37 
38 /* Bus control */
39 #define SBUSCON     (S3C_REG(0x1c40000))
40 
41 /* Memory control */
42 #define BWSCON      (S3C_REG(0x1c80000))
43 #define BANKCON0    (S3C_REG(0x1c80004))
44 #define BANKCON1    (S3C_REG(0x1c80008))
45 #define BANKCON2    (S3C_REG(0x1c8000c))
46 #define BANKCON3    (S3C_REG(0x1c80010))
47 #define BANKCON4    (S3C_REG(0x1c80014))
48 #define BANKCON5    (S3C_REG(0x1c80018))
49 #define BANKCON6    (S3C_REG(0x1c8001c))
50 #define BANKCON7    (S3C_REG(0x1c80020))
51 #define REFRESH     (S3C_REG(0x1c80024))
52 #define BANKSIZE    (S3C_REG(0x1c80028))
53 #define MRSRB6      (S3C_REG(0x1c8002c))
54 #define MRSRB7      (S3C_REG(0x1c80030))
55 
56 /* UART */
57 #define ULCON0      (S3C_REG(0x1d00000))
58 #define ULCON1      (S3C_REG(0x1d04000))
59 #define UCON0       (S3C_REG(0x1d00004))
60 #define UCON1       (S3C_REG(0x1d04004))
61 #define UFCON0      (S3C_REG(0x1d00008))
62 #define UFCON1      (S3C_REG(0x1d04008))
63 #define UMCON0      (S3C_REG(0x1d0000c))
64 #define UMCON1      (S3C_REG(0x1d0400c))
65 #define UTRSTAT0    (S3C_REG(0x1d00010))
66 #define UTRSTAT1    (S3C_REG(0x1d04010))
67 #define UERSTAT0    (S3C_REG(0x1d00014))
68 #define UERSTAT1    (S3C_REG(0x1d04014))
69 #define UFSTAT0     (S3C_REG(0x1d00018))
70 #define UFSTAT1     (S3C_REG(0x1d04018))
71 #define UMSTAT0     (S3C_REG(0x1d0001c))
72 #define UMSTAT1     (S3C_REG(0x1d0401c))
73 #define UBRDIV0     (S3C_REG(0x1d00028))
74 #define UBRDIV1     (S3C_REG(0x1d04028))
75 
76 #define UTXH0       (S3C_REGB(0x1d00020))
77 #define UTXH1       (S3C_REGB(0x1d04020))
78 #define URXH0       (S3C_REGB(0x1d00024))
79 #define URXH1       (S3C_REGB(0x1d04024))
80 
81 /* SIO */
82 #define SIOCON      (S3C_REG(0x1d14000))
83 #define SIODAT      (S3C_REG(0x1d14004))
84 #define SBRDR       (S3C_REG(0x1d14008))
85 #define IVTCNT      (S3C_REG(0x1d1400c))
86 #define DCNTZ       (S3C_REG(0x1d14010))
87 
88 /* IIS */
89 #define IISCON      (S3C_REG(0x1d18000))
90 #define IISMOD      (S3C_REG(0x1d18004))
91 #define IISPSR      (S3C_REG(0x1d18008))
92 #define IISFCON     (S3C_REG(0x1d1800c))
93 
94 #define IISFIF      (S3C_REQW(0x1d18010))
95 
96 /* I/O Port */
97 #define PCONA       (S3C_REG(0x1d20000))
98 #define PDATA       (S3C_REG(0x1d20004))
99 
100 #define PCONB       (S3C_REG(0x1d20008))
101 #define PDATB       (S3C_REG(0x1d2000c))
102 
103 #define PCONC       (S3C_REG(0x1d20010))
104 #define PDATC       (S3C_REG(0x1d20014))
105 #define PUPC        (S3C_REG(0x1d20018))
106 
107 #define PCOND       (S3C_REG(0x1d2001c))
108 #define PDATD       (S3C_REG(0x1d20020))
109 #define PUPD        (S3C_REG(0x1d20024))
110 
111 #define PCONE       (S3C_REG(0x1d20028))
112 #define PDATE       (S3C_REG(0x1d2002c))
113 #define PUPE        (S3C_REG(0x1d20030))
114 
115 #define PCONF       (S3C_REG(0x1d20034))
116 #define PDATF       (S3C_REG(0x1d20038))
117 #define PUPF        (S3C_REG(0x1d2003c))
118 
119 #define PCONG       (S3C_REG(0x1d20040))
120 #define PDATG       (S3C_REG(0x1d20044))
121 #define PUPG        (S3C_REG(0x1d20048))
122 
123 #define SPUCR       (S3C_REG(0x1d2004c))
124 #define EXTINT      (S3C_REG(0x1d20050))
125 #define EXTINTPND   (S3C_REG(0x1d20054))
126 
127 /* Watchdog */
128 #define WTCON       (S3C_REG(0x1d30000))
129 #define WTDAT       (S3C_REG(0x1d30004))
130 #define WTCNT       (S3C_REG(0x1d30008))
131 
132 /* ADC */
133 #define ADCCON      (S3C_REG(0x1d40000))
134 #define ADCPSR      (S3C_REG(0x1d40004))
135 #define ADCDAT      (S3C_REG(0x1d40008))
136 
137 /* Timer */
138 #define TCFG0       (S3C_REG(0x1d50000))
139 #define TCFG1       (S3C_REG(0x1d50004))
140 #define TCON        (S3C_REG(0x1d50008))
141 
142 #define TCNTB0      (S3C_REG(0x1d5000c))
143 #define TCMPB0      (S3C_REG(0x1d50010))
144 #define TCNTO0      (S3C_REG(0x1d50014))
145 
146 #define TCNTB1      (S3C_REG(0x1d50018))
147 #define TCMPB1      (S3C_REG(0x1d5001c))
148 #define TCNTO1      (S3C_REG(0x1d50020))
149 
150 #define TCNTB2      (S3C_REG(0x1d50024))
151 #define TCMPB2      (S3C_REG(0x1d50028))
152 #define TCNTO2      (S3C_REG(0x1d5002c))
153 
154 #define TCNTB3      (S3C_REG(0x1d50030))
155 #define TCMPB3      (S3C_REG(0x1d50034))
156 #define TCNTO3      (S3C_REG(0x1d50038))
157 
158 #define TCNTB4      (S3C_REG(0x1d5003c))
159 #define TCMPB4      (S3C_REG(0x1d50040))
160 #define TCNTO4      (S3C_REG(0x1d50044))
161 
162 #define TCNTB5      (S3C_REG(0x1d50048))
163 #define TCNTO5      (S3C_REG(0x1d5004c))
164 
165 /* IIC */
166 #define IICCON      (S3C_REG(0x1d60000))
167 #define IICSTAT     (S3C_REG(0x1d60004))
168 #define IICADD      (S3C_REG(0x1d60008))
169 #define IICDS       (S3C_REG(0x1d6000c))
170 
171 /* RTC */
172 #define RTCCON      (S3C_REGB(0x1d70040)
173 #define RTCALM      (S3C_REGB(0x1d70050)
174 #define ALMSEC      (S3C_REGB(0x1d70054)
175 #define ALMMIN      (S3C_REGB(0x1d70058)
176 #define ALMHOUR     (S3C_REGB(0x1d7005c)
177 #define ALMDAY      (S3C_REGB(0x1d70060)
178 #define ALMMON      (S3C_REGB(0x1d70064)
179 #define ALMYEAR     (S3C_REGB(0x1d70068)
180 #define RTCRST      (S3C_REGB(0x1d7006c)
181 #define BCDSEC      (S3C_REGB(0x1d70070)
182 #define BCDMIN      (S3C_REGB(0x1d70074)
183 #define BCDHOUR     (S3C_REGB(0x1d70078)
184 #define BCDDAY      (S3C_REGB(0x1d7007c)
185 #define BCDDATE     (S3C_REGB(0x1d70080)
186 #define BCDMON      (S3C_REGB(0x1d70084)
187 #define BCDYEAR     (S3C_REGB(0x1d70088)
188 #define TICINT      (S3C_REGB(0x1d7008c)
189 
190 /* Clock & Power management */
191 #define PLLCON      (S3C_REG(0x1d80000))
192 #define CLKCON      (S3C_REG(0x1d80004))
193 #define CLKSLOW     (S3C_REG(0x1d80008))
194 #define LOCKTIME    (S3C_REG(0x1d8000c))
195 
196 /* Interrupt */
197 #define INTCON      (S3C_REG(0x1e00000))
198 #define INTPND      (S3C_REG(0x1e00004))
199 #define INTMOD      (S3C_REG(0x1e00008))
200 #define INTMSK      (S3C_REG(0x1e0000c))
201 
202 #define I_PSLV      (S3C_REG(0x1e00010))
203 #define I_PMST      (S3C_REG(0x1e00014))
204 #define I_CSLV      (S3C_REG(0x1e00018))
205 #define I_CMST      (S3C_REG(0x1e0001c))
206 #define I_ISPR      (S3C_REG(0x1e00020))
207 #define I_ISPC      (S3C_REG(0x1e00024))
208 
209 #define F_ISPR      (S3C_REG(0x1e00038))
210 #define F_ISPC      (S3C_REG(0x1e0003c))
211 
212 /********************************/
213 /* LCD Controller Registers     */
214 /********************************/
215 #define LCDCON1     (S3C_REG(0x300000))
216 #define LCDCON2     (S3C_REG(0x300004))
217 #define LCDSADDR1   (S3C_REG(0x300008))
218 #define LCDSADDR2   (S3C_REG(0x30000c))
219 #define LCDSADDR3   (S3C_REG(0x300010))
220 #define REDLUT      (S3C_REG(0x300014))
221 #define GREENLUT    (S3C_REG(0x300018))
222 #define BLUELUT     (S3C_REG(0x30001c))
223 #define DP1_2       (S3C_REG(0x300020))
224 #define DP4_7       (S3C_REG(0x300024))
225 #define DP3_5       (S3C_REG(0x300028))
226 #define DP2_3       (S3C_REG(0x30002c))
227 #define DP5_7       (S3C_REG(0x300030))
228 #define DP3_4       (S3C_REG(0x300034))
229 #define DP4_5       (S3C_REG(0x300038))
230 #define DP6_7       (S3C_REG(0x30003c))
231 #define LCDCON3     (S3C_REG(0x300040))
232 #define DITHMODE    (S3C_REG(0x300044))
233 
234 /* ZDMA0 */
235 #define ZDCON0      (S3C_REG(0x1e80000))
236 #define ZDISRC0     (S3C_REG(0x1e80004))
237 #define ZDIDES0     (S3C_REG(0x1e80008))
238 #define ZDICNT0     (S3C_REG(0x1e8000c))
239 #define ZDCSRC0     (S3C_REG(0x1e80010))
240 #define ZDCDES0     (S3C_REG(0x1e80014))
241 #define ZDCCNT0     (S3C_REG(0x1e80018))
242 
243 /* ZDMA1 */
244 #define ZDCON1      (S3C_REG(0x1e80020))
245 #define ZDISRC1     (S3C_REG(0x1e80024))
246 #define ZDIDES1     (S3C_REG(0x1e80028))
247 #define ZDICNT1     (S3C_REG(0x1e8002c))
248 #define ZDCSRC1     (S3C_REG(0x1e80030))
249 #define ZDCDES1     (S3C_REG(0x1e80034))
250 #define ZDCCNT1     (S3C_REG(0x1e80038))
251 
252 /* BDMA0 */
253 #define BDCON0      (S3C_REG(0x1f80000))
254 #define BDISRC0     (S3C_REG(0x1f80004))
255 #define BDIDES0     (S3C_REG(0x1f80008))
256 #define BDICNT0     (S3C_REG(0x1f8000c))
257 #define BDCSRC0     (S3C_REG(0x1f80010))
258 #define BDCDES0     (S3C_REG(0x1f80014))
259 #define BDCCNT0     (S3C_REG(0x1f80018))
260 
261 /* BDMA1 */
262 #define BDCON1      (S3C_REG(0x1f80020))
263 #define BDISRC1     (S3C_REG(0x1f80024))
264 #define BDIDES1     (S3C_REG(0x1f80028))
265 #define BDICNT1     (S3C_REG(0x1f8002c))
266 #define BDCSRC1     (S3C_REG(0x1f80030))
267 #define BDCDES1     (S3C_REG(0x1f80034))
268 #define BDCCNT1     (S3C_REG(0x1f80038))
269 
270 /*****************************/
271 /* CPU Mode                  */
272 /*****************************/
273 #define USERMODE    0x10        /* User Mode(USR) */
274 #define FIQMODE     0x11        /* Fast Interrupt Mode (FIQ) */
275 #define IRQMODE     0x12        /* Interrupt Mode (IRQ) */
276 #define SVCMODE     0x13        /* Supervisor Mode (SVC) */
277 #define ABORTMODE   0x17        /* Abort Mode(ABT) */
278 #define UNDEFMODE   0x1b        /* Undefine Mode(UDF) */
279 #define MODEMASK    0x1f        /* Processor Mode Mask */
280 #define NOINT       0xc0
281 
282 /*****************************/
283 /* INT Define                */
284 /*****************************/
285 #define INT_ADC     0x00
286 #define INT_RTC     0x01
287 #define INT_UTXD1   0x02
288 #define INT_UTXD0   0x03
289 #define INT_SIO     0x04
290 #define INT_IIC     0x05
291 #define INT_URXD1   0x06
292 #define INT_URXD0   0x07
293 #define INT_TIMER5  0x08
294 #define INT_TIMER4  0x09
295 #define INT_TIMER3  0x0A
296 #define INT_TIMER2  0x0B
297 #define INT_TIMER1  0x0C
298 #define INT_TIMER0  0x0D
299 #define INT_UERR01  0x0E
300 #define INT_WDT     0x1F
301 #define INT_BDMA1   0x10
302 #define INT_BDMA0   0x11
303 #define INT_ZDMA1   0x12
304 #define INT_ZDMA0   0x13
305 #define INT_TICK    0x14
306 #define INT_EINT4567    0x15
307 #define INT_EINT3   0x16
308 #define INT_EINT2   0x17
309 #define INT_EINT1   0x18
310 #define INT_EINT0   0x19
311 
312 #define INT_GLOBAL  26
313 
314 struct rt_hw_register
315 {
316     unsigned long r0;
317     unsigned long r1;
318     unsigned long r2;
319     unsigned long r3;
320     unsigned long r4;
321     unsigned long r5;
322     unsigned long r6;
323     unsigned long r7;
324     unsigned long r8;
325     unsigned long r9;
326     unsigned long r10;
327     unsigned long fp;
328     unsigned long ip;
329     unsigned long sp;
330     unsigned long lr;
331     unsigned long pc;
332     unsigned long cpsr;
333     unsigned long ORIG_r0;
334 };
335 
336 /*@}*/
337 
338 #ifdef __cplusplus
339 }
340 #endif
341 
342 #endif
343