1 /*
2 * Copyright (c) 2012, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
6 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
9 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
11 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
12 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
13 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
14 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15 */
16
17 // File: spdif_iomux_config.c
18
19 /* ------------------------------------------------------------------------------
20 * <auto-generated>
21 * This code was generated by a tool.
22 * Runtime Version:3.4.0.0
23 *
24 * Changes to this file may cause incorrect behavior and will be lost if
25 * the code is regenerated.
26 * </auto-generated>
27 * ------------------------------------------------------------------------------
28 */
29
30 #include "iomux_config.h"
31 #include "registers/regsiomuxc.h"
32
33 // Function to configure IOMUXC for spdif module.
spdif_iomux_config(void)34 void spdif_iomux_config(void)
35 {
36 // Config spdif.SPDIF_IN to pad KEY_COL3(U5)
37 // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR(0x00000006);
38 // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR(0x00003000);
39 // HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_WR(0x00000002);
40 // Mux Register:
41 // IOMUXC_SW_MUX_CTL_PAD_KEY_COL3(0x020E0250)
42 // SION [4] - Software Input On Field Reset: DISABLED
43 // Force the selected mux mode Input path no matter of MUX_MODE functionality.
44 // DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
45 // ENABLED (1) - Force input path of pad.
46 // MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
47 // Select iomux modes to be used for pad.
48 // ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SS3
49 // ALT1 (1) - Select instance: enet signal: ENET_CRS
50 // ALT2 (2) - Select instance: hdmi signal: HDMI_TX_DDC_SCL
51 // ALT3 (3) - Select instance: kpp signal: KEY_COL3
52 // ALT4 (4) - Select instance: i2c2 signal: I2C2_SCL
53 // ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO12
54 // ALT6 (6) - Select instance: spdif signal: SPDIF_IN
55 HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_WR(
56 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_SION_V(DISABLED) |
57 BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_MUX_MODE_V(ALT6));
58 // Pad Control Register:
59 // IOMUXC_SW_PAD_CTL_PAD_KEY_COL3(0x020E0638)
60 // HYS [16] - Hysteresis Enable Field Reset: ENABLED
61 // DISABLED (0) - CMOS input
62 // ENABLED (1) - Schmitt trigger input
63 // PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
64 // 100K_OHM_PD (0) - 100K Ohm Pull Down
65 // 47K_OHM_PU (1) - 47K Ohm Pull Up
66 // 100K_OHM_PU (2) - 100K Ohm Pull Up
67 // 22K_OHM_PU (3) - 22K Ohm Pull Up
68 // PUE [13] - Pull / Keep Select Field Reset: PULL
69 // KEEP (0) - Keeper Enabled
70 // PULL (1) - Pull Enabled
71 // PKE [12] - Pull / Keep Enable Field Reset: ENABLED
72 // DISABLED (0) - Pull/Keeper Disabled
73 // ENABLED (1) - Pull/Keeper Enabled
74 // ODE [11] - Open Drain Enable Field Reset: DISABLED
75 // Enables open drain of the pin.
76 // DISABLED (0) - Output is CMOS.
77 // ENABLED (1) - Output is Open Drain.
78 // SPEED [7:6] - Speed Field Reset: 100MHZ
79 // RESERVED0 (0) - Reserved
80 // 50MHZ (1) - Low (50 MHz)
81 // 100MHZ (2) - Medium (100 MHz)
82 // 200MHZ (3) - Maximum (200 MHz)
83 // DSE [5:3] - Drive Strength Field Reset: 40_OHM
84 // HIZ (0) - HI-Z
85 // 240_OHM (1) - 240 Ohm
86 // 120_OHM (2) - 120 Ohm
87 // 80_OHM (3) - 80 Ohm
88 // 60_OHM (4) - 60 Ohm
89 // 48_OHM (5) - 48 Ohm
90 // 40_OHM (6) - 40 Ohm
91 // 34_OHM (7) - 34 Ohm
92 // SRE [0] - Slew Rate Field Reset: SLOW
93 // Slew rate control.
94 // SLOW (0) - Slow Slew Rate
95 // FAST (1) - Fast Slew Rate
96 HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_WR(
97 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_HYS_V(DISABLED) |
98 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUS_V(100K_OHM_PD) |
99 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PUE_V(PULL) |
100 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_PKE_V(ENABLED) |
101 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_ODE_V(DISABLED) |
102 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SPEED_V(RESERVED0) |
103 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_DSE_V(HIZ) |
104 BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_SRE_V(SLOW));
105 // Pad KEY_COL3 is involved in Daisy Chain.
106 // Input Select Register:
107 // IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT(0x020E08F0)
108 // DAISY [1:0] - MUX Mode Select Field Reset: EIM_DATA21_ALT7
109 // Selecting Pads Involved in Daisy Chain.
110 // EIM_DATA21_ALT7 (0) - Select signal spdif SPDIF_IN as input from pad EIM_DATA21(ALT7).
111 // ENET_RX_ER_ALT3 (1) - Select signal spdif SPDIF_IN as input from pad ENET_RX_ER(ALT3).
112 // GPIO16_ALT4 (2) - Select signal spdif SPDIF_IN as input from pad GPIO16(ALT4).
113 // KEY_COL3_ALT6 (3) - Select signal spdif SPDIF_IN as input from pad KEY_COL3(ALT6).
114 HW_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_WR(
115 BF_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_DAISY_V(GPIO16_ALT4));
116 }
117