1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2011-01-13 weety first version
9 */
10
11 #include <rthw.h>
12 #include <rtthread.h>
13 #include <rtdevice.h>
14 #include <dm36x.h>
15 #include <edma.h>
16 #include "spi-davinci.h"
17
18 #define unlikely(x) x
19
20 #define barrier() __asm__ __volatile__("": : :"memory")
21 #define cpu_relax() barrier()
22
23 #define SPI_DEBUG 0
24 #if SPI_DEBUG
25 #define spi_dbg(dev, fmt, ...) \
26 do { \
27 rt_kprintf("%s:", dev->parent.name); \
28 rt_kprintf(fmt, ##__VA_ARGS__); \
29 } while(0)
30 #else
31 #define spi_dbg(dev, fmt, ...)
32 #endif
33
34 #define SZ_64K 0x10000
35 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
36
37 #define SPI_NO_RESOURCE ((resource_size_t)-1)
38
39 #define SPI_MAX_CHIPSELECT 2
40
41 #define CS_DEFAULT 0xFF
42
43 #define __iomem
44 #define BIT(nr) (1UL << (nr))
45
46 #define SPIFMT_PHASE_MASK BIT(16)
47 #define SPIFMT_POLARITY_MASK BIT(17)
48 #define SPIFMT_DISTIMER_MASK BIT(18)
49 #define SPIFMT_SHIFTDIR_MASK BIT(20)
50 #define SPIFMT_WAITENA_MASK BIT(21)
51 #define SPIFMT_PARITYENA_MASK BIT(22)
52 #define SPIFMT_ODD_PARITY_MASK BIT(23)
53 #define SPIFMT_WDELAY_MASK 0x3f000000u
54 #define SPIFMT_WDELAY_SHIFT 24
55 #define SPIFMT_PRESCALE_SHIFT 8
56
57 /* SPIPC0 */
58 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
59 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
60 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
61 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
62
63 #define SPIINT_MASKALL 0x0101035F
64 #define SPIINT_MASKINT 0x0000015F
65 #define SPI_INTLVL_1 0x000001FF
66 #define SPI_INTLVL_0 0x00000000
67
68 /* SPIDAT1 (upper 16 bit defines) */
69 #define SPIDAT1_CSHOLD_MASK BIT(12)
70
71 /* SPIGCR1 */
72 #define SPIGCR1_CLKMOD_MASK BIT(1)
73 #define SPIGCR1_MASTER_MASK BIT(0)
74 #define SPIGCR1_POWERDOWN_MASK BIT(8)
75 #define SPIGCR1_LOOPBACK_MASK BIT(16)
76 #define SPIGCR1_SPIENA_MASK BIT(24)
77
78 /* SPIBUF */
79 #define SPIBUF_TXFULL_MASK BIT(29)
80 #define SPIBUF_RXEMPTY_MASK BIT(31)
81
82 /* SPIDELAY */
83 #define SPIDELAY_C2TDELAY_SHIFT 24
84 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
85 #define SPIDELAY_T2CDELAY_SHIFT 16
86 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
87 #define SPIDELAY_T2EDELAY_SHIFT 8
88 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
89 #define SPIDELAY_C2EDELAY_SHIFT 0
90 #define SPIDELAY_C2EDELAY_MASK 0xFF
91
92 /* Error Masks */
93 #define SPIFLG_DLEN_ERR_MASK BIT(0)
94 #define SPIFLG_TIMEOUT_MASK BIT(1)
95 #define SPIFLG_PARERR_MASK BIT(2)
96 #define SPIFLG_DESYNC_MASK BIT(3)
97 #define SPIFLG_BITERR_MASK BIT(4)
98 #define SPIFLG_OVRRUN_MASK BIT(6)
99 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
100 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
101 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
102 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
103 | SPIFLG_OVRRUN_MASK)
104
105 #define SPIINT_DMA_REQ_EN BIT(16)
106
107 /* SPI Controller registers */
108 #define SPIGCR0 0x00
109 #define SPIGCR1 0x04
110 #define SPIINT 0x08
111 #define SPILVL 0x0c
112 #define SPIFLG 0x10
113 #define SPIPC0 0x14
114 #define SPIDAT1 0x3c
115 #define SPIBUF 0x40
116 #define SPIDELAY 0x48
117 #define SPIDEF 0x4c
118 #define SPIFMT0 0x50
119
120 /* We have 2 DMA channels per CS, one for RX and one for TX */
121 struct davinci_spi_dma {
122 int tx_channel;
123 int rx_channel;
124 int dummy_param_slot;
125 enum dma_event_q eventq;
126 };
127
128 /* SPI Controller driver's private data. */
129 struct davinci_spi {
130 struct rt_spi_bus parent;
131 struct clk *clk;
132
133 u8 version;
134 void __iomem *base;
135 u32 irq;
136 struct rt_completion done;
137
138 const void *tx;
139 void *rx;
140 #define SMP_CACHE_BYTES 32
141 #define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1)
142 u8 rx_tmp_buf[SPI_TMP_BUFSZ];
143 int rcount;
144 int wcount;
145 struct davinci_spi_dma dma;
146
147 void (*get_rx)(u32 rx_data, struct davinci_spi *);
148 u32 (*get_tx)(struct davinci_spi *);
149
150 u8 bytes_per_word[SPI_MAX_CHIPSELECT];
151 u8 chip_sel[SPI_MAX_CHIPSELECT];
152 struct davinci_spi_config *controller_data;
153 int cshold_bug;
154 };
155
156 static struct davinci_spi_config davinci_spi_default_cfg;
157
158 extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
159 extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
160
davinci_spi_rx_buf_u8(u32 data,struct davinci_spi * dspi)161 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
162 {
163 if (dspi->rx) {
164 u8 *rx = dspi->rx;
165 *rx++ = (u8)data;
166 dspi->rx = rx;
167 }
168 }
169
davinci_spi_rx_buf_u16(u32 data,struct davinci_spi * dspi)170 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
171 {
172 if (dspi->rx) {
173 u16 *rx = dspi->rx;
174 *rx++ = (u16)data;
175 dspi->rx = rx;
176 }
177 }
178
davinci_spi_tx_buf_u8(struct davinci_spi * dspi)179 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
180 {
181 u32 data = 0;
182 if (dspi->tx) {
183 const u8 *tx = dspi->tx;
184 data = *tx++;
185 dspi->tx = tx;
186 }
187 return data;
188 }
189
davinci_spi_tx_buf_u16(struct davinci_spi * dspi)190 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
191 {
192 u32 data = 0;
193 if (dspi->tx) {
194 const u16 *tx = dspi->tx;
195 data = *tx++;
196 dspi->tx = tx;
197 }
198 return data;
199 }
200
set_io_bits(void __iomem * addr,u32 bits)201 static inline void set_io_bits(void __iomem *addr, u32 bits)
202 {
203 u32 v = readl(addr);
204
205 v |= bits;
206 writel(v, addr);
207 }
208
clear_io_bits(void __iomem * addr,u32 bits)209 static inline void clear_io_bits(void __iomem *addr, u32 bits)
210 {
211 u32 v = readl(addr);
212
213 v &= ~bits;
214 writel(v, addr);
215 }
216
217 /*
218 * Interface to control the chip select signal
219 */
davinci_spi_chipselect(struct rt_spi_device * spi,int value)220 static void davinci_spi_chipselect(struct rt_spi_device *spi, int value)
221 {
222 struct davinci_spi *dspi;
223 u8 chip_sel = (u8)spi->parent.user_data;
224 u16 spidat1 = CS_DEFAULT;
225 bool gpio_chipsel = RT_FALSE;
226
227 dspi = spi->bus->parent.user_data;
228
229 if (chip_sel < SPI_MAX_CHIPSELECT &&
230 dspi->chip_sel[chip_sel] != SPI_INTERN_CS)
231 gpio_chipsel = RT_TRUE;
232
233 /*
234 * Board specific chip select logic decides the polarity and cs
235 * line for the controller
236 */
237 if (gpio_chipsel) {
238 if (value == 0)
239 gpio_set_value(dspi->chip_sel[chip_sel], 0);
240 else
241 gpio_set_value(dspi->chip_sel[chip_sel], 1);
242 } else {
243 spidat1 = readw(dspi->base + SPIDAT1 + 2);
244 if (value == 0) {
245 spidat1 |= SPIDAT1_CSHOLD_MASK;
246 spidat1 &= ~(0x1 << chip_sel);
247 } else {
248 spidat1 &= ~SPIDAT1_CSHOLD_MASK;
249 spidat1 |= 0x03;
250 }
251 rt_kprintf("0x%04x\n", spidat1);
252
253 writew(spidat1, dspi->base + SPIDAT1 + 2);
254 }
255 }
256
257 /**
258 * davinci_spi_get_prescale - Calculates the correct prescale value
259 * @maxspeed_hz: the maximum rate the SPI clock can run at
260 *
261 * This function calculates the prescale value that generates a clock rate
262 * less than or equal to the specified maximum.
263 *
264 * Returns: calculated prescale - 1 for easy programming into SPI registers
265 * or negative error number if valid prescalar cannot be updated.
266 */
davinci_spi_get_prescale(struct davinci_spi * dspi,u32 max_speed_hz)267 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
268 u32 max_speed_hz)
269 {
270 int ret;
271
272 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
273
274 if (ret < 3) {
275 rt_kprintf("spi clock freq too high\n");
276 ret = 3;
277 }
278 if (ret > 256) {
279 rt_kprintf("spi clock freq too litter\n");
280 ret = 256;
281 }
282
283 /*if (ret < 3 || ret > 256)
284 return -RT_ERROR;*/
285
286 return ret - 1;
287 }
288
289 /**
290 * davinci_spi_setup_transfer - This functions will determine transfer method
291 * @spi: spi device on which data transfer to be done
292 * @t: spi transfer in which transfer info is filled
293 *
294 * This function determines data transfer method (8/16/32 bit transfer).
295 * It will also set the SPI Clock Control register according to
296 * SPI slave device freq.
297 */
davinci_spi_setup_transfer(struct rt_spi_device * spi,struct rt_spi_configuration * cfg)298 static int davinci_spi_setup_transfer(struct rt_spi_device *spi,
299 struct rt_spi_configuration *cfg)
300 {
301
302 struct davinci_spi *dspi;
303 struct davinci_spi_config *spicfg;
304 u8 bits_per_word = 0;
305 u32 hz = 0, spifmt = 0, prescale = 0;
306 u8 chip_select = (u8)spi->parent.user_data;
307
308 dspi = spi->bus->parent.user_data;
309 spicfg = (struct davinci_spi_config *)dspi->controller_data;
310 if (!spicfg)
311 spicfg = &davinci_spi_default_cfg;
312
313 bits_per_word = cfg->data_width;
314 hz = cfg->max_hz;
315
316 /*
317 * Assign function pointer to appropriate transfer method
318 * 8bit, 16bit or 32bit transfer
319 */
320 if (bits_per_word <= 8 && bits_per_word >= 2) {
321 dspi->get_rx = davinci_spi_rx_buf_u8;
322 dspi->get_tx = davinci_spi_tx_buf_u8;
323 dspi->bytes_per_word[chip_select] = 1;
324 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
325 dspi->get_rx = davinci_spi_rx_buf_u16;
326 dspi->get_tx = davinci_spi_tx_buf_u16;
327 dspi->bytes_per_word[chip_select] = 2;
328 } else
329 return -RT_ERROR;
330
331 /* Set up SPIFMTn register, unique to this chipselect. */
332
333 prescale = davinci_spi_get_prescale(dspi, hz);
334 if (prescale < 0)
335 return prescale;
336
337 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
338
339 if (!(cfg->mode & RT_SPI_MSB))
340 spifmt |= SPIFMT_SHIFTDIR_MASK;
341
342 if (cfg->mode & RT_SPI_CPOL)
343 spifmt |= SPIFMT_POLARITY_MASK;
344
345 if (!(cfg->mode & RT_SPI_CPHA))
346 spifmt |= SPIFMT_PHASE_MASK;
347
348 /*
349 * Version 1 hardware supports two basic SPI modes:
350 * - Standard SPI mode uses 4 pins, with chipselect
351 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
352 * (distinct from SPI_3WIRE, with just one data wire;
353 * or similar variants without MOSI or without MISO)
354 *
355 * Version 2 hardware supports an optional handshaking signal,
356 * so it can support two more modes:
357 * - 5 pin SPI variant is standard SPI plus SPI_READY
358 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
359 */
360
361 if (dspi->version == SPI_VERSION_2) {
362
363 u32 delay = 0;
364
365 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
366 & SPIFMT_WDELAY_MASK);
367
368 if (spicfg->odd_parity)
369 spifmt |= SPIFMT_ODD_PARITY_MASK;
370
371 if (spicfg->parity_enable)
372 spifmt |= SPIFMT_PARITYENA_MASK;
373
374 if (spicfg->timer_disable) {
375 spifmt |= SPIFMT_DISTIMER_MASK;
376 } else {
377 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
378 & SPIDELAY_C2TDELAY_MASK;
379 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
380 & SPIDELAY_T2CDELAY_MASK;
381 }
382
383 if (cfg->mode & RT_SPI_READY) {
384 spifmt |= SPIFMT_WAITENA_MASK;
385 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
386 & SPIDELAY_T2EDELAY_MASK;
387 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
388 & SPIDELAY_C2EDELAY_MASK;
389 }
390
391 writel(delay, dspi->base + SPIDELAY);
392 }
393
394 writel(spifmt, dspi->base + SPIFMT0);
395
396 return 0;
397 }
398
399 #if 0
400 /**
401 * davinci_spi_setup - This functions will set default transfer method
402 * @spi: spi device on which data transfer to be done
403 *
404 * This functions sets the default transfer method.
405 */
406 static int davinci_spi_setup(struct spi_device *spi)
407 {
408 int retval = 0;
409 struct davinci_spi *dspi;
410 struct davinci_spi_platform_data *pdata;
411
412 dspi = spi_master_get_devdata(spi->master);
413 pdata = dspi->pdata;
414
415 /* if bits per word length is zero then set it default 8 */
416 if (!spi->bits_per_word)
417 spi->bits_per_word = 8;
418
419 if (!(spi->mode & SPI_NO_CS)) {
420 if ((pdata->chip_sel == NULL) ||
421 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
422 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
423
424 }
425
426 if (spi->mode & SPI_READY)
427 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
428
429 if (spi->mode & SPI_LOOP)
430 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
431 else
432 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
433
434 return retval;
435 }
436 #endif
437
davinci_spi_check_error(struct davinci_spi * dspi,int int_status)438 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
439 {
440 struct rt_device *sdev = &dspi->parent.parent;
441
442 if (int_status & SPIFLG_TIMEOUT_MASK) {
443 spi_dbg(sdev, "SPI Time-out Error\n");
444 return -RT_ETIMEOUT;
445 }
446 if (int_status & SPIFLG_DESYNC_MASK) {
447 spi_dbg(sdev, "SPI Desynchronization Error\n");
448 return -RT_EIO;
449 }
450 if (int_status & SPIFLG_BITERR_MASK) {
451 spi_dbg(sdev, "SPI Bit error\n");
452 return -RT_EIO;
453 }
454
455 if (dspi->version == SPI_VERSION_2) {
456 if (int_status & SPIFLG_DLEN_ERR_MASK) {
457 spi_dbg(sdev, "SPI Data Length Error\n");
458 return -RT_EIO;
459 }
460 if (int_status & SPIFLG_PARERR_MASK) {
461 spi_dbg(sdev, "SPI Parity Error\n");
462 return -RT_EIO;
463 }
464 if (int_status & SPIFLG_OVRRUN_MASK) {
465 spi_dbg(sdev, "SPI Data Overrun error\n");
466 return -RT_EIO;
467 }
468 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
469 spi_dbg(sdev, "SPI Buffer Init Active\n");
470 return -RT_EBUSY;
471 }
472 }
473
474 return 0;
475 }
476
477 /**
478 * davinci_spi_process_events - check for and handle any SPI controller events
479 * @dspi: the controller data
480 *
481 * This function will check the SPIFLG register and handle any events that are
482 * detected there
483 */
davinci_spi_process_events(struct davinci_spi * dspi)484 static int davinci_spi_process_events(struct davinci_spi *dspi)
485 {
486 u32 buf, status, errors = 0, spidat1;
487
488 buf = readl(dspi->base + SPIBUF);
489
490 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
491 dspi->get_rx(buf & 0xFFFF, dspi);
492 dspi->rcount--;
493 }
494
495 status = readl(dspi->base + SPIFLG);
496
497 if (unlikely(status & SPIFLG_ERROR_MASK)) {
498 errors = status & SPIFLG_ERROR_MASK;
499 goto out;
500 }
501
502 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
503 spidat1 = readl(dspi->base + SPIDAT1);
504 dspi->wcount--;
505 spidat1 &= ~0xFFFF;
506 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
507 writel(spidat1, dspi->base + SPIDAT1);
508 }
509
510 out:
511 return errors;
512 }
513
davinci_spi_dma_callback(unsigned lch,u16 status,void * data)514 static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
515 {
516 struct davinci_spi *dspi = data;
517 struct davinci_spi_dma *dma = &dspi->dma;
518
519 edma_stop(lch);
520
521 if (status == DMA_COMPLETE) {
522 if (lch == dma->rx_channel)
523 dspi->rcount = 0;
524 if (lch == dma->tx_channel)
525 dspi->wcount = 0;
526 }
527
528 if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE))
529 rt_completion_done(&dspi->done);
530 }
531
532 /**
533 * davinci_spi_bufs - functions which will handle transfer data
534 * @spi: spi device on which data transfer to be done
535 * @t: spi transfer in which transfer info is filled
536 *
537 * This function will put data to be transferred into data register
538 * of SPI controller and then wait until the completion will be marked
539 * by the IRQ Handler.
540 */
davinci_spi_bufs(struct rt_spi_device * spi,struct rt_spi_message * msg)541 static int davinci_spi_bufs(struct rt_spi_device *spi, struct rt_spi_message *msg)
542 {
543 struct davinci_spi *dspi;
544 int data_type, ret;
545 u32 tx_data, spidat1;
546 u32 errors = 0;
547 struct davinci_spi_config *spicfg;
548 unsigned rx_buf_count;
549 struct rt_device *sdev;
550 u8 chip_select = (u8)spi->parent.user_data;
551
552 dspi = spi->bus->parent.user_data;
553 spicfg = (struct davinci_spi_config *)dspi->controller_data;
554 if (!spicfg)
555 spicfg = &davinci_spi_default_cfg;
556 sdev = &dspi->parent.parent;
557
558 /* convert len to words based on bits_per_word */
559 data_type = dspi->bytes_per_word[chip_select];
560
561 dspi->tx = msg->send_buf;
562 dspi->rx = msg->recv_buf;
563 dspi->wcount = msg->length / data_type;
564 dspi->rcount = dspi->wcount;
565
566 spidat1 = readl(dspi->base + SPIDAT1);
567
568 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
569 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
570
571 rt_completion_init(&(dspi->done));
572
573 if (msg->cs_take)
574 davinci_spi_chipselect(spi, 0);
575
576 if (spicfg->io_type == SPI_IO_TYPE_INTR)
577 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
578
579 if (msg->length > 0) {
580 if (spicfg->io_type != SPI_IO_TYPE_DMA) {
581 /* start the transfer */
582 dspi->wcount--;
583 tx_data = dspi->get_tx(dspi);
584 spidat1 &= 0xFFFF0000;
585 spidat1 |= tx_data & 0xFFFF;
586 writel(spidat1, dspi->base + SPIDAT1);
587 } else {
588 struct davinci_spi_dma *dma;
589 unsigned long tx_reg, rx_reg;
590 struct edmacc_param param;
591 void *rx_buf;
592 int b, c;
593
594 dma = &dspi->dma;
595
596 tx_reg = (unsigned long)dspi->base + SPIDAT1;
597 rx_reg = (unsigned long)dspi->base + SPIBUF;
598
599 /*
600 * Transmit DMA setup
601 *
602 * If there is transmit data, map the transmit buffer, set it
603 * as the source of data and set the source B index to data
604 * size. If there is no transmit data, set the transmit register
605 * as the source of data, and set the source B index to zero.
606 *
607 * The destination is always the transmit register itself. And
608 * the destination never increments.
609 */
610
611 if (msg->send_buf) {
612 mmu_clean_dcache((rt_uint32_t)msg->send_buf, (rt_uint32_t)msg->length);
613 }
614
615 /*
616 * If number of words is greater than 65535, then we need
617 * to configure a 3 dimension transfer. Use the BCNTRLD
618 * feature to allow for transfers that aren't even multiples
619 * of 65535 (or any other possible b size) by first transferring
620 * the remainder amount then grabbing the next N blocks of
621 * 65535 words.
622 */
623
624 c = dspi->wcount / (SZ_64K - 1); /* N 65535 Blocks */
625 b = dspi->wcount - c * (SZ_64K - 1); /* Remainder */
626 if (b)
627 c++;
628 else
629 b = SZ_64K - 1;
630
631 param.opt = TCINTEN | EDMA_TCC(dma->tx_channel);
632 param.src = msg->send_buf ? msg->send_buf : tx_reg;
633 param.a_b_cnt = b << 16 | data_type;
634 param.dst = tx_reg;
635 param.src_dst_bidx = msg->send_buf ? data_type : 0;
636 param.link_bcntrld = 0xffffffff;
637 param.src_dst_cidx = msg->send_buf ? data_type : 0;
638 param.ccnt = c;
639 edma_write_slot(dma->tx_channel, ¶m);
640 edma_link(dma->tx_channel, dma->dummy_param_slot);
641
642 /*
643 * Receive DMA setup
644 *
645 * If there is receive buffer, use it to receive data. If there
646 * is none provided, use a temporary receive buffer. Set the
647 * destination B index to 0 so effectively only one byte is used
648 * in the temporary buffer (address does not increment).
649 *
650 * The source of receive data is the receive data register. The
651 * source address never increments.
652 */
653
654 if (msg->recv_buf) {
655 rx_buf = msg->recv_buf;
656 rx_buf_count = msg->length;
657 } else {
658 rx_buf = dspi->rx_tmp_buf;
659 rx_buf_count = sizeof(dspi->rx_tmp_buf);
660 }
661
662 mmu_invalidate_dcache((rt_uint32_t)rx_buf, (rt_uint32_t)rx_buf_count);
663
664 param.opt = TCINTEN | EDMA_TCC(dma->rx_channel);
665 param.src = rx_reg;
666 param.a_b_cnt = b << 16 | data_type;
667 param.dst = rx_buf;
668 param.src_dst_bidx = (msg->recv_buf ? data_type : 0) << 16;
669 param.link_bcntrld = 0xffffffff;
670 param.src_dst_cidx = (msg->recv_buf ? data_type : 0) << 16;
671 param.ccnt = c;
672 edma_write_slot(dma->rx_channel, ¶m);
673
674 if (dspi->cshold_bug)
675 writew(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
676
677 edma_start(dma->rx_channel);
678 edma_start(dma->tx_channel);
679 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
680 }
681
682 /* Wait for the transfer to complete */
683 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
684 rt_completion_wait(&(dspi->done), RT_WAITING_FOREVER);
685 } else {
686 while (dspi->rcount > 0 || dspi->wcount > 0) {
687 errors = davinci_spi_process_events(dspi);
688 if (errors)
689 break;
690 cpu_relax();
691 }
692 }
693 }
694
695 if (msg->cs_release)
696 davinci_spi_chipselect(spi, 1);
697
698 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
699 if (spicfg->io_type == SPI_IO_TYPE_DMA) {
700 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
701 }
702
703 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
704 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
705
706 /*
707 * Check for bit error, desync error,parity error,timeout error and
708 * receive overflow errors
709 */
710 if (errors) {
711 ret = davinci_spi_check_error(dspi, errors);
712 rt_kprintf("%s: error reported but no error found!\n",
713 spi->bus->parent.parent.name);
714 return ret;
715 }
716
717 if (dspi->rcount != 0 || dspi->wcount != 0) {
718 spi_dbg(sdev, "SPI data transfer error\n");
719 return -RT_EIO;
720 }
721
722 return msg->length;
723 }
724
725 /**
726 * davinci_spi_irq - Interrupt handler for SPI Master Controller
727 * @irq: IRQ number for this SPI Master
728 * @context_data: structure for SPI Master controller davinci_spi
729 *
730 * ISR will determine that interrupt arrives either for READ or WRITE command.
731 * According to command it will do the appropriate action. It will check
732 * transfer length and if it is not zero then dispatch transfer command again.
733 * If transfer length is zero then it will indicate the COMPLETION so that
734 * davinci_spi_bufs function can go ahead.
735 */
davinci_spi_irq(int irq,void * data)736 static void davinci_spi_irq(int irq, void *data)
737 {
738 struct davinci_spi *dspi = data;
739 int status;
740
741 status = davinci_spi_process_events(dspi);
742 if (unlikely(status != 0))
743 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
744
745 if ((!dspi->rcount && !dspi->wcount) || status)
746 rt_completion_done(&dspi->done);
747 }
748
davinci_spi_request_dma(struct davinci_spi * dspi)749 static int davinci_spi_request_dma(struct davinci_spi *dspi)
750 {
751 int r;
752 struct davinci_spi_dma *dma = &dspi->dma;
753
754 r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi,
755 dma->eventq);
756 if (r < 0) {
757 rt_kprintf("Unable to request DMA channel for SPI RX\n");
758 r = -RT_EFULL;
759 goto rx_dma_failed;
760 }
761
762 r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi,
763 dma->eventq);
764 if (r < 0) {
765 rt_kprintf("Unable to request DMA channel for SPI TX\n");
766 r = -RT_EFULL;
767 goto tx_dma_failed;
768 }
769
770 r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY);
771 if (r < 0) {
772 rt_kprintf("Unable to request SPI TX DMA param slot\n");
773 r = -RT_EFULL;
774 goto param_failed;
775 }
776 dma->dummy_param_slot = r;
777 edma_link(dma->dummy_param_slot, dma->dummy_param_slot);
778
779 return 0;
780 param_failed:
781 edma_free_channel(dma->tx_channel);
782 tx_dma_failed:
783 edma_free_channel(dma->rx_channel);
784 rx_dma_failed:
785 return r;
786 }
787
configure(struct rt_spi_device * device,struct rt_spi_configuration * configuration)788 static rt_err_t configure(struct rt_spi_device *device,
789 struct rt_spi_configuration *configuration)
790 {
791 return davinci_spi_setup_transfer(device, configuration);
792 }
793
xfer(struct rt_spi_device * device,struct rt_spi_message * message)794 static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message)
795 {
796 return davinci_spi_bufs(device, message);
797 };
798
799
800
801 static struct rt_spi_ops davinci_spi_ops =
802 {
803 configure,
804 xfer
805 };
806
udelay(volatile rt_uint32_t us)807 static void udelay (volatile rt_uint32_t us)
808 {
809 volatile rt_int32_t i;
810 for (; us > 0; us--)
811 {
812 i = 5000;
813 while(i > 0)
814 {
815 i--;
816 }
817 }
818 }
819
spi_pin_cfg(void)820 void spi_pin_cfg(void)
821 {
822 rt_uint32_t val;
823
824 val = davinci_readl(PINMUX3);
825 val |= 0x80000000; /* SPI1 */
826 davinci_writel(val, PINMUX3);
827
828 val = davinci_readl(PINMUX4);
829 val &= 0xffffffc0; /* SPI1 */
830 val |= 0x05;//0x00000015; /* SPI1 */
831 davinci_writel(val, PINMUX4);
832 }
833
834 /**
835 * davinci_spi_probe - probe function for SPI Master Controller
836 * @pdev: platform_device structure which contains plateform specific data
837 *
838 * According to Linux Device Model this function will be invoked by Linux
839 * with platform_device struct which contains the device specific info.
840 * This function will map the SPI controller's memory, register IRQ,
841 * Reset SPI controller and setting its registers to default value.
842 * It will invoke spi_bitbang_start to create work queue so that client driver
843 * can register transfer method to work queue.
844 */
davinci_spi_probe(struct davinci_spi * dspi,char * spi_bus_name)845 static int davinci_spi_probe(struct davinci_spi *dspi, char *spi_bus_name)
846 {
847 int i = 0, ret = 0;
848 u32 spipc0;
849
850 spi_pin_cfg();
851 psc_change_state(DAVINCI_DM365_LPSC_SPI1, PSC_ENABLE);
852
853 dspi->base = DM3XX_SPI1_BASE;//spi;
854
855 dspi->irq = IRQ_DM3XX_SPINT1_0;
856
857 rt_hw_interrupt_install(dspi->irq, davinci_spi_irq, dspi, spi_bus_name);
858 rt_hw_interrupt_umask(dspi->irq);
859
860 dspi->clk = clk_get("SPICLK");
861
862 dspi->version = SPI_VERSION_1;
863 dspi->chip_sel[0] = 29;//SPI_INTERN_CS;
864 dspi->chip_sel[1] = 0;//GPIO0
865
866 dspi->dma.rx_channel = 15;
867 dspi->dma.tx_channel = 14;
868 dspi->dma.eventq = EVENTQ_3;
869
870 ret = davinci_spi_request_dma(dspi);
871 if (ret)
872 goto err;
873
874 rt_kprintf("%s: DMA: supported\n", spi_bus_name);
875 rt_kprintf("%s: DMA: RX channel: %d, TX channel: %d, "
876 "event queue: %d\n", spi_bus_name, dspi->dma.rx_channel,
877 dspi->dma.tx_channel, dspi->dma.eventq);
878
879 dspi->get_rx = davinci_spi_rx_buf_u8;
880 dspi->get_tx = davinci_spi_tx_buf_u8;
881
882 rt_completion_init(&dspi->done);
883
884 /* Reset In/OUT SPI module */
885 writel(0, dspi->base + SPIGCR0);
886 udelay(100);
887 writel(1, dspi->base + SPIGCR0);
888
889 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
890 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
891 writel(spipc0, dspi->base + SPIPC0);
892
893 /* initialize chip selects */
894 for (i = 0; i < SPI_MAX_CHIPSELECT; i++) {
895 if (dspi->chip_sel[i] != SPI_INTERN_CS)
896 gpio_direction_output(dspi->chip_sel[i], 1);
897 }
898
899 if (0)
900 writel(SPI_INTLVL_1, dspi->base + SPILVL);
901 else
902 writel(SPI_INTLVL_0, dspi->base + SPILVL);
903
904 writel(CS_DEFAULT, dspi->base + SPIDEF);
905
906 /* master mode default */
907 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
908 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
909 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
910
911 //set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);//LOOP BACK mode
912
913 rt_kprintf("%s: Controller at 0x%p\n", spi_bus_name, dspi->base);
914
915 dspi->parent.parent.user_data = dspi;
916
917 return rt_spi_bus_register(&dspi->parent, spi_bus_name, &davinci_spi_ops);
918
919 return ret;
920
921 free_dma:
922 edma_free_channel(dspi->dma.tx_channel);
923 edma_free_channel(dspi->dma.rx_channel);
924 edma_free_slot(dspi->dma.dummy_param_slot);
925
926 err:
927 return ret;
928 }
929
930
rt_hw_spi_init(void)931 int rt_hw_spi_init(void)
932 {
933 /* register spi bus */
934 {
935 static struct davinci_spi dspi;
936 rt_memset(&dspi, 0, sizeof(dspi));
937 davinci_spi_probe(&dspi, "spi1");
938 }
939 /* attach cs */
940 {
941 static struct rt_spi_device spi_device;
942 rt_spi_bus_attach_device(&spi_device, "spi10", "spi1", (void *)0);
943 }
944 {
945 static struct rt_spi_device spi_device;
946 rt_spi_bus_attach_device(&spi_device, "spi11", "spi1", (void *)1);
947 }
948
949 return 0;
950 }
951
952 INIT_DEVICE_EXPORT(rt_hw_spi_init);
953
954